| Line Number |
../DebugInfoTest/example_mips_dbg.ll
BUT NOT
../DebugInfoTest/example_mips.ll
|
Line Number |
../DebugInfoTest/example_mips.ll
BUT NOT
../DebugInfoTest/example_mips_dbg.ll
|
| 1 |
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
1 |
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 2 |
|* *| |
2 |
|* *| |
| 3 |
|* Assembly Writer Source Fragment *| |
3 |
|* Assembly Writer Source Fragment *| |
| 4 |
|* *| |
4 |
|* *| |
| 5 |
|* Automatically generated file, do not edit! *| |
5 |
|* Automatically generated file, do not edit! *| |
| 6 |
|* *| |
6 |
|* *| |
| 7 |
\*===----------------------------------------------------------------------===*/ |
7 |
\*===----------------------------------------------------------------------===*/ |
| 8 |
|
8 |
|
| 9 |
/// getMnemonic - This method is automatically generated by tablegen |
9 |
/// getMnemonic - This method is automatically generated by tablegen |
| 10 |
/// from the instruction set description. |
10 |
/// from the instruction set description. |
| 11 |
std::pair MipsInstPrinter::getMnemonic(const MCInst *MI) { |
11 |
std::pair MipsInstPrinter::getMnemonic(const MCInst *MI) { |
| 12 |
|
12 |
|
| 13 |
#ifdef __GNUC__ |
13 |
#ifdef __GNUC__ |
| 14 |
#pragma GCC diagnostic push |
14 |
#pragma GCC diagnostic push |
| 15 |
#pragma GCC diagnostic ignored "-Woverlength-strings" |
15 |
#pragma GCC diagnostic ignored "-Woverlength-strings" |
| 16 |
#endif |
16 |
#endif |
| 17 |
static const char AsmStrs[] = { |
17 |
static const char AsmStrs[] = { |
| 18 |
/* 0 */ "dmfc0\t\0" |
18 |
/* 0 */ "dmfc0\t\0" |
| 19 |
/* 7 */ "dmfgc0\t\0" |
19 |
/* 7 */ "dmfgc0\t\0" |
| 20 |
/* 15 */ "mfhgc0\t\0" |
20 |
/* 15 */ "mfhgc0\t\0" |
| 21 |
/* 23 */ "mthgc0\t\0" |
21 |
/* 23 */ "mthgc0\t\0" |
| 22 |
/* 31 */ "dmtgc0\t\0" |
22 |
/* 31 */ "dmtgc0\t\0" |
| 23 |
/* 39 */ "mfhc0\t\0" |
23 |
/* 39 */ "mfhc0\t\0" |
| 24 |
/* 46 */ "mthc0\t\0" |
24 |
/* 46 */ "mthc0\t\0" |
| 25 |
/* 53 */ "dmtc0\t\0" |
25 |
/* 53 */ "dmtc0\t\0" |
| 26 |
/* 60 */ "vmm0\t\0" |
26 |
/* 60 */ "vmm0\t\0" |
| 27 |
/* 66 */ "mtm0\t\0" |
27 |
/* 66 */ "mtm0\t\0" |
| 28 |
/* 72 */ "mtp0\t\0" |
28 |
/* 72 */ "mtp0\t\0" |
| 29 |
/* 78 */ "bbit0\t\0" |
29 |
/* 78 */ "bbit0\t\0" |
| 30 |
/* 85 */ "ldc1\t\0" |
30 |
/* 85 */ "ldc1\t\0" |
| 31 |
/* 91 */ "sdc1\t\0" |
31 |
/* 91 */ "sdc1\t\0" |
| 32 |
/* 97 */ "cfc1\t\0" |
32 |
/* 97 */ "cfc1\t\0" |
| 33 |
/* 103 */ "dmfc1\t\0" |
33 |
/* 103 */ "dmfc1\t\0" |
| 34 |
/* 110 */ "mfhc1\t\0" |
34 |
/* 110 */ "mfhc1\t\0" |
| 35 |
/* 117 */ "mthc1\t\0" |
35 |
/* 117 */ "mthc1\t\0" |
| 36 |
/* 124 */ "ctc1\t\0" |
36 |
/* 124 */ "ctc1\t\0" |
| 37 |
/* 130 */ "dmtc1\t\0" |
37 |
/* 130 */ "dmtc1\t\0" |
| 38 |
/* 137 */ "lwc1\t\0" |
38 |
/* 137 */ "lwc1\t\0" |
| 39 |
/* 143 */ "swc1\t\0" |
39 |
/* 143 */ "swc1\t\0" |
| 40 |
/* 149 */ "ldxc1\t\0" |
40 |
/* 149 */ "ldxc1\t\0" |
| 41 |
/* 156 */ "sdxc1\t\0" |
41 |
/* 156 */ "sdxc1\t\0" |
| 42 |
/* 163 */ "luxc1\t\0" |
42 |
/* 163 */ "luxc1\t\0" |
| 43 |
/* 170 */ "suxc1\t\0" |
43 |
/* 170 */ "suxc1\t\0" |
| 44 |
/* 177 */ "lwxc1\t\0" |
44 |
/* 177 */ "lwxc1\t\0" |
| 45 |
/* 184 */ "swxc1\t\0" |
45 |
/* 184 */ "swxc1\t\0" |
| 46 |
/* 191 */ "mtm1\t\0" |
46 |
/* 191 */ "mtm1\t\0" |
| 47 |
/* 197 */ "mtp1\t\0" |
47 |
/* 197 */ "mtp1\t\0" |
| 48 |
/* 203 */ "bbit1\t\0" |
48 |
/* 203 */ "bbit1\t\0" |
| 49 |
/* 210 */ "bbit032\t\0" |
49 |
/* 210 */ "bbit032\t\0" |
| 50 |
/* 219 */ "bbit132\t\0" |
50 |
/* 219 */ "bbit132\t\0" |
| 51 |
/* 228 */ "dsra32\t\0" |
51 |
/* 228 */ "dsra32\t\0" |
| 52 |
/* 236 */ "bposge32\t\0" |
52 |
/* 236 */ "bposge32\t\0" |
| 53 |
/* 246 */ "dsll32\t\0" |
53 |
/* 246 */ "dsll32\t\0" |
| 54 |
/* 254 */ "dsrl32\t\0" |
54 |
/* 254 */ "dsrl32\t\0" |
| 55 |
/* 262 */ "lwm32\t\0" |
55 |
/* 262 */ "lwm32\t\0" |
| 56 |
/* 269 */ "swm32\t\0" |
56 |
/* 269 */ "swm32\t\0" |
| 57 |
/* 276 */ "drotr32\t\0" |
57 |
/* 276 */ "drotr32\t\0" |
| 58 |
/* 285 */ "cins32\t\0" |
58 |
/* 285 */ "cins32\t\0" |
| 59 |
/* 293 */ "exts32\t\0" |
59 |
/* 293 */ "exts32\t\0" |
| 60 |
/* 301 */ "ldc2\t\0" |
60 |
/* 301 */ "ldc2\t\0" |
| 61 |
/* 307 */ "sdc2\t\0" |
61 |
/* 307 */ "sdc2\t\0" |
| 62 |
/* 313 */ "cfc2\t\0" |
62 |
/* 313 */ "cfc2\t\0" |
| 63 |
/* 319 */ "dmfc2\t\0" |
63 |
/* 319 */ "dmfc2\t\0" |
| 64 |
/* 326 */ "mfhc2\t\0" |
64 |
/* 326 */ "mfhc2\t\0" |
| 65 |
/* 333 */ "mthc2\t\0" |
65 |
/* 333 */ "mthc2\t\0" |
| 66 |
/* 340 */ "ctc2\t\0" |
66 |
/* 340 */ "ctc2\t\0" |
| 67 |
/* 346 */ "dmtc2\t\0" |
67 |
/* 346 */ "dmtc2\t\0" |
| 68 |
/* 353 */ "lwc2\t\0" |
68 |
/* 353 */ "lwc2\t\0" |
| 69 |
/* 359 */ "swc2\t\0" |
69 |
/* 359 */ "swc2\t\0" |
| 70 |
/* 365 */ "mtm2\t\0" |
70 |
/* 365 */ "mtm2\t\0" |
| 71 |
/* 371 */ "mtp2\t\0" |
71 |
/* 371 */ "mtp2\t\0" |
| 72 |
/* 377 */ "addiur2\t\0" |
72 |
/* 377 */ "addiur2\t\0" |
| 73 |
/* 386 */ "ldc3\t\0" |
73 |
/* 386 */ "ldc3\t\0" |
| 74 |
/* 392 */ "sdc3\t\0" |
74 |
/* 392 */ "sdc3\t\0" |
| 75 |
/* 398 */ "lwc3\t\0" |
75 |
/* 398 */ "lwc3\t\0" |
| 76 |
/* 404 */ "swc3\t\0" |
76 |
/* 404 */ "swc3\t\0" |
| 77 |
/* 410 */ "addius5\t\0" |
77 |
/* 410 */ "addius5\t\0" |
| 78 |
/* 419 */ "sb16\t\0" |
78 |
/* 419 */ "sb16\t\0" |
| 79 |
/* 425 */ "bc16\t\0" |
79 |
/* 425 */ "bc16\t\0" |
| 80 |
/* 431 */ "jrc16\t\0" |
80 |
/* 431 */ "jrc16\t\0" |
| 81 |
/* 438 */ "bnezc16\t\0" |
81 |
/* 438 */ "bnezc16\t\0" |
| 82 |
/* 447 */ "beqzc16\t\0" |
82 |
/* 447 */ "beqzc16\t\0" |
| 83 |
/* 456 */ "and16\t\0" |
83 |
/* 456 */ "and16\t\0" |
| 84 |
/* 463 */ "move16\t\0" |
84 |
/* 463 */ "move16\t\0" |
| 85 |
/* 471 */ "sh16\t\0" |
85 |
/* 471 */ "sh16\t\0" |
| 86 |
/* 477 */ "andi16\t\0" |
86 |
/* 477 */ "andi16\t\0" |
| 87 |
/* 485 */ "mfhi16\t\0" |
87 |
/* 485 */ "mfhi16\t\0" |
| 88 |
/* 493 */ "li16\t\0" |
88 |
/* 493 */ "li16\t\0" |
| 89 |
/* 499 */ "break16\t\0" |
89 |
/* 499 */ "break16\t\0" |
| 90 |
/* 508 */ "sll16\t\0" |
90 |
/* 508 */ "sll16\t\0" |
| 91 |
/* 515 */ "srl16\t\0" |
91 |
/* 515 */ "srl16\t\0" |
| 92 |
/* 522 */ "lwm16\t\0" |
92 |
/* 522 */ "lwm16\t\0" |
| 93 |
/* 529 */ "swm16\t\0" |
93 |
/* 529 */ "swm16\t\0" |
| 94 |
/* 536 */ "mflo16\t\0" |
94 |
/* 536 */ "mflo16\t\0" |
| 95 |
/* 544 */ "sdbbp16\t\0" |
95 |
/* 544 */ "sdbbp16\t\0" |
| 96 |
/* 553 */ "jr16\t\0" |
96 |
/* 553 */ "jr16\t\0" |
| 97 |
/* 559 */ "xor16\t\0" |
97 |
/* 559 */ "xor16\t\0" |
| 98 |
/* 566 */ "jalrs16\t\0" |
98 |
/* 566 */ "jalrs16\t\0" |
| 99 |
/* 575 */ "not16\t\0" |
99 |
/* 575 */ "not16\t\0" |
| 100 |
/* 582 */ "lbu16\t\0" |
100 |
/* 582 */ "lbu16\t\0" |
| 101 |
/* 589 */ "subu16\t\0" |
101 |
/* 589 */ "subu16\t\0" |
| 102 |
/* 597 */ "addu16\t\0" |
102 |
/* 597 */ "addu16\t\0" |
| 103 |
/* 605 */ "lhu16\t\0" |
103 |
/* 605 */ "lhu16\t\0" |
| 104 |
/* 612 */ "lw16\t\0" |
104 |
/* 612 */ "lw16\t\0" |
| 105 |
/* 618 */ "sw16\t\0" |
105 |
/* 618 */ "sw16\t\0" |
| 106 |
/* 624 */ "bnez16\t\0" |
106 |
/* 624 */ "bnez16\t\0" |
| 107 |
/* 632 */ "beqz16\t\0" |
107 |
/* 632 */ "beqz16\t\0" |
| 108 |
/* 640 */ "saa\t\0" |
108 |
/* 640 */ "saa\t\0" |
| 109 |
/* 645 */ "preceu.ph.qbla\t\0" |
109 |
/* 645 */ "preceu.ph.qbla\t\0" |
| 110 |
/* 661 */ "precequ.ph.qbla\t\0" |
110 |
/* 661 */ "precequ.ph.qbla\t\0" |
| 111 |
/* 678 */ "dla\t\0" |
111 |
/* 678 */ "dla\t\0" |
| 112 |
/* 683 */ "preceu.ph.qbra\t\0" |
112 |
/* 683 */ "preceu.ph.qbra\t\0" |
| 113 |
/* 699 */ "precequ.ph.qbra\t\0" |
113 |
/* 699 */ "precequ.ph.qbra\t\0" |
| 114 |
/* 716 */ "dsra\t\0" |
114 |
/* 716 */ "dsra\t\0" |
| 115 |
/* 722 */ "dlsa\t\0" |
115 |
/* 722 */ "dlsa\t\0" |
| 116 |
/* 728 */ "cfcmsa\t\0" |
116 |
/* 728 */ "cfcmsa\t\0" |
| 117 |
/* 736 */ "ctcmsa\t\0" |
117 |
/* 736 */ "ctcmsa\t\0" |
| 118 |
/* 744 */ "add_a.b\t\0" |
118 |
/* 744 */ "add_a.b\t\0" |
| 119 |
/* 753 */ "min_a.b\t\0" |
119 |
/* 753 */ "min_a.b\t\0" |
| 120 |
/* 762 */ "adds_a.b\t\0" |
120 |
/* 762 */ "adds_a.b\t\0" |
| 121 |
/* 772 */ "max_a.b\t\0" |
121 |
/* 772 */ "max_a.b\t\0" |
| 122 |
/* 781 */ "sra.b\t\0" |
122 |
/* 781 */ "sra.b\t\0" |
| 123 |
/* 788 */ "nloc.b\t\0" |
123 |
/* 788 */ "nloc.b\t\0" |
| 124 |
/* 796 */ "nlzc.b\t\0" |
124 |
/* 796 */ "nlzc.b\t\0" |
| 125 |
/* 804 */ "sld.b\t\0" |
125 |
/* 804 */ "sld.b\t\0" |
| 126 |
/* 811 */ "pckod.b\t\0" |
126 |
/* 811 */ "pckod.b\t\0" |
| 127 |
/* 820 */ "ilvod.b\t\0" |
127 |
/* 820 */ "ilvod.b\t\0" |
| 128 |
/* 829 */ "insve.b\t\0" |
128 |
/* 829 */ "insve.b\t\0" |
| 129 |
/* 838 */ "vshf.b\t\0" |
129 |
/* 838 */ "vshf.b\t\0" |
| 130 |
/* 846 */ "bneg.b\t\0" |
130 |
/* 846 */ "bneg.b\t\0" |
| 131 |
/* 854 */ "srai.b\t\0" |
131 |
/* 854 */ "srai.b\t\0" |
| 132 |
/* 862 */ "sldi.b\t\0" |
132 |
/* 862 */ "sldi.b\t\0" |
| 133 |
/* 870 */ "andi.b\t\0" |
133 |
/* 870 */ "andi.b\t\0" |
| 134 |
/* 878 */ "bnegi.b\t\0" |
134 |
/* 878 */ "bnegi.b\t\0" |
| 135 |
/* 887 */ "bseli.b\t\0" |
135 |
/* 887 */ "bseli.b\t\0" |
| 136 |
/* 896 */ "slli.b\t\0" |
136 |
/* 896 */ "slli.b\t\0" |
| 137 |
/* 904 */ "srli.b\t\0" |
137 |
/* 904 */ "srli.b\t\0" |
| 138 |
/* 912 */ "binsli.b\t\0" |
138 |
/* 912 */ "binsli.b\t\0" |
| 139 |
/* 922 */ "ceqi.b\t\0" |
139 |
/* 922 */ "ceqi.b\t\0" |
| 140 |
/* 930 */ "srari.b\t\0" |
140 |
/* 930 */ "srari.b\t\0" |
| 141 |
/* 939 */ "bclri.b\t\0" |
141 |
/* 939 */ "bclri.b\t\0" |
| 142 |
/* 948 */ "srlri.b\t\0" |
142 |
/* 948 */ "srlri.b\t\0" |
| 143 |
/* 957 */ "nori.b\t\0" |
143 |
/* 957 */ "nori.b\t\0" |
| 144 |
/* 965 */ "xori.b\t\0" |
144 |
/* 965 */ "xori.b\t\0" |
| 145 |
/* 973 */ "binsri.b\t\0" |
145 |
/* 973 */ "binsri.b\t\0" |
| 146 |
/* 983 */ "splati.b\t\0" |
146 |
/* 983 */ "splati.b\t\0" |
| 147 |
/* 993 */ "bseti.b\t\0" |
147 |
/* 993 */ "bseti.b\t\0" |
| 148 |
/* 1002 */ "subvi.b\t\0" |
148 |
/* 1002 */ "subvi.b\t\0" |
| 149 |
/* 1011 */ "addvi.b\t\0" |
149 |
/* 1011 */ "addvi.b\t\0" |
| 150 |
/* 1020 */ "bmzi.b\t\0" |
150 |
/* 1020 */ "bmzi.b\t\0" |
| 151 |
/* 1028 */ "bmnzi.b\t\0" |
151 |
/* 1028 */ "bmnzi.b\t\0" |
| 152 |
/* 1037 */ "fill.b\t\0" |
152 |
/* 1037 */ "fill.b\t\0" |
| 153 |
/* 1045 */ "sll.b\t\0" |
153 |
/* 1045 */ "sll.b\t\0" |
| 154 |
/* 1052 */ "srl.b\t\0" |
154 |
/* 1052 */ "srl.b\t\0" |
| 155 |
/* 1059 */ "binsl.b\t\0" |
155 |
/* 1059 */ "binsl.b\t\0" |
| 156 |
/* 1068 */ "ilvl.b\t\0" |
156 |
/* 1068 */ "ilvl.b\t\0" |
| 157 |
/* 1076 */ "ceq.b\t\0" |
157 |
/* 1076 */ "ceq.b\t\0" |
| 158 |
/* 1083 */ "srar.b\t\0" |
158 |
/* 1083 */ "srar.b\t\0" |
| 159 |
/* 1091 */ "bclr.b\t\0" |
159 |
/* 1091 */ "bclr.b\t\0" |
| 160 |
/* 1099 */ "srlr.b\t\0" |
160 |
/* 1099 */ "srlr.b\t\0" |
| 161 |
/* 1107 */ "binsr.b\t\0" |
161 |
/* 1107 */ "binsr.b\t\0" |
| 162 |
/* 1116 */ "ilvr.b\t\0" |
162 |
/* 1116 */ "ilvr.b\t\0" |
| 163 |
/* 1124 */ "asub_s.b\t\0" |
163 |
/* 1124 */ "asub_s.b\t\0" |
| 164 |
/* 1134 */ "mod_s.b\t\0" |
164 |
/* 1134 */ "mod_s.b\t\0" |
| 165 |
/* 1143 */ "cle_s.b\t\0" |
165 |
/* 1143 */ "cle_s.b\t\0" |
| 166 |
/* 1152 */ "ave_s.b\t\0" |
166 |
/* 1152 */ "ave_s.b\t\0" |
| 167 |
/* 1161 */ "clei_s.b\t\0" |
167 |
/* 1161 */ "clei_s.b\t\0" |
| 168 |
/* 1171 */ "mini_s.b\t\0" |
168 |
/* 1171 */ "mini_s.b\t\0" |
| 169 |
/* 1181 */ "clti_s.b\t\0" |
169 |
/* 1181 */ "clti_s.b\t\0" |
| 170 |
/* 1191 */ "maxi_s.b\t\0" |
170 |
/* 1191 */ "maxi_s.b\t\0" |
| 171 |
/* 1201 */ "min_s.b\t\0" |
171 |
/* 1201 */ "min_s.b\t\0" |
| 172 |
/* 1210 */ "aver_s.b\t\0" |
172 |
/* 1210 */ "aver_s.b\t\0" |
| 173 |
/* 1220 */ "subs_s.b\t\0" |
173 |
/* 1220 */ "subs_s.b\t\0" |
| 174 |
/* 1230 */ "adds_s.b\t\0" |
174 |
/* 1230 */ "adds_s.b\t\0" |
| 175 |
/* 1240 */ "sat_s.b\t\0" |
175 |
/* 1240 */ "sat_s.b\t\0" |
| 176 |
/* 1249 */ "clt_s.b\t\0" |
176 |
/* 1249 */ "clt_s.b\t\0" |
| 177 |
/* 1258 */ "subsuu_s.b\t\0" |
177 |
/* 1258 */ "subsuu_s.b\t\0" |
| 178 |
/* 1270 */ "div_s.b\t\0" |
178 |
/* 1270 */ "div_s.b\t\0" |
| 179 |
/* 1279 */ "max_s.b\t\0" |
179 |
/* 1279 */ "max_s.b\t\0" |
| 180 |
/* 1288 */ "copy_s.b\t\0" |
180 |
/* 1288 */ "copy_s.b\t\0" |
| 181 |
/* 1298 */ "splat.b\t\0" |
181 |
/* 1298 */ "splat.b\t\0" |
| 182 |
/* 1307 */ "bset.b\t\0" |
182 |
/* 1307 */ "bset.b\t\0" |
| 183 |
/* 1315 */ "pcnt.b\t\0" |
183 |
/* 1315 */ "pcnt.b\t\0" |
| 184 |
/* 1323 */ "insert.b\t\0" |
184 |
/* 1323 */ "insert.b\t\0" |
| 185 |
/* 1333 */ "st.b\t\0" |
185 |
/* 1333 */ "st.b\t\0" |
| 186 |
/* 1339 */ "asub_u.b\t\0" |
186 |
/* 1339 */ "asub_u.b\t\0" |
| 187 |
/* 1349 */ "mod_u.b\t\0" |
187 |
/* 1349 */ "mod_u.b\t\0" |
| 188 |
/* 1358 */ "cle_u.b\t\0" |
188 |
/* 1358 */ "cle_u.b\t\0" |
| 189 |
/* 1367 */ "ave_u.b\t\0" |
189 |
/* 1367 */ "ave_u.b\t\0" |
| 190 |
/* 1376 */ "clei_u.b\t\0" |
190 |
/* 1376 */ "clei_u.b\t\0" |
| 191 |
/* 1386 */ "mini_u.b\t\0" |
191 |
/* 1386 */ "mini_u.b\t\0" |
| 192 |
/* 1396 */ "clti_u.b\t\0" |
192 |
/* 1396 */ "clti_u.b\t\0" |
| 193 |
/* 1406 */ "maxi_u.b\t\0" |
193 |
/* 1406 */ "maxi_u.b\t\0" |
| 194 |
/* 1416 */ "min_u.b\t\0" |
194 |
/* 1416 */ "min_u.b\t\0" |
| 195 |
/* 1425 */ "aver_u.b\t\0" |
195 |
/* 1425 */ "aver_u.b\t\0" |
| 196 |
/* 1435 */ "subs_u.b\t\0" |
196 |
/* 1435 */ "subs_u.b\t\0" |
| 197 |
/* 1445 */ "adds_u.b\t\0" |
197 |
/* 1445 */ "adds_u.b\t\0" |
| 198 |
/* 1455 */ "subsus_u.b\t\0" |
198 |
/* 1455 */ "subsus_u.b\t\0" |
| 199 |
/* 1467 */ "sat_u.b\t\0" |
199 |
/* 1467 */ "sat_u.b\t\0" |
| 200 |
/* 1476 */ "clt_u.b\t\0" |
200 |
/* 1476 */ "clt_u.b\t\0" |
| 201 |
/* 1485 */ "div_u.b\t\0" |
201 |
/* 1485 */ "div_u.b\t\0" |
| 202 |
/* 1494 */ "max_u.b\t\0" |
202 |
/* 1494 */ "max_u.b\t\0" |
| 203 |
/* 1503 */ "copy_u.b\t\0" |
203 |
/* 1503 */ "copy_u.b\t\0" |
| 204 |
/* 1513 */ "msubv.b\t\0" |
204 |
/* 1513 */ "msubv.b\t\0" |
| 205 |
/* 1522 */ "maddv.b\t\0" |
205 |
/* 1522 */ "maddv.b\t\0" |
| 206 |
/* 1531 */ "pckev.b\t\0" |
206 |
/* 1531 */ "pckev.b\t\0" |
| 207 |
/* 1540 */ "ilvev.b\t\0" |
207 |
/* 1540 */ "ilvev.b\t\0" |
| 208 |
/* 1549 */ "mulv.b\t\0" |
208 |
/* 1549 */ "mulv.b\t\0" |
| 209 |
/* 1557 */ "bz.b\t\0" |
209 |
/* 1557 */ "bz.b\t\0" |
| 210 |
/* 1563 */ "bnz.b\t\0" |
210 |
/* 1563 */ "bnz.b\t\0" |
| 211 |
/* 1570 */ "crc32b\t\0" |
211 |
/* 1570 */ "crc32b\t\0" |
| 212 |
/* 1578 */ "crc32cb\t\0" |
212 |
/* 1578 */ "crc32cb\t\0" |
| 213 |
/* 1587 */ "seb\t\0" |
213 |
/* 1587 */ "seb\t\0" |
| 214 |
/* 1592 */ "jalrc.hb\t\0" |
214 |
/* 1592 */ "jalrc.hb\t\0" |
| 215 |
/* 1602 */ "jr.hb\t\0" |
215 |
/* 1602 */ "jr.hb\t\0" |
| 216 |
/* 1609 */ "jalr.hb\t\0" |
216 |
/* 1609 */ "jalr.hb\t\0" |
| 217 |
/* 1618 */ "lb\t\0" |
217 |
/* 1618 */ "lb\t\0" |
| 218 |
/* 1622 */ "shra.qb\t\0" |
218 |
/* 1622 */ "shra.qb\t\0" |
| 219 |
/* 1631 */ "cmpgdu.le.qb\t\0" |
219 |
/* 1631 */ "cmpgdu.le.qb\t\0" |
| 220 |
/* 1645 */ "cmpgu.le.qb\t\0" |
220 |
/* 1645 */ "cmpgu.le.qb\t\0" |
| 221 |
/* 1658 */ "cmpu.le.qb\t\0" |
221 |
/* 1658 */ "cmpu.le.qb\t\0" |
| 222 |
/* 1670 */ "subuh.qb\t\0" |
222 |
/* 1670 */ "subuh.qb\t\0" |
| 223 |
/* 1680 */ "adduh.qb\t\0" |
223 |
/* 1680 */ "adduh.qb\t\0" |
| 224 |
/* 1690 */ "pick.qb\t\0" |
224 |
/* 1690 */ "pick.qb\t\0" |
| 225 |
/* 1699 */ "shll.qb\t\0" |
225 |
/* 1699 */ "shll.qb\t\0" |
| 226 |
/* 1708 */ "repl.qb\t\0" |
226 |
/* 1708 */ "repl.qb\t\0" |
| 227 |
/* 1717 */ "shrl.qb\t\0" |
227 |
/* 1717 */ "shrl.qb\t\0" |
| 228 |
/* 1726 */ "cmpgdu.eq.qb\t\0" |
228 |
/* 1726 */ "cmpgdu.eq.qb\t\0" |
| 229 |
/* 1740 */ "cmpgu.eq.qb\t\0" |
229 |
/* 1740 */ "cmpgu.eq.qb\t\0" |
| 230 |
/* 1753 */ "cmpu.eq.qb\t\0" |
230 |
/* 1753 */ "cmpu.eq.qb\t\0" |
| 231 |
/* 1765 */ "shra_r.qb\t\0" |
231 |
/* 1765 */ "shra_r.qb\t\0" |
| 232 |
/* 1776 */ "subuh_r.qb\t\0" |
232 |
/* 1776 */ "subuh_r.qb\t\0" |
| 233 |
/* 1788 */ "adduh_r.qb\t\0" |
233 |
/* 1788 */ "adduh_r.qb\t\0" |
| 234 |
/* 1800 */ "shrav_r.qb\t\0" |
234 |
/* 1800 */ "shrav_r.qb\t\0" |
| 235 |
/* 1812 */ "absq_s.qb\t\0" |
235 |
/* 1812 */ "absq_s.qb\t\0" |
| 236 |
/* 1823 */ "subu_s.qb\t\0" |
236 |
/* 1823 */ "subu_s.qb\t\0" |
| 237 |
/* 1834 */ "addu_s.qb\t\0" |
237 |
/* 1834 */ "addu_s.qb\t\0" |
| 238 |
/* 1845 */ "cmpgdu.lt.qb\t\0" |
238 |
/* 1845 */ "cmpgdu.lt.qb\t\0" |
| 239 |
/* 1859 */ "cmpgu.lt.qb\t\0" |
239 |
/* 1859 */ "cmpgu.lt.qb\t\0" |
| 240 |
/* 1872 */ "cmpu.lt.qb\t\0" |
240 |
/* 1872 */ "cmpu.lt.qb\t\0" |
| 241 |
/* 1884 */ "subu.qb\t\0" |
241 |
/* 1884 */ "subu.qb\t\0" |
| 242 |
/* 1893 */ "addu.qb\t\0" |
242 |
/* 1893 */ "addu.qb\t\0" |
| 243 |
/* 1902 */ "shrav.qb\t\0" |
243 |
/* 1902 */ "shrav.qb\t\0" |
| 244 |
/* 1912 */ "shllv.qb\t\0" |
244 |
/* 1912 */ "shllv.qb\t\0" |
| 245 |
/* 1922 */ "replv.qb\t\0" |
245 |
/* 1922 */ "replv.qb\t\0" |
| 246 |
/* 1932 */ "shrlv.qb\t\0" |
246 |
/* 1932 */ "shrlv.qb\t\0" |
| 247 |
/* 1942 */ "raddu.w.qb\t\0" |
247 |
/* 1942 */ "raddu.w.qb\t\0" |
| 248 |
/* 1954 */ "sb\t\0" |
248 |
/* 1954 */ "sb\t\0" |
| 249 |
/* 1958 */ "modsub\t\0" |
249 |
/* 1958 */ "modsub\t\0" |
| 250 |
/* 1966 */ "msub\t\0" |
250 |
/* 1966 */ "msub\t\0" |
| 251 |
/* 1972 */ "bposge32c\t\0" |
251 |
/* 1972 */ "bposge32c\t\0" |
| 252 |
/* 1983 */ "bc\t\0" |
252 |
/* 1983 */ "bc\t\0" |
| 253 |
/* 1987 */ "bgec\t\0" |
253 |
/* 1987 */ "bgec\t\0" |
| 254 |
/* 1993 */ "bnec\t\0" |
254 |
/* 1993 */ "bnec\t\0" |
| 255 |
/* 1999 */ "jic\t\0" |
255 |
/* 1999 */ "jic\t\0" |
| 256 |
/* 2004 */ "balc\t\0" |
256 |
/* 2004 */ "balc\t\0" |
| 257 |
/* 2010 */ "jialc\t\0" |
257 |
/* 2010 */ "jialc\t\0" |
| 258 |
/* 2017 */ "bgezalc\t\0" |
258 |
/* 2017 */ "bgezalc\t\0" |
| 259 |
/* 2026 */ "blezalc\t\0" |
259 |
/* 2026 */ "blezalc\t\0" |
| 260 |
/* 2035 */ "bnezalc\t\0" |
260 |
/* 2035 */ "bnezalc\t\0" |
| 261 |
/* 2044 */ "beqzalc\t\0" |
261 |
/* 2044 */ "beqzalc\t\0" |
| 262 |
/* 2053 */ "bgtzalc\t\0" |
262 |
/* 2053 */ "bgtzalc\t\0" |
| 263 |
/* 2062 */ "bltzalc\t\0" |
263 |
/* 2062 */ "bltzalc\t\0" |
| 264 |
/* 2071 */ "sync\t\0" |
264 |
/* 2071 */ "sync\t\0" |
| 265 |
/* 2077 */ "ldpc\t\0" |
265 |
/* 2077 */ "ldpc\t\0" |
| 266 |
/* 2083 */ "auipc\t\0" |
266 |
/* 2083 */ "auipc\t\0" |
| 267 |
/* 2090 */ "aluipc\t\0" |
267 |
/* 2090 */ "aluipc\t\0" |
| 268 |
/* 2098 */ "addiupc\t\0" |
268 |
/* 2098 */ "addiupc\t\0" |
| 269 |
/* 2107 */ "lwupc\t\0" |
269 |
/* 2107 */ "lwupc\t\0" |
| 270 |
/* 2114 */ "lwpc\t\0" |
270 |
/* 2114 */ "lwpc\t\0" |
| 271 |
/* 2120 */ "beqc\t\0" |
271 |
/* 2120 */ "beqc\t\0" |
| 272 |
/* 2126 */ "jrc\t\0" |
272 |
/* 2126 */ "jrc\t\0" |
| 273 |
/* 2131 */ "jalrc\t\0" |
273 |
/* 2131 */ "jalrc\t\0" |
| 274 |
/* 2138 */ "addsc\t\0" |
274 |
/* 2138 */ "addsc\t\0" |
| 275 |
/* 2145 */ "bltc\t\0" |
275 |
/* 2145 */ "bltc\t\0" |
| 276 |
/* 2151 */ "bgeuc\t\0" |
276 |
/* 2151 */ "bgeuc\t\0" |
| 277 |
/* 2158 */ "bltuc\t\0" |
277 |
/* 2158 */ "bltuc\t\0" |
| 278 |
/* 2165 */ "bnvc\t\0" |
278 |
/* 2165 */ "bnvc\t\0" |
| 279 |
/* 2171 */ "bovc\t\0" |
279 |
/* 2171 */ "bovc\t\0" |
| 280 |
/* 2177 */ "addwc\t\0" |
280 |
/* 2177 */ "addwc\t\0" |
| 281 |
/* 2184 */ "bgezc\t\0" |
281 |
/* 2184 */ "bgezc\t\0" |
| 282 |
/* 2191 */ "blezc\t\0" |
282 |
/* 2191 */ "blezc\t\0" |
| 283 |
/* 2198 */ "bc1nezc\t\0" |
283 |
/* 2198 */ "bc1nezc\t\0" |
| 284 |
/* 2207 */ "bc2nezc\t\0" |
284 |
/* 2207 */ "bc2nezc\t\0" |
| 285 |
/* 2216 */ "bnezc\t\0" |
285 |
/* 2216 */ "bnezc\t\0" |
| 286 |
/* 2223 */ "bc1eqzc\t\0" |
286 |
/* 2223 */ "bc1eqzc\t\0" |
| 287 |
/* 2232 */ "bc2eqzc\t\0" |
287 |
/* 2232 */ "bc2eqzc\t\0" |
| 288 |
/* 2241 */ "beqzc\t\0" |
288 |
/* 2241 */ "beqzc\t\0" |
| 289 |
/* 2248 */ "bgtzc\t\0" |
289 |
/* 2248 */ "bgtzc\t\0" |
| 290 |
/* 2255 */ "bltzc\t\0" |
290 |
/* 2255 */ "bltzc\t\0" |
| 291 |
/* 2262 */ "flog2.d\t\0" |
291 |
/* 2262 */ "flog2.d\t\0" |
| 292 |
/* 2271 */ "fexp2.d\t\0" |
292 |
/* 2271 */ "fexp2.d\t\0" |
| 293 |
/* 2280 */ "add_a.d\t\0" |
293 |
/* 2280 */ "add_a.d\t\0" |
| 294 |
/* 2289 */ "fmin_a.d\t\0" |
294 |
/* 2289 */ "fmin_a.d\t\0" |
| 295 |
/* 2299 */ "adds_a.d\t\0" |
295 |
/* 2299 */ "adds_a.d\t\0" |
| 296 |
/* 2309 */ "fmax_a.d\t\0" |
296 |
/* 2309 */ "fmax_a.d\t\0" |
| 297 |
/* 2319 */ "mina.d\t\0" |
297 |
/* 2319 */ "mina.d\t\0" |
| 298 |
/* 2327 */ "sra.d\t\0" |
298 |
/* 2327 */ "sra.d\t\0" |
| 299 |
/* 2334 */ "maxa.d\t\0" |
299 |
/* 2334 */ "maxa.d\t\0" |
| 300 |
/* 2342 */ "fsub.d\t\0" |
300 |
/* 2342 */ "fsub.d\t\0" |
| 301 |
/* 2350 */ "fmsub.d\t\0" |
301 |
/* 2350 */ "fmsub.d\t\0" |
| 302 |
/* 2359 */ "nmsub.d\t\0" |
302 |
/* 2359 */ "nmsub.d\t\0" |
| 303 |
/* 2368 */ "nloc.d\t\0" |
303 |
/* 2368 */ "nloc.d\t\0" |
| 304 |
/* 2376 */ "nlzc.d\t\0" |
304 |
/* 2376 */ "nlzc.d\t\0" |
| 305 |
/* 2384 */ "fadd.d\t\0" |
305 |
/* 2384 */ "fadd.d\t\0" |
| 306 |
/* 2392 */ "fmadd.d\t\0" |
306 |
/* 2392 */ "fmadd.d\t\0" |
| 307 |
/* 2401 */ "nmadd.d\t\0" |
307 |
/* 2401 */ "nmadd.d\t\0" |
| 308 |
/* 2410 */ "sld.d\t\0" |
308 |
/* 2410 */ "sld.d\t\0" |
| 309 |
/* 2417 */ "pckod.d\t\0" |
309 |
/* 2417 */ "pckod.d\t\0" |
| 310 |
/* 2426 */ "ilvod.d\t\0" |
310 |
/* 2426 */ "ilvod.d\t\0" |
| 311 |
/* 2435 */ "c.nge.d\t\0" |
311 |
/* 2435 */ "c.nge.d\t\0" |
| 312 |
/* 2444 */ "c.le.d\t\0" |
312 |
/* 2444 */ "c.le.d\t\0" |
| 313 |
/* 2452 */ "cmp.le.d\t\0" |
313 |
/* 2452 */ "cmp.le.d\t\0" |
| 314 |
/* 2462 */ "fcle.d\t\0" |
314 |
/* 2462 */ "fcle.d\t\0" |
| 315 |
/* 2470 */ "c.ngle.d\t\0" |
315 |
/* 2470 */ "c.ngle.d\t\0" |
| 316 |
/* 2480 */ "c.ole.d\t\0" |
316 |
/* 2480 */ "c.ole.d\t\0" |
| 317 |
/* 2489 */ "cmp.sle.d\t\0" |
317 |
/* 2489 */ "cmp.sle.d\t\0" |
| 318 |
/* 2500 */ "fsle.d\t\0" |
318 |
/* 2500 */ "fsle.d\t\0" |
| 319 |
/* 2508 */ "c.ule.d\t\0" |
319 |
/* 2508 */ "c.ule.d\t\0" |
| 320 |
/* 2517 */ "cmp.ule.d\t\0" |
320 |
/* 2517 */ "cmp.ule.d\t\0" |
| 321 |
/* 2528 */ "fcule.d\t\0" |
321 |
/* 2528 */ "fcule.d\t\0" |
| 322 |
/* 2537 */ "cmp.sule.d\t\0" |
322 |
/* 2537 */ "cmp.sule.d\t\0" |
| 323 |
/* 2549 */ "fsule.d\t\0" |
323 |
/* 2549 */ "fsule.d\t\0" |
| 324 |
/* 2558 */ "fcne.d\t\0" |
324 |
/* 2558 */ "fcne.d\t\0" |
| 325 |
/* 2566 */ "fsne.d\t\0" |
325 |
/* 2566 */ "fsne.d\t\0" |
| 326 |
/* 2574 */ "fcune.d\t\0" |
326 |
/* 2574 */ "fcune.d\t\0" |
| 327 |
/* 2583 */ "fsune.d\t\0" |
327 |
/* 2583 */ "fsune.d\t\0" |
| 328 |
/* 2592 */ "insve.d\t\0" |
328 |
/* 2592 */ "insve.d\t\0" |
| 329 |
/* 2601 */ "c.f.d\t\0" |
329 |
/* 2601 */ "c.f.d\t\0" |
| 330 |
/* 2608 */ "cmp.af.d\t\0" |
330 |
/* 2608 */ "cmp.af.d\t\0" |
| 331 |
/* 2618 */ "fcaf.d\t\0" |
331 |
/* 2618 */ "fcaf.d\t\0" |
| 332 |
/* 2626 */ "cmp.saf.d\t\0" |
332 |
/* 2626 */ "cmp.saf.d\t\0" |
| 333 |
/* 2637 */ "fsaf.d\t\0" |
333 |
/* 2637 */ "fsaf.d\t\0" |
| 334 |
/* 2645 */ "msubf.d\t\0" |
334 |
/* 2645 */ "msubf.d\t\0" |
| 335 |
/* 2654 */ "maddf.d\t\0" |
335 |
/* 2654 */ "maddf.d\t\0" |
| 336 |
/* 2663 */ "vshf.d\t\0" |
336 |
/* 2663 */ "vshf.d\t\0" |
| 337 |
/* 2671 */ "c.sf.d\t\0" |
337 |
/* 2671 */ "c.sf.d\t\0" |
| 338 |
/* 2679 */ "movf.d\t\0" |
338 |
/* 2679 */ "movf.d\t\0" |
| 339 |
/* 2687 */ "bneg.d\t\0" |
339 |
/* 2687 */ "bneg.d\t\0" |
| 340 |
/* 2695 */ "srai.d\t\0" |
340 |
/* 2695 */ "srai.d\t\0" |
| 341 |
/* 2703 */ "sldi.d\t\0" |
341 |
/* 2703 */ "sldi.d\t\0" |
| 342 |
/* 2711 */ "bnegi.d\t\0" |
342 |
/* 2711 */ "bnegi.d\t\0" |
| 343 |
/* 2720 */ "slli.d\t\0" |
343 |
/* 2720 */ "slli.d\t\0" |
| 344 |
/* 2728 */ "srli.d\t\0" |
344 |
/* 2728 */ "srli.d\t\0" |
| 345 |
/* 2736 */ "binsli.d\t\0" |
345 |
/* 2736 */ "binsli.d\t\0" |
| 346 |
/* 2746 */ "ceqi.d\t\0" |
346 |
/* 2746 */ "ceqi.d\t\0" |
| 347 |
/* 2754 */ "srari.d\t\0" |
347 |
/* 2754 */ "srari.d\t\0" |
| 348 |
/* 2763 */ "bclri.d\t\0" |
348 |
/* 2763 */ "bclri.d\t\0" |
| 349 |
/* 2772 */ "srlri.d\t\0" |
349 |
/* 2772 */ "srlri.d\t\0" |
| 350 |
/* 2781 */ "binsri.d\t\0" |
350 |
/* 2781 */ "binsri.d\t\0" |
| 351 |
/* 2791 */ "splati.d\t\0" |
351 |
/* 2791 */ "splati.d\t\0" |
| 352 |
/* 2801 */ "bseti.d\t\0" |
352 |
/* 2801 */ "bseti.d\t\0" |
| 353 |
/* 2810 */ "subvi.d\t\0" |
353 |
/* 2810 */ "subvi.d\t\0" |
| 354 |
/* 2819 */ "addvi.d\t\0" |
354 |
/* 2819 */ "addvi.d\t\0" |
| 355 |
/* 2828 */ "trunc.l.d\t\0" |
355 |
/* 2828 */ "trunc.l.d\t\0" |
| 356 |
/* 2839 */ "round.l.d\t\0" |
356 |
/* 2839 */ "round.l.d\t\0" |
| 357 |
/* 2850 */ "ceil.l.d\t\0" |
357 |
/* 2850 */ "ceil.l.d\t\0" |
| 358 |
/* 2860 */ "floor.l.d\t\0" |
358 |
/* 2860 */ "floor.l.d\t\0" |
| 359 |
/* 2871 */ "cvt.l.d\t\0" |
359 |
/* 2871 */ "cvt.l.d\t\0" |
| 360 |
/* 2880 */ "sel.d\t\0" |
360 |
/* 2880 */ "sel.d\t\0" |
| 361 |
/* 2887 */ "c.ngl.d\t\0" |
361 |
/* 2887 */ "c.ngl.d\t\0" |
| 362 |
/* 2896 */ "fill.d\t\0" |
362 |
/* 2896 */ "fill.d\t\0" |
| 363 |
/* 2904 */ "sll.d\t\0" |
363 |
/* 2904 */ "sll.d\t\0" |
| 364 |
/* 2911 */ "fexupl.d\t\0" |
364 |
/* 2911 */ "fexupl.d\t\0" |
| 365 |
/* 2921 */ "ffql.d\t\0" |
365 |
/* 2921 */ "ffql.d\t\0" |
| 366 |
/* 2929 */ "srl.d\t\0" |
366 |
/* 2929 */ "srl.d\t\0" |
| 367 |
/* 2936 */ "binsl.d\t\0" |
367 |
/* 2936 */ "binsl.d\t\0" |
| 368 |
/* 2945 */ "fmul.d\t\0" |
368 |
/* 2945 */ "fmul.d\t\0" |
| 369 |
/* 2953 */ "ilvl.d\t\0" |
369 |
/* 2953 */ "ilvl.d\t\0" |
| 370 |
/* 2961 */ "fmin.d\t\0" |
370 |
/* 2961 */ "fmin.d\t\0" |
| 371 |
/* 2969 */ "c.un.d\t\0" |
371 |
/* 2969 */ "c.un.d\t\0" |
| 372 |
/* 2977 */ "cmp.un.d\t\0" |
372 |
/* 2977 */ "cmp.un.d\t\0" |
| 373 |
/* 2987 */ "fcun.d\t\0" |
373 |
/* 2987 */ "fcun.d\t\0" |
| 374 |
/* 2995 */ "cmp.sun.d\t\0" |
374 |
/* 2995 */ "cmp.sun.d\t\0" |
| 375 |
/* 3006 */ "fsun.d\t\0" |
375 |
/* 3006 */ "fsun.d\t\0" |
| 376 |
/* 3014 */ "movn.d\t\0" |
376 |
/* 3014 */ "movn.d\t\0" |
| 377 |
/* 3022 */ "frcp.d\t\0" |
377 |
/* 3022 */ "frcp.d\t\0" |
| 378 |
/* 3030 */ "recip.d\t\0" |
378 |
/* 3030 */ "recip.d\t\0" |
| 379 |
/* 3039 */ "c.eq.d\t\0" |
379 |
/* 3039 */ "c.eq.d\t\0" |
| 380 |
/* 3047 */ "cmp.eq.d\t\0" |
380 |
/* 3047 */ "cmp.eq.d\t\0" |
| 381 |
/* 3057 */ "fceq.d\t\0" |
381 |
/* 3057 */ "fceq.d\t\0" |
| 382 |
/* 3065 */ "c.seq.d\t\0" |
382 |
/* 3065 */ "c.seq.d\t\0" |
| 383 |
/* 3074 */ "cmp.seq.d\t\0" |
383 |
/* 3074 */ "cmp.seq.d\t\0" |
| 384 |
/* 3085 */ "fseq.d\t\0" |
384 |
/* 3085 */ "fseq.d\t\0" |
| 385 |
/* 3093 */ "c.ueq.d\t\0" |
385 |
/* 3093 */ "c.ueq.d\t\0" |
| 386 |
/* 3102 */ "cmp.ueq.d\t\0" |
386 |
/* 3102 */ "cmp.ueq.d\t\0" |
| 387 |
/* 3113 */ "fcueq.d\t\0" |
387 |
/* 3113 */ "fcueq.d\t\0" |
| 388 |
/* 3122 */ "cmp.sueq.d\t\0" |
388 |
/* 3122 */ "cmp.sueq.d\t\0" |
| 389 |
/* 3134 */ "fsueq.d\t\0" |
389 |
/* 3134 */ "fsueq.d\t\0" |
| 390 |
/* 3143 */ "srar.d\t\0" |
390 |
/* 3143 */ "srar.d\t\0" |
| 391 |
/* 3151 */ "bclr.d\t\0" |
391 |
/* 3151 */ "bclr.d\t\0" |
| 392 |
/* 3159 */ "srlr.d\t\0" |
392 |
/* 3159 */ "srlr.d\t\0" |
| 393 |
/* 3167 */ "fcor.d\t\0" |
393 |
/* 3167 */ "fcor.d\t\0" |
| 394 |
/* 3175 */ "fsor.d\t\0" |
394 |
/* 3175 */ "fsor.d\t\0" |
| 395 |
/* 3183 */ "fexupr.d\t\0" |
395 |
/* 3183 */ "fexupr.d\t\0" |
| 396 |
/* 3193 */ "ffqr.d\t\0" |
396 |
/* 3193 */ "ffqr.d\t\0" |
| 397 |
/* 3201 */ "binsr.d\t\0" |
397 |
/* 3201 */ "binsr.d\t\0" |
| 398 |
/* 3210 */ "ilvr.d\t\0" |
398 |
/* 3210 */ "ilvr.d\t\0" |
| 399 |
/* 3218 */ "cvt.s.d\t\0" |
399 |
/* 3218 */ "cvt.s.d\t\0" |
| 400 |
/* 3227 */ "asub_s.d\t\0" |
400 |
/* 3227 */ "asub_s.d\t\0" |
| 401 |
/* 3237 */ "hsub_s.d\t\0" |
401 |
/* 3237 */ "hsub_s.d\t\0" |
| 402 |
/* 3247 */ "dpsub_s.d\t\0" |
402 |
/* 3247 */ "dpsub_s.d\t\0" |
| 403 |
/* 3258 */ "ftrunc_s.d\t\0" |
403 |
/* 3258 */ "ftrunc_s.d\t\0" |
| 404 |
/* 3270 */ "hadd_s.d\t\0" |
404 |
/* 3270 */ "hadd_s.d\t\0" |
| 405 |
/* 3280 */ "dpadd_s.d\t\0" |
405 |
/* 3280 */ "dpadd_s.d\t\0" |
| 406 |
/* 3291 */ "mod_s.d\t\0" |
406 |
/* 3291 */ "mod_s.d\t\0" |
| 407 |
/* 3300 */ "cle_s.d\t\0" |
407 |
/* 3300 */ "cle_s.d\t\0" |
| 408 |
/* 3309 */ "ave_s.d\t\0" |
408 |
/* 3309 */ "ave_s.d\t\0" |
| 409 |
/* 3318 */ "clei_s.d\t\0" |
409 |
/* 3318 */ "clei_s.d\t\0" |
| 410 |
/* 3328 */ "mini_s.d\t\0" |
410 |
/* 3328 */ "mini_s.d\t\0" |
| 411 |
/* 3338 */ "clti_s.d\t\0" |
411 |
/* 3338 */ "clti_s.d\t\0" |
| 412 |
/* 3348 */ "maxi_s.d\t\0" |
412 |
/* 3348 */ "maxi_s.d\t\0" |
| 413 |
/* 3358 */ "min_s.d\t\0" |
413 |
/* 3358 */ "min_s.d\t\0" |
| 414 |
/* 3367 */ "dotp_s.d\t\0" |
414 |
/* 3367 */ "dotp_s.d\t\0" |
| 415 |
/* 3377 */ "aver_s.d\t\0" |
415 |
/* 3377 */ "aver_s.d\t\0" |
| 416 |
/* 3387 */ "subs_s.d\t\0" |
416 |
/* 3387 */ "subs_s.d\t\0" |
| 417 |
/* 3397 */ "adds_s.d\t\0" |
417 |
/* 3397 */ "adds_s.d\t\0" |
| 418 |
/* 3407 */ "sat_s.d\t\0" |
418 |
/* 3407 */ "sat_s.d\t\0" |
| 419 |
/* 3416 */ "clt_s.d\t\0" |
419 |
/* 3416 */ "clt_s.d\t\0" |
| 420 |
/* 3425 */ "ffint_s.d\t\0" |
420 |
/* 3425 */ "ffint_s.d\t\0" |
| 421 |
/* 3436 */ "ftint_s.d\t\0" |
421 |
/* 3436 */ "ftint_s.d\t\0" |
| 422 |
/* 3447 */ "subsuu_s.d\t\0" |
422 |
/* 3447 */ "subsuu_s.d\t\0" |
| 423 |
/* 3459 */ "div_s.d\t\0" |
423 |
/* 3459 */ "div_s.d\t\0" |
| 424 |
/* 3468 */ "max_s.d\t\0" |
424 |
/* 3468 */ "max_s.d\t\0" |
| 425 |
/* 3477 */ "copy_s.d\t\0" |
425 |
/* 3477 */ "copy_s.d\t\0" |
| 426 |
/* 3487 */ "abs.d\t\0" |
426 |
/* 3487 */ "abs.d\t\0" |
| 427 |
/* 3494 */ "fclass.d\t\0" |
427 |
/* 3494 */ "fclass.d\t\0" |
| 428 |
/* 3504 */ "splat.d\t\0" |
428 |
/* 3504 */ "splat.d\t\0" |
| 429 |
/* 3513 */ "bset.d\t\0" |
429 |
/* 3513 */ "bset.d\t\0" |
| 430 |
/* 3521 */ "c.ngt.d\t\0" |
430 |
/* 3521 */ "c.ngt.d\t\0" |
| 431 |
/* 3530 */ "c.lt.d\t\0" |
431 |
/* 3530 */ "c.lt.d\t\0" |
| 432 |
/* 3538 */ "cmp.lt.d\t\0" |
432 |
/* 3538 */ "cmp.lt.d\t\0" |
| 433 |
/* 3548 */ "fclt.d\t\0" |
433 |
/* 3548 */ "fclt.d\t\0" |
| 434 |
/* 3556 */ "c.olt.d\t\0" |
434 |
/* 3556 */ "c.olt.d\t\0" |
| 435 |
/* 3565 */ "cmp.slt.d\t\0" |
435 |
/* 3565 */ "cmp.slt.d\t\0" |
| 436 |
/* 3576 */ "fslt.d\t\0" |
436 |
/* 3576 */ "fslt.d\t\0" |
| 437 |
/* 3584 */ "c.ult.d\t\0" |
437 |
/* 3584 */ "c.ult.d\t\0" |
| 438 |
/* 3593 */ "cmp.ult.d\t\0" |
438 |
/* 3593 */ "cmp.ult.d\t\0" |
| 439 |
/* 3604 */ "fcult.d\t\0" |
439 |
/* 3604 */ "fcult.d\t\0" |
| 440 |
/* 3613 */ "cmp.sult.d\t\0" |
440 |
/* 3613 */ "cmp.sult.d\t\0" |
| 441 |
/* 3625 */ "fsult.d\t\0" |
441 |
/* 3625 */ "fsult.d\t\0" |
| 442 |
/* 3634 */ "pcnt.d\t\0" |
442 |
/* 3634 */ "pcnt.d\t\0" |
| 443 |
/* 3642 */ "frint.d\t\0" |
443 |
/* 3642 */ "frint.d\t\0" |
| 444 |
/* 3651 */ "insert.d\t\0" |
444 |
/* 3651 */ "insert.d\t\0" |
| 445 |
/* 3661 */ "fsqrt.d\t\0" |
445 |
/* 3661 */ "fsqrt.d\t\0" |
| 446 |
/* 3670 */ "frsqrt.d\t\0" |
446 |
/* 3670 */ "frsqrt.d\t\0" |
| 447 |
/* 3680 */ "st.d\t\0" |
447 |
/* 3680 */ "st.d\t\0" |
| 448 |
/* 3686 */ "movt.d\t\0" |
448 |
/* 3686 */ "movt.d\t\0" |
| 449 |
/* 3694 */ "asub_u.d\t\0" |
449 |
/* 3694 */ "asub_u.d\t\0" |
| 450 |
/* 3704 */ "hsub_u.d\t\0" |
450 |
/* 3704 */ "hsub_u.d\t\0" |
| 451 |
/* 3714 */ "dpsub_u.d\t\0" |
451 |
/* 3714 */ "dpsub_u.d\t\0" |
| 452 |
/* 3725 */ "ftrunc_u.d\t\0" |
452 |
/* 3725 */ "ftrunc_u.d\t\0" |
| 453 |
/* 3737 */ "hadd_u.d\t\0" |
453 |
/* 3737 */ "hadd_u.d\t\0" |
| 454 |
/* 3747 */ "dpadd_u.d\t\0" |
454 |
/* 3747 */ "dpadd_u.d\t\0" |
| 455 |
/* 3758 */ "mod_u.d\t\0" |
455 |
/* 3758 */ "mod_u.d\t\0" |
| 456 |
/* 3767 */ "cle_u.d\t\0" |
456 |
/* 3767 */ "cle_u.d\t\0" |
| 457 |
/* 3776 */ "ave_u.d\t\0" |
457 |
/* 3776 */ "ave_u.d\t\0" |
| 458 |
/* 3785 */ "clei_u.d\t\0" |
458 |
/* 3785 */ "clei_u.d\t\0" |
| 459 |
/* 3795 */ "mini_u.d\t\0" |
459 |
/* 3795 */ "mini_u.d\t\0" |
| 460 |
/* 3805 */ "clti_u.d\t\0" |
460 |
/* 3805 */ "clti_u.d\t\0" |
| 461 |
/* 3815 */ "maxi_u.d\t\0" |
461 |
/* 3815 */ "maxi_u.d\t\0" |
| 462 |
/* 3825 */ "min_u.d\t\0" |
462 |
/* 3825 */ "min_u.d\t\0" |
| 463 |
/* 3834 */ "dotp_u.d\t\0" |
463 |
/* 3834 */ "dotp_u.d\t\0" |
| 464 |
/* 3844 */ "aver_u.d\t\0" |
464 |
/* 3844 */ "aver_u.d\t\0" |
| 465 |
/* 3854 */ "subs_u.d\t\0" |
465 |
/* 3854 */ "subs_u.d\t\0" |
| 466 |
/* 3864 */ "adds_u.d\t\0" |
466 |
/* 3864 */ "adds_u.d\t\0" |
| 467 |
/* 3874 */ "subsus_u.d\t\0" |
467 |
/* 3874 */ "subsus_u.d\t\0" |
| 468 |
/* 3886 */ "sat_u.d\t\0" |
468 |
/* 3886 */ "sat_u.d\t\0" |
| 469 |
/* 3895 */ "clt_u.d\t\0" |
469 |
/* 3895 */ "clt_u.d\t\0" |
| 470 |
/* 3904 */ "ffint_u.d\t\0" |
470 |
/* 3904 */ "ffint_u.d\t\0" |
| 471 |
/* 3915 */ "ftint_u.d\t\0" |
471 |
/* 3915 */ "ftint_u.d\t\0" |
| 472 |
/* 3926 */ "div_u.d\t\0" |
472 |
/* 3926 */ "div_u.d\t\0" |
| 473 |
/* 3935 */ "max_u.d\t\0" |
473 |
/* 3935 */ "max_u.d\t\0" |
| 474 |
/* 3944 */ "msubv.d\t\0" |
474 |
/* 3944 */ "msubv.d\t\0" |
| 475 |
/* 3953 */ "maddv.d\t\0" |
475 |
/* 3953 */ "maddv.d\t\0" |
| 476 |
/* 3962 */ "pckev.d\t\0" |
476 |
/* 3962 */ "pckev.d\t\0" |
| 477 |
/* 3971 */ "ilvev.d\t\0" |
477 |
/* 3971 */ "ilvev.d\t\0" |
| 478 |
/* 3980 */ "fdiv.d\t\0" |
478 |
/* 3980 */ "fdiv.d\t\0" |
| 479 |
/* 3988 */ "mulv.d\t\0" |
479 |
/* 3988 */ "mulv.d\t\0" |
| 480 |
/* 3996 */ "mov.d\t\0" |
480 |
/* 3996 */ "mov.d\t\0" |
| 481 |
/* 4003 */ "trunc.w.d\t\0" |
481 |
/* 4003 */ "trunc.w.d\t\0" |
| 482 |
/* 4014 */ "round.w.d\t\0" |
482 |
/* 4014 */ "round.w.d\t\0" |
| 483 |
/* 4025 */ "ceil.w.d\t\0" |
483 |
/* 4025 */ "ceil.w.d\t\0" |
| 484 |
/* 4035 */ "floor.w.d\t\0" |
484 |
/* 4035 */ "floor.w.d\t\0" |
| 485 |
/* 4046 */ "cvt.w.d\t\0" |
485 |
/* 4046 */ "cvt.w.d\t\0" |
| 486 |
/* 4055 */ "fmax.d\t\0" |
486 |
/* 4055 */ "fmax.d\t\0" |
| 487 |
/* 4063 */ "bz.d\t\0" |
487 |
/* 4063 */ "bz.d\t\0" |
| 488 |
/* 4069 */ "selnez.d\t\0" |
488 |
/* 4069 */ "selnez.d\t\0" |
| 489 |
/* 4079 */ "bnz.d\t\0" |
489 |
/* 4079 */ "bnz.d\t\0" |
| 490 |
/* 4086 */ "seleqz.d\t\0" |
490 |
/* 4086 */ "seleqz.d\t\0" |
| 491 |
/* 4096 */ "movz.d\t\0" |
491 |
/* 4096 */ "movz.d\t\0" |
| 492 |
/* 4104 */ "crc32d\t\0" |
492 |
/* 4104 */ "crc32d\t\0" |
| 493 |
/* 4112 */ "saad\t\0" |
493 |
/* 4112 */ "saad\t\0" |
| 494 |
/* 4118 */ "crc32cd\t\0" |
494 |
/* 4118 */ "crc32cd\t\0" |
| 495 |
/* 4127 */ "scd\t\0" |
495 |
/* 4127 */ "scd\t\0" |
| 496 |
/* 4132 */ "dadd\t\0" |
496 |
/* 4132 */ "dadd\t\0" |
| 497 |
/* 4138 */ "madd\t\0" |
497 |
/* 4138 */ "madd\t\0" |
| 498 |
/* 4144 */ "dshd\t\0" |
498 |
/* 4144 */ "dshd\t\0" |
| 499 |
/* 4150 */ "yield\t\0" |
499 |
/* 4150 */ "yield\t\0" |
| 500 |
/* 4157 */ "lld\t\0" |
500 |
/* 4157 */ "lld\t\0" |
| 501 |
/* 4162 */ "and\t\0" |
501 |
/* 4162 */ "and\t\0" |
| 502 |
/* 4167 */ "prepend\t\0" |
502 |
/* 4167 */ "prepend\t\0" |
| 503 |
/* 4176 */ "append\t\0" |
503 |
/* 4176 */ "append\t\0" |
| 504 |
/* 4184 */ "dmod\t\0" |
504 |
/* 4184 */ "dmod\t\0" |
| 505 |
/* 4190 */ "sd\t\0" |
505 |
/* 4190 */ "sd\t\0" |
| 506 |
/* 4194 */ "lbe\t\0" |
506 |
/* 4194 */ "lbe\t\0" |
| 507 |
/* 4199 */ "sbe\t\0" |
507 |
/* 4199 */ "sbe\t\0" |
| 508 |
/* 4204 */ "sce\t\0" |
508 |
/* 4204 */ "sce\t\0" |
| 509 |
/* 4209 */ "cachee\t\0" |
509 |
/* 4209 */ "cachee\t\0" |
| 510 |
/* 4217 */ "prefe\t\0" |
510 |
/* 4217 */ "prefe\t\0" |
| 511 |
/* 4224 */ "bge\t\0" |
511 |
/* 4224 */ "bge\t\0" |
| 512 |
/* 4229 */ "sge\t\0" |
512 |
/* 4229 */ "sge\t\0" |
| 513 |
/* 4234 */ "tge\t\0" |
513 |
/* 4234 */ "tge\t\0" |
| 514 |
/* 4239 */ "cache\t\0" |
514 |
/* 4239 */ "cache\t\0" |
| 515 |
/* 4246 */ "lhe\t\0" |
515 |
/* 4246 */ "lhe\t\0" |
| 516 |
/* 4251 */ "she\t\0" |
516 |
/* 4251 */ "she\t\0" |
| 517 |
/* 4256 */ "sigrie\t\0" |
517 |
/* 4256 */ "sigrie\t\0" |
| 518 |
/* 4264 */ "ble\t\0" |
518 |
/* 4264 */ "ble\t\0" |
| 519 |
/* 4269 */ "lle\t\0" |
519 |
/* 4269 */ "lle\t\0" |
| 520 |
/* 4274 */ "sle\t\0" |
520 |
/* 4274 */ "sle\t\0" |
| 521 |
/* 4279 */ "lwle\t\0" |
521 |
/* 4279 */ "lwle\t\0" |
| 522 |
/* 4285 */ "swle\t\0" |
522 |
/* 4285 */ "swle\t\0" |
| 523 |
/* 4291 */ "bne\t\0" |
523 |
/* 4291 */ "bne\t\0" |
| 524 |
/* 4296 */ "sne\t\0" |
524 |
/* 4296 */ "sne\t\0" |
| 525 |
/* 4301 */ "tne\t\0" |
525 |
/* 4301 */ "tne\t\0" |
| 526 |
/* 4306 */ "dvpe\t\0" |
526 |
/* 4306 */ "dvpe\t\0" |
| 527 |
/* 4312 */ "evpe\t\0" |
527 |
/* 4312 */ "evpe\t\0" |
| 528 |
/* 4318 */ "lwre\t\0" |
528 |
/* 4318 */ "lwre\t\0" |
| 529 |
/* 4324 */ "swre\t\0" |
529 |
/* 4324 */ "swre\t\0" |
| 530 |
/* 4330 */ "lbue\t\0" |
530 |
/* 4330 */ "lbue\t\0" |
| 531 |
/* 4336 */ "lhue\t\0" |
531 |
/* 4336 */ "lhue\t\0" |
| 532 |
/* 4342 */ "move\t\0" |
532 |
/* 4342 */ "move\t\0" |
| 533 |
/* 4348 */ "lwe\t\0" |
533 |
/* 4348 */ "lwe\t\0" |
| 534 |
/* 4353 */ "swe\t\0" |
534 |
/* 4353 */ "swe\t\0" |
| 535 |
/* 4358 */ "bc1f\t\0" |
535 |
/* 4358 */ "bc1f\t\0" |
| 536 |
/* 4364 */ "pref\t\0" |
536 |
/* 4364 */ "pref\t\0" |
| 537 |
/* 4370 */ "movf\t\0" |
537 |
/* 4370 */ "movf\t\0" |
| 538 |
/* 4376 */ "neg\t\0" |
538 |
/* 4376 */ "neg\t\0" |
| 539 |
/* 4381 */ "add_a.h\t\0" |
539 |
/* 4381 */ "add_a.h\t\0" |
| 540 |
/* 4390 */ "min_a.h\t\0" |
540 |
/* 4390 */ "min_a.h\t\0" |
| 541 |
/* 4399 */ "adds_a.h\t\0" |
541 |
/* 4399 */ "adds_a.h\t\0" |
| 542 |
/* 4409 */ "max_a.h\t\0" |
542 |
/* 4409 */ "max_a.h\t\0" |
| 543 |
/* 4418 */ "sra.h\t\0" |
543 |
/* 4418 */ "sra.h\t\0" |
| 544 |
/* 4425 */ "nloc.h\t\0" |
544 |
/* 4425 */ "nloc.h\t\0" |
| 545 |
/* 4433 */ "nlzc.h\t\0" |
545 |
/* 4433 */ "nlzc.h\t\0" |
| 546 |
/* 4441 */ "sld.h\t\0" |
546 |
/* 4441 */ "sld.h\t\0" |
| 547 |
/* 4448 */ "pckod.h\t\0" |
547 |
/* 4448 */ "pckod.h\t\0" |
| 548 |
/* 4457 */ "ilvod.h\t\0" |
548 |
/* 4457 */ "ilvod.h\t\0" |
| 549 |
/* 4466 */ "insve.h\t\0" |
549 |
/* 4466 */ "insve.h\t\0" |
| 550 |
/* 4475 */ "vshf.h\t\0" |
550 |
/* 4475 */ "vshf.h\t\0" |
| 551 |
/* 4483 */ "bneg.h\t\0" |
551 |
/* 4483 */ "bneg.h\t\0" |
| 552 |
/* 4491 */ "srai.h\t\0" |
552 |
/* 4491 */ "srai.h\t\0" |
| 553 |
/* 4499 */ "sldi.h\t\0" |
553 |
/* 4499 */ "sldi.h\t\0" |
| 554 |
/* 4507 */ "bnegi.h\t\0" |
554 |
/* 4507 */ "bnegi.h\t\0" |
| 555 |
/* 4516 */ "slli.h\t\0" |
555 |
/* 4516 */ "slli.h\t\0" |
| 556 |
/* 4524 */ "srli.h\t\0" |
556 |
/* 4524 */ "srli.h\t\0" |
| 557 |
/* 4532 */ "binsli.h\t\0" |
557 |
/* 4532 */ "binsli.h\t\0" |
| 558 |
/* 4542 */ "ceqi.h\t\0" |
558 |
/* 4542 */ "ceqi.h\t\0" |
| 559 |
/* 4550 */ "srari.h\t\0" |
559 |
/* 4550 */ "srari.h\t\0" |
| 560 |
/* 4559 */ "bclri.h\t\0" |
560 |
/* 4559 */ "bclri.h\t\0" |
| 561 |
/* 4568 */ "srlri.h\t\0" |
561 |
/* 4568 */ "srlri.h\t\0" |
| 562 |
/* 4577 */ "binsri.h\t\0" |
562 |
/* 4577 */ "binsri.h\t\0" |
| 563 |
/* 4587 */ "splati.h\t\0" |
563 |
/* 4587 */ "splati.h\t\0" |
| 564 |
/* 4597 */ "bseti.h\t\0" |
564 |
/* 4597 */ "bseti.h\t\0" |
| 565 |
/* 4606 */ "subvi.h\t\0" |
565 |
/* 4606 */ "subvi.h\t\0" |
| 566 |
/* 4615 */ "addvi.h\t\0" |
566 |
/* 4615 */ "addvi.h\t\0" |
| 567 |
/* 4624 */ "fill.h\t\0" |
567 |
/* 4624 */ "fill.h\t\0" |
| 568 |
/* 4632 */ "sll.h\t\0" |
568 |
/* 4632 */ "sll.h\t\0" |
| 569 |
/* 4639 */ "srl.h\t\0" |
569 |
/* 4639 */ "srl.h\t\0" |
| 570 |
/* 4646 */ "binsl.h\t\0" |
570 |
/* 4646 */ "binsl.h\t\0" |
| 571 |
/* 4655 */ "ilvl.h\t\0" |
571 |
/* 4655 */ "ilvl.h\t\0" |
| 572 |
/* 4663 */ "fexdo.h\t\0" |
572 |
/* 4663 */ "fexdo.h\t\0" |
| 573 |
/* 4672 */ "msub_q.h\t\0" |
573 |
/* 4672 */ "msub_q.h\t\0" |
| 574 |
/* 4682 */ "madd_q.h\t\0" |
574 |
/* 4682 */ "madd_q.h\t\0" |
| 575 |
/* 4692 */ "mul_q.h\t\0" |
575 |
/* 4692 */ "mul_q.h\t\0" |
| 576 |
/* 4701 */ "msubr_q.h\t\0" |
576 |
/* 4701 */ "msubr_q.h\t\0" |
| 577 |
/* 4712 */ "maddr_q.h\t\0" |
577 |
/* 4712 */ "maddr_q.h\t\0" |
| 578 |
/* 4723 */ "mulr_q.h\t\0" |
578 |
/* 4723 */ "mulr_q.h\t\0" |
| 579 |
/* 4733 */ "ceq.h\t\0" |
579 |
/* 4733 */ "ceq.h\t\0" |
| 580 |
/* 4740 */ "ftq.h\t\0" |
580 |
/* 4740 */ "ftq.h\t\0" |
| 581 |
/* 4747 */ "srar.h\t\0" |
581 |
/* 4747 */ "srar.h\t\0" |
| 582 |
/* 4755 */ "bclr.h\t\0" |
582 |
/* 4755 */ "bclr.h\t\0" |
| 583 |
/* 4763 */ "srlr.h\t\0" |
583 |
/* 4763 */ "srlr.h\t\0" |
| 584 |
/* 4771 */ "binsr.h\t\0" |
584 |
/* 4771 */ "binsr.h\t\0" |
| 585 |
/* 4780 */ "ilvr.h\t\0" |
585 |
/* 4780 */ "ilvr.h\t\0" |
| 586 |
/* 4788 */ "asub_s.h\t\0" |
586 |
/* 4788 */ "asub_s.h\t\0" |
| 587 |
/* 4798 */ "hsub_s.h\t\0" |
587 |
/* 4798 */ "hsub_s.h\t\0" |
| 588 |
/* 4808 */ "dpsub_s.h\t\0" |
588 |
/* 4808 */ "dpsub_s.h\t\0" |
| 589 |
/* 4819 */ "hadd_s.h\t\0" |
589 |
/* 4819 */ "hadd_s.h\t\0" |
| 590 |
/* 4829 */ "dpadd_s.h\t\0" |
590 |
/* 4829 */ "dpadd_s.h\t\0" |
| 591 |
/* 4840 */ "mod_s.h\t\0" |
591 |
/* 4840 */ "mod_s.h\t\0" |
| 592 |
/* 4849 */ "cle_s.h\t\0" |
592 |
/* 4849 */ "cle_s.h\t\0" |
| 593 |
/* 4858 */ "ave_s.h\t\0" |
593 |
/* 4858 */ "ave_s.h\t\0" |
| 594 |
/* 4867 */ "clei_s.h\t\0" |
594 |
/* 4867 */ "clei_s.h\t\0" |
| 595 |
/* 4877 */ "mini_s.h\t\0" |
595 |
/* 4877 */ "mini_s.h\t\0" |
| 596 |
/* 4887 */ "clti_s.h\t\0" |
596 |
/* 4887 */ "clti_s.h\t\0" |
| 597 |
/* 4897 */ "maxi_s.h\t\0" |
597 |
/* 4897 */ "maxi_s.h\t\0" |
| 598 |
/* 4907 */ "min_s.h\t\0" |
598 |
/* 4907 */ "min_s.h\t\0" |
| 599 |
/* 4916 */ "dotp_s.h\t\0" |
599 |
/* 4916 */ "dotp_s.h\t\0" |
| 600 |
/* 4926 */ "aver_s.h\t\0" |
600 |
/* 4926 */ "aver_s.h\t\0" |
| 601 |
/* 4936 */ "extr_s.h\t\0" |
601 |
/* 4936 */ "extr_s.h\t\0" |
| 602 |
/* 4946 */ "subs_s.h\t\0" |
602 |
/* 4946 */ "subs_s.h\t\0" |
| 603 |
/* 4956 */ "adds_s.h\t\0" |
603 |
/* 4956 */ "adds_s.h\t\0" |
| 604 |
/* 4966 */ "sat_s.h\t\0" |
604 |
/* 4966 */ "sat_s.h\t\0" |
| 605 |
/* 4975 */ "clt_s.h\t\0" |
605 |
/* 4975 */ "clt_s.h\t\0" |
| 606 |
/* 4984 */ "subsuu_s.h\t\0" |
606 |
/* 4984 */ "subsuu_s.h\t\0" |
| 607 |
/* 4996 */ "div_s.h\t\0" |
607 |
/* 4996 */ "div_s.h\t\0" |
| 608 |
/* 5005 */ "extrv_s.h\t\0" |
608 |
/* 5005 */ "extrv_s.h\t\0" |
| 609 |
/* 5016 */ "max_s.h\t\0" |
609 |
/* 5016 */ "max_s.h\t\0" |
| 610 |
/* 5025 */ "copy_s.h\t\0" |
610 |
/* 5025 */ "copy_s.h\t\0" |
| 611 |
/* 5035 */ "splat.h\t\0" |
611 |
/* 5035 */ "splat.h\t\0" |
| 612 |
/* 5044 */ "bset.h\t\0" |
612 |
/* 5044 */ "bset.h\t\0" |
| 613 |
/* 5052 */ "pcnt.h\t\0" |
613 |
/* 5052 */ "pcnt.h\t\0" |
| 614 |
/* 5060 */ "insert.h\t\0" |
614 |
/* 5060 */ "insert.h\t\0" |
| 615 |
/* 5070 */ "st.h\t\0" |
615 |
/* 5070 */ "st.h\t\0" |
| 616 |
/* 5076 */ "asub_u.h\t\0" |
616 |
/* 5076 */ "asub_u.h\t\0" |
| 617 |
/* 5086 */ "hsub_u.h\t\0" |
617 |
/* 5086 */ "hsub_u.h\t\0" |
| 618 |
/* 5096 */ "dpsub_u.h\t\0" |
618 |
/* 5096 */ "dpsub_u.h\t\0" |
| 619 |
/* 5107 */ "hadd_u.h\t\0" |
619 |
/* 5107 */ "hadd_u.h\t\0" |
| 620 |
/* 5117 */ "dpadd_u.h\t\0" |
620 |
/* 5117 */ "dpadd_u.h\t\0" |
| 621 |
/* 5128 */ "mod_u.h\t\0" |
621 |
/* 5128 */ "mod_u.h\t\0" |
| 622 |
/* 5137 */ "cle_u.h\t\0" |
622 |
/* 5137 */ "cle_u.h\t\0" |
| 623 |
/* 5146 */ "ave_u.h\t\0" |
623 |
/* 5146 */ "ave_u.h\t\0" |
| 624 |
/* 5155 */ "clei_u.h\t\0" |
624 |
/* 5155 */ "clei_u.h\t\0" |
| 625 |
/* 5165 */ "mini_u.h\t\0" |
625 |
/* 5165 */ "mini_u.h\t\0" |
| 626 |
/* 5175 */ "clti_u.h\t\0" |
626 |
/* 5175 */ "clti_u.h\t\0" |
| 627 |
/* 5185 */ "maxi_u.h\t\0" |
627 |
/* 5185 */ "maxi_u.h\t\0" |
| 628 |
/* 5195 */ "min_u.h\t\0" |
628 |
/* 5195 */ "min_u.h\t\0" |
| 629 |
/* 5204 */ "dotp_u.h\t\0" |
629 |
/* 5204 */ "dotp_u.h\t\0" |
| 630 |
/* 5214 */ "aver_u.h\t\0" |
630 |
/* 5214 */ "aver_u.h\t\0" |
| 631 |
/* 5224 */ "subs_u.h\t\0" |
631 |
/* 5224 */ "subs_u.h\t\0" |
| 632 |
/* 5234 */ "adds_u.h\t\0" |
632 |
/* 5234 */ "adds_u.h\t\0" |
| 633 |
/* 5244 */ "subsus_u.h\t\0" |
633 |
/* 5244 */ "subsus_u.h\t\0" |
| 634 |
/* 5256 */ "sat_u.h\t\0" |
634 |
/* 5256 */ "sat_u.h\t\0" |
| 635 |
/* 5265 */ "clt_u.h\t\0" |
635 |
/* 5265 */ "clt_u.h\t\0" |
| 636 |
/* 5274 */ "div_u.h\t\0" |
636 |
/* 5274 */ "div_u.h\t\0" |
| 637 |
/* 5283 */ "max_u.h\t\0" |
637 |
/* 5283 */ "max_u.h\t\0" |
| 638 |
/* 5292 */ "copy_u.h\t\0" |
638 |
/* 5292 */ "copy_u.h\t\0" |
| 639 |
/* 5302 */ "msubv.h\t\0" |
639 |
/* 5302 */ "msubv.h\t\0" |
| 640 |
/* 5311 */ "maddv.h\t\0" |
640 |
/* 5311 */ "maddv.h\t\0" |
| 641 |
/* 5320 */ "pckev.h\t\0" |
641 |
/* 5320 */ "pckev.h\t\0" |
| 642 |
/* 5329 */ "ilvev.h\t\0" |
642 |
/* 5329 */ "ilvev.h\t\0" |
| 643 |
/* 5338 */ "mulv.h\t\0" |
643 |
/* 5338 */ "mulv.h\t\0" |
| 644 |
/* 5346 */ "bz.h\t\0" |
644 |
/* 5346 */ "bz.h\t\0" |
| 645 |
/* 5352 */ "bnz.h\t\0" |
645 |
/* 5352 */ "bnz.h\t\0" |
| 646 |
/* 5359 */ "crc32h\t\0" |
646 |
/* 5359 */ "crc32h\t\0" |
| 647 |
/* 5367 */ "dsbh\t\0" |
647 |
/* 5367 */ "dsbh\t\0" |
| 648 |
/* 5373 */ "wsbh\t\0" |
648 |
/* 5373 */ "wsbh\t\0" |
| 649 |
/* 5379 */ "crc32ch\t\0" |
649 |
/* 5379 */ "crc32ch\t\0" |
| 650 |
/* 5388 */ "seh\t\0" |
650 |
/* 5388 */ "seh\t\0" |
| 651 |
/* 5393 */ "ulh\t\0" |
651 |
/* 5393 */ "ulh\t\0" |
| 652 |
/* 5398 */ "shra.ph\t\0" |
652 |
/* 5398 */ "shra.ph\t\0" |
| 653 |
/* 5407 */ "precrq.qb.ph\t\0" |
653 |
/* 5407 */ "precrq.qb.ph\t\0" |
| 654 |
/* 5421 */ "precr.qb.ph\t\0" |
654 |
/* 5421 */ "precr.qb.ph\t\0" |
| 655 |
/* 5434 */ "precrqu_s.qb.ph\t\0" |
655 |
/* 5434 */ "precrqu_s.qb.ph\t\0" |
| 656 |
/* 5451 */ "cmp.le.ph\t\0" |
656 |
/* 5451 */ "cmp.le.ph\t\0" |
| 657 |
/* 5462 */ "subqh.ph\t\0" |
657 |
/* 5462 */ "subqh.ph\t\0" |
| 658 |
/* 5472 */ "addqh.ph\t\0" |
658 |
/* 5472 */ "addqh.ph\t\0" |
| 659 |
/* 5482 */ "pick.ph\t\0" |
659 |
/* 5482 */ "pick.ph\t\0" |
| 660 |
/* 5491 */ "shll.ph\t\0" |
660 |
/* 5491 */ "shll.ph\t\0" |
| 661 |
/* 5500 */ "repl.ph\t\0" |
661 |
/* 5500 */ "repl.ph\t\0" |
| 662 |
/* 5509 */ "shrl.ph\t\0" |
662 |
/* 5509 */ "shrl.ph\t\0" |
| 663 |
/* 5518 */ "packrl.ph\t\0" |
663 |
/* 5518 */ "packrl.ph\t\0" |
| 664 |
/* 5529 */ "mul.ph\t\0" |
664 |
/* 5529 */ "mul.ph\t\0" |
| 665 |
/* 5537 */ "subq.ph\t\0" |
665 |
/* 5537 */ "subq.ph\t\0" |
| 666 |
/* 5546 */ "addq.ph\t\0" |
666 |
/* 5546 */ "addq.ph\t\0" |
| 667 |
/* 5555 */ "cmp.eq.ph\t\0" |
667 |
/* 5555 */ "cmp.eq.ph\t\0" |
| 668 |
/* 5566 */ "shra_r.ph\t\0" |
668 |
/* 5566 */ "shra_r.ph\t\0" |
| 669 |
/* 5577 */ "subqh_r.ph\t\0" |
669 |
/* 5577 */ "subqh_r.ph\t\0" |
| 670 |
/* 5589 */ "addqh_r.ph\t\0" |
670 |
/* 5589 */ "addqh_r.ph\t\0" |
| 671 |
/* 5601 */ "shrav_r.ph\t\0" |
671 |
/* 5601 */ "shrav_r.ph\t\0" |
| 672 |
/* 5613 */ "shll_s.ph\t\0" |
672 |
/* 5613 */ "shll_s.ph\t\0" |
| 673 |
/* 5624 */ "mul_s.ph\t\0" |
673 |
/* 5624 */ "mul_s.ph\t\0" |
| 674 |
/* 5634 */ "subq_s.ph\t\0" |
674 |
/* 5634 */ "subq_s.ph\t\0" |
| 675 |
/* 5645 */ "addq_s.ph\t\0" |
675 |
/* 5645 */ "addq_s.ph\t\0" |
| 676 |
/* 5656 */ "mulq_s.ph\t\0" |
676 |
/* 5656 */ "mulq_s.ph\t\0" |
| 677 |
/* 5667 */ "absq_s.ph\t\0" |
677 |
/* 5667 */ "absq_s.ph\t\0" |
| 678 |
/* 5678 */ "subu_s.ph\t\0" |
678 |
/* 5678 */ "subu_s.ph\t\0" |
| 679 |
/* 5689 */ "addu_s.ph\t\0" |
679 |
/* 5689 */ "addu_s.ph\t\0" |
| 680 |
/* 5700 */ "shllv_s.ph\t\0" |
680 |
/* 5700 */ "shllv_s.ph\t\0" |
| 681 |
/* 5712 */ "mulq_rs.ph\t\0" |
681 |
/* 5712 */ "mulq_rs.ph\t\0" |
| 682 |
/* 5724 */ "cmp.lt.ph\t\0" |
682 |
/* 5724 */ "cmp.lt.ph\t\0" |
| 683 |
/* 5735 */ "subu.ph\t\0" |
683 |
/* 5735 */ "subu.ph\t\0" |
| 684 |
/* 5744 */ "addu.ph\t\0" |
684 |
/* 5744 */ "addu.ph\t\0" |
| 685 |
/* 5753 */ "shrav.ph\t\0" |
685 |
/* 5753 */ "shrav.ph\t\0" |
| 686 |
/* 5763 */ "shllv.ph\t\0" |
686 |
/* 5763 */ "shllv.ph\t\0" |
| 687 |
/* 5773 */ "replv.ph\t\0" |
687 |
/* 5773 */ "replv.ph\t\0" |
| 688 |
/* 5783 */ "shrlv.ph\t\0" |
688 |
/* 5783 */ "shrlv.ph\t\0" |
| 689 |
/* 5793 */ "dpa.w.ph\t\0" |
689 |
/* 5793 */ "dpa.w.ph\t\0" |
| 690 |
/* 5803 */ "dpaqx_sa.w.ph\t\0" |
690 |
/* 5803 */ "dpaqx_sa.w.ph\t\0" |
| 691 |
/* 5818 */ "dpsqx_sa.w.ph\t\0" |
691 |
/* 5818 */ "dpsqx_sa.w.ph\t\0" |
| 692 |
/* 5833 */ "mulsa.w.ph\t\0" |
692 |
/* 5833 */ "mulsa.w.ph\t\0" |
| 693 |
/* 5845 */ "dpaq_s.w.ph\t\0" |
693 |
/* 5845 */ "dpaq_s.w.ph\t\0" |
| 694 |
/* 5858 */ "mulsaq_s.w.ph\t\0" |
694 |
/* 5858 */ "mulsaq_s.w.ph\t\0" |
| 695 |
/* 5873 */ "dpsq_s.w.ph\t\0" |
695 |
/* 5873 */ "dpsq_s.w.ph\t\0" |
| 696 |
/* 5886 */ "dpaqx_s.w.ph\t\0" |
696 |
/* 5886 */ "dpaqx_s.w.ph\t\0" |
| 697 |
/* 5900 */ "dpsqx_s.w.ph\t\0" |
697 |
/* 5900 */ "dpsqx_s.w.ph\t\0" |
| 698 |
/* 5914 */ "dps.w.ph\t\0" |
698 |
/* 5914 */ "dps.w.ph\t\0" |
| 699 |
/* 5924 */ "dpax.w.ph\t\0" |
699 |
/* 5924 */ "dpax.w.ph\t\0" |
| 700 |
/* 5935 */ "dpsx.w.ph\t\0" |
700 |
/* 5935 */ "dpsx.w.ph\t\0" |
| 701 |
/* 5946 */ "ush\t\0" |
701 |
/* 5946 */ "ush\t\0" |
| 702 |
/* 5951 */ "dmuh\t\0" |
702 |
/* 5951 */ "dmuh\t\0" |
| 703 |
/* 5957 */ "synci\t\0" |
703 |
/* 5957 */ "synci\t\0" |
| 704 |
/* 5964 */ "daddi\t\0" |
704 |
/* 5964 */ "daddi\t\0" |
| 705 |
/* 5971 */ "andi\t\0" |
705 |
/* 5971 */ "andi\t\0" |
| 706 |
/* 5977 */ "tgei\t\0" |
706 |
/* 5977 */ "tgei\t\0" |
| 707 |
/* 5983 */ "snei\t\0" |
707 |
/* 5983 */ "snei\t\0" |
| 708 |
/* 5989 */ "tnei\t\0" |
708 |
/* 5989 */ "tnei\t\0" |
| 709 |
/* 5995 */ "dahi\t\0" |
709 |
/* 5995 */ "dahi\t\0" |
| 710 |
/* 6001 */ "mfhi\t\0" |
710 |
/* 6001 */ "mfhi\t\0" |
| 711 |
/* 6007 */ "mthi\t\0" |
711 |
/* 6007 */ "mthi\t\0" |
| 712 |
/* 6013 */ ".align 2\n\tli\t\0" |
712 |
/* 6013 */ ".align 2\n\tli\t\0" |
| 713 |
/* 6027 */ "dli\t\0" |
713 |
/* 6027 */ "dli\t\0" |
| 714 |
/* 6032 */ "cmpi\t\0" |
714 |
/* 6032 */ "cmpi\t\0" |
| 715 |
/* 6038 */ "seqi\t\0" |
715 |
/* 6038 */ "seqi\t\0" |
| 716 |
/* 6044 */ "teqi\t\0" |
716 |
/* 6044 */ "teqi\t\0" |
| 717 |
/* 6050 */ "xori\t\0" |
717 |
/* 6050 */ "xori\t\0" |
| 718 |
/* 6056 */ "dati\t\0" |
718 |
/* 6056 */ "dati\t\0" |
| 719 |
/* 6062 */ "slti\t\0" |
719 |
/* 6062 */ "slti\t\0" |
| 720 |
/* 6068 */ "tlti\t\0" |
720 |
/* 6068 */ "tlti\t\0" |
| 721 |
/* 6074 */ "daui\t\0" |
721 |
/* 6074 */ "daui\t\0" |
| 722 |
/* 6080 */ "lui\t\0" |
722 |
/* 6080 */ "lui\t\0" |
| 723 |
/* 6085 */ "ginvi\t\0" |
723 |
/* 6085 */ "ginvi\t\0" |
| 724 |
/* 6092 */ "j\t\0" |
724 |
/* 6092 */ "j\t\0" |
| 725 |
/* 6095 */ "break\t\0" |
725 |
/* 6095 */ "break\t\0" |
| 726 |
/* 6102 */ "fork\t\0" |
726 |
/* 6102 */ "fork\t\0" |
| 727 |
/* 6108 */ "cvt.d.l\t\0" |
727 |
/* 6108 */ "cvt.d.l\t\0" |
| 728 |
/* 6117 */ "cvt.s.l\t\0" |
728 |
/* 6117 */ "cvt.s.l\t\0" |
| 729 |
/* 6126 */ "bal\t\0" |
729 |
/* 6126 */ "bal\t\0" |
| 730 |
/* 6131 */ "jal\t\0" |
730 |
/* 6131 */ "jal\t\0" |
| 731 |
/* 6136 */ "bgezal\t\0" |
731 |
/* 6136 */ "bgezal\t\0" |
| 732 |
/* 6144 */ "bltzal\t\0" |
732 |
/* 6144 */ "bltzal\t\0" |
| 733 |
/* 6152 */ "dpau.h.qbl\t\0" |
733 |
/* 6152 */ "dpau.h.qbl\t\0" |
| 734 |
/* 6164 */ "dpsu.h.qbl\t\0" |
734 |
/* 6164 */ "dpsu.h.qbl\t\0" |
| 735 |
/* 6176 */ "muleu_s.ph.qbl\t\0" |
735 |
/* 6176 */ "muleu_s.ph.qbl\t\0" |
| 736 |
/* 6192 */ "preceu.ph.qbl\t\0" |
736 |
/* 6192 */ "preceu.ph.qbl\t\0" |
| 737 |
/* 6207 */ "precequ.ph.qbl\t\0" |
737 |
/* 6207 */ "precequ.ph.qbl\t\0" |
| 738 |
/* 6223 */ "ldl\t\0" |
738 |
/* 6223 */ "ldl\t\0" |
| 739 |
/* 6228 */ "sdl\t\0" |
739 |
/* 6228 */ "sdl\t\0" |
| 740 |
/* 6233 */ "bgel\t\0" |
740 |
/* 6233 */ "bgel\t\0" |
| 741 |
/* 6239 */ "blel\t\0" |
741 |
/* 6239 */ "blel\t\0" |
| 742 |
/* 6245 */ "bnel\t\0" |
742 |
/* 6245 */ "bnel\t\0" |
| 743 |
/* 6251 */ "bc1fl\t\0" |
743 |
/* 6251 */ "bc1fl\t\0" |
| 744 |
/* 6258 */ "maq_sa.w.phl\t\0" |
744 |
/* 6258 */ "maq_sa.w.phl\t\0" |
| 745 |
/* 6272 */ "preceq.w.phl\t\0" |
745 |
/* 6272 */ "preceq.w.phl\t\0" |
| 746 |
/* 6286 */ "maq_s.w.phl\t\0" |
746 |
/* 6286 */ "maq_s.w.phl\t\0" |
| 747 |
/* 6299 */ "muleq_s.w.phl\t\0" |
747 |
/* 6299 */ "muleq_s.w.phl\t\0" |
| 748 |
/* 6314 */ "hypcall\t\0" |
748 |
/* 6314 */ "hypcall\t\0" |
| 749 |
/* 6323 */ "syscall\t\0" |
749 |
/* 6323 */ "syscall\t\0" |
| 750 |
/* 6332 */ "bgezall\t\0" |
750 |
/* 6332 */ "bgezall\t\0" |
| 751 |
/* 6341 */ "bltzall\t\0" |
751 |
/* 6341 */ "bltzall\t\0" |
| 752 |
/* 6350 */ "dsll\t\0" |
752 |
/* 6350 */ "dsll\t\0" |
| 753 |
/* 6356 */ "drol\t\0" |
753 |
/* 6356 */ "drol\t\0" |
| 754 |
/* 6362 */ "cvt.s.pl\t\0" |
754 |
/* 6362 */ "cvt.s.pl\t\0" |
| 755 |
/* 6372 */ "beql\t\0" |
755 |
/* 6372 */ "beql\t\0" |
| 756 |
/* 6378 */ "dsrl\t\0" |
756 |
/* 6378 */ "dsrl\t\0" |
| 757 |
/* 6384 */ "bc1tl\t\0" |
757 |
/* 6384 */ "bc1tl\t\0" |
| 758 |
/* 6391 */ "bgtl\t\0" |
758 |
/* 6391 */ "bgtl\t\0" |
| 759 |
/* 6397 */ "bltl\t\0" |
759 |
/* 6397 */ "bltl\t\0" |
| 760 |
/* 6403 */ "bgeul\t\0" |
760 |
/* 6403 */ "bgeul\t\0" |
| 761 |
/* 6410 */ "bleul\t\0" |
761 |
/* 6410 */ "bleul\t\0" |
| 762 |
/* 6417 */ "dmul\t\0" |
762 |
/* 6417 */ "dmul\t\0" |
| 763 |
/* 6423 */ "bgtul\t\0" |
763 |
/* 6423 */ "bgtul\t\0" |
| 764 |
/* 6430 */ "bltul\t\0" |
764 |
/* 6430 */ "bltul\t\0" |
| 765 |
/* 6437 */ "lwl\t\0" |
765 |
/* 6437 */ "lwl\t\0" |
| 766 |
/* 6442 */ "swl\t\0" |
766 |
/* 6442 */ "swl\t\0" |
| 767 |
/* 6447 */ "bgezl\t\0" |
767 |
/* 6447 */ "bgezl\t\0" |
| 768 |
/* 6454 */ "blezl\t\0" |
768 |
/* 6454 */ "blezl\t\0" |
| 769 |
/* 6461 */ "bgtzl\t\0" |
769 |
/* 6461 */ "bgtzl\t\0" |
| 770 |
/* 6468 */ "bltzl\t\0" |
770 |
/* 6468 */ "bltzl\t\0" |
| 771 |
/* 6475 */ "drem\t\0" |
771 |
/* 6475 */ "drem\t\0" |
| 772 |
/* 6481 */ "dinsm\t\0" |
772 |
/* 6481 */ "dinsm\t\0" |
| 773 |
/* 6488 */ "dextm\t\0" |
773 |
/* 6488 */ "dextm\t\0" |
| 774 |
/* 6495 */ "lwm\t\0" |
774 |
/* 6495 */ "lwm\t\0" |
| 775 |
/* 6500 */ "swm\t\0" |
775 |
/* 6500 */ "swm\t\0" |
| 776 |
/* 6505 */ "balign\t\0" |
776 |
/* 6505 */ "balign\t\0" |
| 777 |
/* 6513 */ "dalign\t\0" |
777 |
/* 6513 */ "dalign\t\0" |
| 778 |
/* 6521 */ "movn\t\0" |
778 |
/* 6521 */ "movn\t\0" |
| 779 |
/* 6527 */ "dclo\t\0" |
779 |
/* 6527 */ "dclo\t\0" |
| 780 |
/* 6533 */ "mflo\t\0" |
780 |
/* 6533 */ "mflo\t\0" |
| 781 |
/* 6539 */ "shilo\t\0" |
781 |
/* 6539 */ "shilo\t\0" |
| 782 |
/* 6546 */ "mtlo\t\0" |
782 |
/* 6546 */ "mtlo\t\0" |
| 783 |
/* 6552 */ "dmulo\t\0" |
783 |
/* 6552 */ "dmulo\t\0" |
| 784 |
/* 6559 */ "dbitswap\t\0" |
784 |
/* 6559 */ "dbitswap\t\0" |
| 785 |
/* 6569 */ "sdbbp\t\0" |
785 |
/* 6569 */ "sdbbp\t\0" |
| 786 |
/* 6576 */ "extpdp\t\0" |
786 |
/* 6576 */ "extpdp\t\0" |
| 787 |
/* 6584 */ "movep\t\0" |
787 |
/* 6584 */ "movep\t\0" |
| 788 |
/* 6591 */ "mthlip\t\0" |
788 |
/* 6591 */ "mthlip\t\0" |
| 789 |
/* 6599 */ "cmp\t\0" |
789 |
/* 6599 */ "cmp\t\0" |
| 790 |
/* 6604 */ "dpop\t\0" |
790 |
/* 6604 */ "dpop\t\0" |
| 791 |
/* 6610 */ "addiur1sp\t\0" |
791 |
/* 6610 */ "addiur1sp\t\0" |
| 792 |
/* 6621 */ "load_ccond_dsp\t\0" |
792 |
/* 6621 */ "load_ccond_dsp\t\0" |
| 793 |
/* 6637 */ "store_ccond_dsp\t\0" |
793 |
/* 6637 */ "store_ccond_dsp\t\0" |
| 794 |
/* 6654 */ "rddsp\t\0" |
794 |
/* 6654 */ "rddsp\t\0" |
| 795 |
/* 6661 */ "wrdsp\t\0" |
795 |
/* 6661 */ "wrdsp\t\0" |
| 796 |
/* 6668 */ "jrcaddiusp\t\0" |
796 |
/* 6668 */ "jrcaddiusp\t\0" |
| 797 |
/* 6680 */ "jraddiusp\t\0" |
797 |
/* 6680 */ "jraddiusp\t\0" |
| 798 |
/* 6691 */ "swsp\t\0" |
798 |
/* 6691 */ "swsp\t\0" |
| 799 |
/* 6697 */ "extp\t\0" |
799 |
/* 6697 */ "extp\t\0" |
| 800 |
/* 6703 */ "dvp\t\0" |
800 |
/* 6703 */ "dvp\t\0" |
| 801 |
/* 6708 */ "evp\t\0" |
801 |
/* 6708 */ "evp\t\0" |
| 802 |
/* 6713 */ "lwp\t\0" |
802 |
/* 6713 */ "lwp\t\0" |
| 803 |
/* 6718 */ "swp\t\0" |
803 |
/* 6718 */ "swp\t\0" |
| 804 |
/* 6723 */ "beq\t\0" |
804 |
/* 6723 */ "beq\t\0" |
| 805 |
/* 6728 */ "seq\t\0" |
805 |
/* 6728 */ "seq\t\0" |
| 806 |
/* 6733 */ "teq\t\0" |
806 |
/* 6733 */ "teq\t\0" |
| 807 |
/* 6738 */ "dpau.h.qbr\t\0" |
807 |
/* 6738 */ "dpau.h.qbr\t\0" |
| 808 |
/* 6750 */ "dpsu.h.qbr\t\0" |
808 |
/* 6750 */ "dpsu.h.qbr\t\0" |
| 809 |
/* 6762 */ "muleu_s.ph.qbr\t\0" |
809 |
/* 6762 */ "muleu_s.ph.qbr\t\0" |
| 810 |
/* 6778 */ "preceu.ph.qbr\t\0" |
810 |
/* 6778 */ "preceu.ph.qbr\t\0" |
| 811 |
/* 6793 */ "precequ.ph.qbr\t\0" |
811 |
/* 6793 */ "precequ.ph.qbr\t\0" |
| 812 |
/* 6809 */ "ldr\t\0" |
812 |
/* 6809 */ "ldr\t\0" |
| 813 |
/* 6814 */ "sdr\t\0" |
813 |
/* 6814 */ "sdr\t\0" |
| 814 |
/* 6819 */ "maq_sa.w.phr\t\0" |
814 |
/* 6819 */ "maq_sa.w.phr\t\0" |
| 815 |
/* 6833 */ "preceq.w.phr\t\0" |
815 |
/* 6833 */ "preceq.w.phr\t\0" |
| 816 |
/* 6847 */ "maq_s.w.phr\t\0" |
816 |
/* 6847 */ "maq_s.w.phr\t\0" |
| 817 |
/* 6860 */ "muleq_s.w.phr\t\0" |
817 |
/* 6860 */ "muleq_s.w.phr\t\0" |
| 818 |
/* 6875 */ "jr\t\0" |
818 |
/* 6875 */ "jr\t\0" |
| 819 |
/* 6879 */ "jalr\t\0" |
819 |
/* 6879 */ "jalr\t\0" |
| 820 |
/* 6885 */ "nor\t\0" |
820 |
/* 6885 */ "nor\t\0" |
| 821 |
/* 6890 */ "dror\t\0" |
821 |
/* 6890 */ "dror\t\0" |
| 822 |
/* 6896 */ "xor\t\0" |
822 |
/* 6896 */ "xor\t\0" |
| 823 |
/* 6901 */ "rdpgpr\t\0" |
823 |
/* 6901 */ "rdpgpr\t\0" |
| 824 |
/* 6909 */ "wrpgpr\t\0" |
824 |
/* 6909 */ "wrpgpr\t\0" |
| 825 |
/* 6917 */ "mftr\t\0" |
825 |
/* 6917 */ "mftr\t\0" |
| 826 |
/* 6923 */ "drotr\t\0" |
826 |
/* 6923 */ "drotr\t\0" |
| 827 |
/* 6930 */ "mttr\t\0" |
827 |
/* 6930 */ "mttr\t\0" |
| 828 |
/* 6936 */ "rdhwr\t\0" |
828 |
/* 6936 */ "rdhwr\t\0" |
| 829 |
/* 6943 */ "lwr\t\0" |
829 |
/* 6943 */ "lwr\t\0" |
| 830 |
/* 6948 */ "swr\t\0" |
830 |
/* 6948 */ "swr\t\0" |
| 831 |
/* 6953 */ "mina.s\t\0" |
831 |
/* 6953 */ "mina.s\t\0" |
| 832 |
/* 6961 */ "maxa.s\t\0" |
832 |
/* 6961 */ "maxa.s\t\0" |
| 833 |
/* 6969 */ "nmsub.s\t\0" |
833 |
/* 6969 */ "nmsub.s\t\0" |
| 834 |
/* 6978 */ "cvt.d.s\t\0" |
834 |
/* 6978 */ "cvt.d.s\t\0" |
| 835 |
/* 6987 */ "nmadd.s\t\0" |
835 |
/* 6987 */ "nmadd.s\t\0" |
| 836 |
/* 6996 */ "c.nge.s\t\0" |
836 |
/* 6996 */ "c.nge.s\t\0" |
| 837 |
/* 7005 */ "c.le.s\t\0" |
837 |
/* 7005 */ "c.le.s\t\0" |
| 838 |
/* 7013 */ "cmp.le.s\t\0" |
838 |
/* 7013 */ "cmp.le.s\t\0" |
| 839 |
/* 7023 */ "c.ngle.s\t\0" |
839 |
/* 7023 */ "c.ngle.s\t\0" |
| 840 |
/* 7033 */ "c.ole.s\t\0" |
840 |
/* 7033 */ "c.ole.s\t\0" |
| 841 |
/* 7042 */ "cmp.sle.s\t\0" |
841 |
/* 7042 */ "cmp.sle.s\t\0" |
| 842 |
/* 7053 */ "c.ule.s\t\0" |
842 |
/* 7053 */ "c.ule.s\t\0" |
| 843 |
/* 7062 */ "cmp.ule.s\t\0" |
843 |
/* 7062 */ "cmp.ule.s\t\0" |
| 844 |
/* 7073 */ "cmp.sule.s\t\0" |
844 |
/* 7073 */ "cmp.sule.s\t\0" |
| 845 |
/* 7085 */ "c.f.s\t\0" |
845 |
/* 7085 */ "c.f.s\t\0" |
| 846 |
/* 7092 */ "cmp.af.s\t\0" |
846 |
/* 7092 */ "cmp.af.s\t\0" |
| 847 |
/* 7102 */ "cmp.saf.s\t\0" |
847 |
/* 7102 */ "cmp.saf.s\t\0" |
| 848 |
/* 7113 */ "msubf.s\t\0" |
848 |
/* 7113 */ "msubf.s\t\0" |
| 849 |
/* 7122 */ "maddf.s\t\0" |
849 |
/* 7122 */ "maddf.s\t\0" |
| 850 |
/* 7131 */ "c.sf.s\t\0" |
850 |
/* 7131 */ "c.sf.s\t\0" |
| 851 |
/* 7139 */ "movf.s\t\0" |
851 |
/* 7139 */ "movf.s\t\0" |
| 852 |
/* 7147 */ "neg.s\t\0" |
852 |
/* 7147 */ "neg.s\t\0" |
| 853 |
/* 7154 */ "li.s\t\0" |
853 |
/* 7154 */ "li.s\t\0" |
| 854 |
/* 7160 */ "trunc.l.s\t\0" |
854 |
/* 7160 */ "trunc.l.s\t\0" |
| 855 |
/* 7171 */ "round.l.s\t\0" |
855 |
/* 7171 */ "round.l.s\t\0" |
| 856 |
/* 7182 */ "ceil.l.s\t\0" |
856 |
/* 7182 */ "ceil.l.s\t\0" |
| 857 |
/* 7192 */ "floor.l.s\t\0" |
857 |
/* 7192 */ "floor.l.s\t\0" |
| 858 |
/* 7203 */ "cvt.l.s\t\0" |
858 |
/* 7203 */ "cvt.l.s\t\0" |
| 859 |
/* 7212 */ "sel.s\t\0" |
859 |
/* 7212 */ "sel.s\t\0" |
| 860 |
/* 7219 */ "c.ngl.s\t\0" |
860 |
/* 7219 */ "c.ngl.s\t\0" |
| 861 |
/* 7228 */ "mul.s\t\0" |
861 |
/* 7228 */ "mul.s\t\0" |
| 862 |
/* 7235 */ "min.s\t\0" |
862 |
/* 7235 */ "min.s\t\0" |
| 863 |
/* 7242 */ "c.un.s\t\0" |
863 |
/* 7242 */ "c.un.s\t\0" |
| 864 |
/* 7250 */ "cmp.un.s\t\0" |
864 |
/* 7250 */ "cmp.un.s\t\0" |
| 865 |
/* 7260 */ "cmp.sun.s\t\0" |
865 |
/* 7260 */ "cmp.sun.s\t\0" |
| 866 |
/* 7271 */ "movn.s\t\0" |
866 |
/* 7271 */ "movn.s\t\0" |
| 867 |
/* 7279 */ "recip.s\t\0" |
867 |
/* 7279 */ "recip.s\t\0" |
| 868 |
/* 7288 */ "c.eq.s\t\0" |
868 |
/* 7288 */ "c.eq.s\t\0" |
| 869 |
/* 7296 */ "cmp.eq.s\t\0" |
869 |
/* 7296 */ "cmp.eq.s\t\0" |
| 870 |
/* 7306 */ "c.seq.s\t\0" |
870 |
/* 7306 */ "c.seq.s\t\0" |
| 871 |
/* 7315 */ "cmp.seq.s\t\0" |
871 |
/* 7315 */ "cmp.seq.s\t\0" |
| 872 |
/* 7326 */ "c.ueq.s\t\0" |
872 |
/* 7326 */ "c.ueq.s\t\0" |
| 873 |
/* 7335 */ "cmp.ueq.s\t\0" |
873 |
/* 7335 */ "cmp.ueq.s\t\0" |
| 874 |
/* 7346 */ "cmp.sueq.s\t\0" |
874 |
/* 7346 */ "cmp.sueq.s\t\0" |
| 875 |
/* 7358 */ "abs.s\t\0" |
875 |
/* 7358 */ "abs.s\t\0" |
| 876 |
/* 7365 */ "cvt.ps.s\t\0" |
876 |
/* 7365 */ "cvt.ps.s\t\0" |
| 877 |
/* 7375 */ "class.s\t\0" |
877 |
/* 7375 */ "class.s\t\0" |
| 878 |
/* 7384 */ "c.ngt.s\t\0" |
878 |
/* 7384 */ "c.ngt.s\t\0" |
| 879 |
/* 7393 */ "c.lt.s\t\0" |
879 |
/* 7393 */ "c.lt.s\t\0" |
| 880 |
/* 7401 */ "cmp.lt.s\t\0" |
880 |
/* 7401 */ "cmp.lt.s\t\0" |
| 881 |
/* 7411 */ "c.olt.s\t\0" |
881 |
/* 7411 */ "c.olt.s\t\0" |
| 882 |
/* 7420 */ "cmp.slt.s\t\0" |
882 |
/* 7420 */ "cmp.slt.s\t\0" |
| 883 |
/* 7431 */ "c.ult.s\t\0" |
883 |
/* 7431 */ "c.ult.s\t\0" |
| 884 |
/* 7440 */ "cmp.ult.s\t\0" |
884 |
/* 7440 */ "cmp.ult.s\t\0" |
| 885 |
/* 7451 */ "cmp.sult.s\t\0" |
885 |
/* 7451 */ "cmp.sult.s\t\0" |
| 886 |
/* 7463 */ "rint.s\t\0" |
886 |
/* 7463 */ "rint.s\t\0" |
| 887 |
/* 7471 */ "rsqrt.s\t\0" |
887 |
/* 7471 */ "rsqrt.s\t\0" |
| 888 |
/* 7480 */ "movt.s\t\0" |
888 |
/* 7480 */ "movt.s\t\0" |
| 889 |
/* 7488 */ "div.s\t\0" |
889 |
/* 7488 */ "div.s\t\0" |
| 890 |
/* 7495 */ "mov.s\t\0" |
890 |
/* 7495 */ "mov.s\t\0" |
| 891 |
/* 7502 */ "trunc.w.s\t\0" |
891 |
/* 7502 */ "trunc.w.s\t\0" |
| 892 |
/* 7513 */ "round.w.s\t\0" |
892 |
/* 7513 */ "round.w.s\t\0" |
| 893 |
/* 7524 */ "ceil.w.s\t\0" |
893 |
/* 7524 */ "ceil.w.s\t\0" |
| 894 |
/* 7534 */ "floor.w.s\t\0" |
894 |
/* 7534 */ "floor.w.s\t\0" |
| 895 |
/* 7545 */ "cvt.w.s\t\0" |
895 |
/* 7545 */ "cvt.w.s\t\0" |
| 896 |
/* 7554 */ "max.s\t\0" |
896 |
/* 7554 */ "max.s\t\0" |
| 897 |
/* 7561 */ "selnez.s\t\0" |
897 |
/* 7561 */ "selnez.s\t\0" |
| 898 |
/* 7571 */ "seleqz.s\t\0" |
898 |
/* 7571 */ "seleqz.s\t\0" |
| 899 |
/* 7581 */ "movz.s\t\0" |
899 |
/* 7581 */ "movz.s\t\0" |
| 900 |
/* 7589 */ "abs\t\0" |
900 |
/* 7589 */ "abs\t\0" |
| 901 |
/* 7594 */ "jals\t\0" |
901 |
/* 7594 */ "jals\t\0" |
| 902 |
/* 7600 */ "bgezals\t\0" |
902 |
/* 7600 */ "bgezals\t\0" |
| 903 |
/* 7609 */ "bltzals\t\0" |
903 |
/* 7609 */ "bltzals\t\0" |
| 904 |
/* 7618 */ "cins\t\0" |
904 |
/* 7618 */ "cins\t\0" |
| 905 |
/* 7624 */ "dins\t\0" |
905 |
/* 7624 */ "dins\t\0" |
| 906 |
/* 7630 */ "sub.ps\t\0" |
906 |
/* 7630 */ "sub.ps\t\0" |
| 907 |
/* 7638 */ "add.ps\t\0" |
907 |
/* 7638 */ "add.ps\t\0" |
| 908 |
/* 7646 */ "pll.ps\t\0" |
908 |
/* 7646 */ "pll.ps\t\0" |
| 909 |
/* 7654 */ "mul.ps\t\0" |
909 |
/* 7654 */ "mul.ps\t\0" |
| 910 |
/* 7662 */ "pul.ps\t\0" |
910 |
/* 7662 */ "pul.ps\t\0" |
| 911 |
/* 7670 */ "addr.ps\t\0" |
911 |
/* 7670 */ "addr.ps\t\0" |
| 912 |
/* 7679 */ "mulr.ps\t\0" |
912 |
/* 7679 */ "mulr.ps\t\0" |
| 913 |
/* 7688 */ "plu.ps\t\0" |
913 |
/* 7688 */ "plu.ps\t\0" |
| 914 |
/* 7696 */ "puu.ps\t\0" |
914 |
/* 7696 */ "puu.ps\t\0" |
| 915 |
/* 7704 */ "cvt.pw.ps\t\0" |
915 |
/* 7704 */ "cvt.pw.ps\t\0" |
| 916 |
/* 7715 */ "jalrs\t\0" |
916 |
/* 7715 */ "jalrs\t\0" |
| 917 |
/* 7722 */ "exts\t\0" |
917 |
/* 7722 */ "exts\t\0" |
| 918 |
/* 7728 */ "lwxs\t\0" |
918 |
/* 7728 */ "lwxs\t\0" |
| 919 |
/* 7734 */ "bc1t\t\0" |
919 |
/* 7734 */ "bc1t\t\0" |
| 920 |
/* 7740 */ "bgt\t\0" |
920 |
/* 7740 */ "bgt\t\0" |
| 921 |
/* 7745 */ "sgt\t\0" |
921 |
/* 7745 */ "sgt\t\0" |
| 922 |
/* 7750 */ "wait\t\0" |
922 |
/* 7750 */ "wait\t\0" |
| 923 |
/* 7756 */ "blt\t\0" |
923 |
/* 7756 */ "blt\t\0" |
| 924 |
/* 7761 */ "slt\t\0" |
924 |
/* 7761 */ "slt\t\0" |
| 925 |
/* 7766 */ "tlt\t\0" |
925 |
/* 7766 */ "tlt\t\0" |
| 926 |
/* 7771 */ "dmult\t\0" |
926 |
/* 7771 */ "dmult\t\0" |
| 927 |
/* 7778 */ "dmt\t\0" |
927 |
/* 7778 */ "dmt\t\0" |
| 928 |
/* 7783 */ "emt\t\0" |
928 |
/* 7783 */ "emt\t\0" |
| 929 |
/* 7788 */ "not\t\0" |
929 |
/* 7788 */ "not\t\0" |
| 930 |
/* 7793 */ "ginvt\t\0" |
930 |
/* 7793 */ "ginvt\t\0" |
| 931 |
/* 7800 */ "movt\t\0" |
931 |
/* 7800 */ "movt\t\0" |
| 932 |
/* 7806 */ "dext\t\0" |
932 |
/* 7806 */ "dext\t\0" |
| 933 |
/* 7812 */ "lbu\t\0" |
933 |
/* 7812 */ "lbu\t\0" |
| 934 |
/* 7817 */ "dsubu\t\0" |
934 |
/* 7817 */ "dsubu\t\0" |
| 935 |
/* 7824 */ "msubu\t\0" |
935 |
/* 7824 */ "msubu\t\0" |
| 936 |
/* 7831 */ "baddu\t\0" |
936 |
/* 7831 */ "baddu\t\0" |
| 937 |
/* 7838 */ "daddu\t\0" |
937 |
/* 7838 */ "daddu\t\0" |
| 938 |
/* 7845 */ "maddu\t\0" |
938 |
/* 7845 */ "maddu\t\0" |
| 939 |
/* 7852 */ "dmodu\t\0" |
939 |
/* 7852 */ "dmodu\t\0" |
| 940 |
/* 7859 */ "bgeu\t\0" |
940 |
/* 7859 */ "bgeu\t\0" |
| 941 |
/* 7865 */ "sgeu\t\0" |
941 |
/* 7865 */ "sgeu\t\0" |
| 942 |
/* 7871 */ "tgeu\t\0" |
942 |
/* 7871 */ "tgeu\t\0" |
| 943 |
/* 7877 */ "bleu\t\0" |
943 |
/* 7877 */ "bleu\t\0" |
| 944 |
/* 7883 */ "sleu\t\0" |
944 |
/* 7883 */ "sleu\t\0" |
| 945 |
/* 7889 */ "ulhu\t\0" |
945 |
/* 7889 */ "ulhu\t\0" |
| 946 |
/* 7895 */ "dmuhu\t\0" |
946 |
/* 7895 */ "dmuhu\t\0" |
| 947 |
/* 7902 */ "daddiu\t\0" |
947 |
/* 7902 */ "daddiu\t\0" |
| 948 |
/* 7910 */ "tgeiu\t\0" |
948 |
/* 7910 */ "tgeiu\t\0" |
| 949 |
/* 7917 */ "sltiu\t\0" |
949 |
/* 7917 */ "sltiu\t\0" |
| 950 |
/* 7924 */ "tltiu\t\0" |
950 |
/* 7924 */ "tltiu\t\0" |
| 951 |
/* 7931 */ "v3mulu\t\0" |
951 |
/* 7931 */ "v3mulu\t\0" |
| 952 |
/* 7939 */ "dmulu\t\0" |
952 |
/* 7939 */ "dmulu\t\0" |
| 953 |
/* 7946 */ "vmulu\t\0" |
953 |
/* 7946 */ "vmulu\t\0" |
| 954 |
/* 7953 */ "dremu\t\0" |
954 |
/* 7953 */ "dremu\t\0" |
| 955 |
/* 7960 */ "dmulou\t\0" |
955 |
/* 7960 */ "dmulou\t\0" |
| 956 |
/* 7968 */ "cvt.s.pu\t\0" |
956 |
/* 7968 */ "cvt.s.pu\t\0" |
| 957 |
/* 7978 */ "dinsu\t\0" |
957 |
/* 7978 */ "dinsu\t\0" |
| 958 |
/* 7985 */ "bgtu\t\0" |
958 |
/* 7985 */ "bgtu\t\0" |
| 959 |
/* 7991 */ "sgtu\t\0" |
959 |
/* 7991 */ "sgtu\t\0" |
| 960 |
/* 7997 */ "bltu\t\0" |
960 |
/* 7997 */ "bltu\t\0" |
| 961 |
/* 8003 */ "sltu\t\0" |
961 |
/* 8003 */ "sltu\t\0" |
| 962 |
/* 8009 */ "tltu\t\0" |
962 |
/* 8009 */ "tltu\t\0" |
| 963 |
/* 8015 */ "dmultu\t\0" |
963 |
/* 8015 */ "dmultu\t\0" |
| 964 |
/* 8023 */ "dextu\t\0" |
964 |
/* 8023 */ "dextu\t\0" |
| 965 |
/* 8030 */ "ddivu\t\0" |
965 |
/* 8030 */ "ddivu\t\0" |
| 966 |
/* 8037 */ "lwu\t\0" |
966 |
/* 8037 */ "lwu\t\0" |
| 967 |
/* 8042 */ "and.v\t\0" |
967 |
/* 8042 */ "and.v\t\0" |
| 968 |
/* 8049 */ "move.v\t\0" |
968 |
/* 8049 */ "move.v\t\0" |
| 969 |
/* 8057 */ "bsel.v\t\0" |
969 |
/* 8057 */ "bsel.v\t\0" |
| 970 |
/* 8065 */ "nor.v\t\0" |
970 |
/* 8065 */ "nor.v\t\0" |
| 971 |
/* 8072 */ "xor.v\t\0" |
971 |
/* 8072 */ "xor.v\t\0" |
| 972 |
/* 8079 */ "bz.v\t\0" |
972 |
/* 8079 */ "bz.v\t\0" |
| 973 |
/* 8085 */ "bmz.v\t\0" |
973 |
/* 8085 */ "bmz.v\t\0" |
| 974 |
/* 8092 */ "bnz.v\t\0" |
974 |
/* 8092 */ "bnz.v\t\0" |
| 975 |
/* 8099 */ "bmnz.v\t\0" |
975 |
/* 8099 */ "bmnz.v\t\0" |
| 976 |
/* 8107 */ "dsrav\t\0" |
976 |
/* 8107 */ "dsrav\t\0" |
| 977 |
/* 8114 */ "bitrev\t\0" |
977 |
/* 8114 */ "bitrev\t\0" |
| 978 |
/* 8122 */ "ddiv\t\0" |
978 |
/* 8122 */ "ddiv\t\0" |
| 979 |
/* 8128 */ "dsllv\t\0" |
979 |
/* 8128 */ "dsllv\t\0" |
| 980 |
/* 8135 */ "dsrlv\t\0" |
980 |
/* 8135 */ "dsrlv\t\0" |
| 981 |
/* 8142 */ "shilov\t\0" |
981 |
/* 8142 */ "shilov\t\0" |
| 982 |
/* 8150 */ "extpdpv\t\0" |
982 |
/* 8150 */ "extpdpv\t\0" |
| 983 |
/* 8159 */ "extpv\t\0" |
983 |
/* 8159 */ "extpv\t\0" |
| 984 |
/* 8166 */ "drotrv\t\0" |
984 |
/* 8166 */ "drotrv\t\0" |
| 985 |
/* 8174 */ "insv\t\0" |
985 |
/* 8174 */ "insv\t\0" |
| 986 |
/* 8180 */ "flog2.w\t\0" |
986 |
/* 8180 */ "flog2.w\t\0" |
| 987 |
/* 8189 */ "fexp2.w\t\0" |
987 |
/* 8189 */ "fexp2.w\t\0" |
| 988 |
/* 8198 */ "add_a.w\t\0" |
988 |
/* 8198 */ "add_a.w\t\0" |
| 989 |
/* 8207 */ "fmin_a.w\t\0" |
989 |
/* 8207 */ "fmin_a.w\t\0" |
| 990 |
/* 8217 */ "adds_a.w\t\0" |
990 |
/* 8217 */ "adds_a.w\t\0" |
| 991 |
/* 8227 */ "fmax_a.w\t\0" |
991 |
/* 8227 */ "fmax_a.w\t\0" |
| 992 |
/* 8237 */ "sra.w\t\0" |
992 |
/* 8237 */ "sra.w\t\0" |
| 993 |
/* 8244 */ "fsub.w\t\0" |
993 |
/* 8244 */ "fsub.w\t\0" |
| 994 |
/* 8252 */ "fmsub.w\t\0" |
994 |
/* 8252 */ "fmsub.w\t\0" |
| 995 |
/* 8261 */ "nloc.w\t\0" |
995 |
/* 8261 */ "nloc.w\t\0" |
| 996 |
/* 8269 */ "nlzc.w\t\0" |
996 |
/* 8269 */ "nlzc.w\t\0" |
| 997 |
/* 8277 */ "cvt.d.w\t\0" |
997 |
/* 8277 */ "cvt.d.w\t\0" |
| 998 |
/* 8286 */ "fadd.w\t\0" |
998 |
/* 8286 */ "fadd.w\t\0" |
| 999 |
/* 8294 */ "fmadd.w\t\0" |
999 |
/* 8294 */ "fmadd.w\t\0" |
| 1000 |
/* 8303 */ "sld.w\t\0" |
1000 |
/* 8303 */ "sld.w\t\0" |
| 1001 |
/* 8310 */ "pckod.w\t\0" |
1001 |
/* 8310 */ "pckod.w\t\0" |
| 1002 |
/* 8319 */ "ilvod.w\t\0" |
1002 |
/* 8319 */ "ilvod.w\t\0" |
| 1003 |
/* 8328 */ "fcle.w\t\0" |
1003 |
/* 8328 */ "fcle.w\t\0" |
| 1004 |
/* 8336 */ "fsle.w\t\0" |
1004 |
/* 8336 */ "fsle.w\t\0" |
| 1005 |
/* 8344 */ "fcule.w\t\0" |
1005 |
/* 8344 */ "fcule.w\t\0" |
| 1006 |
/* 8353 */ "fsule.w\t\0" |
1006 |
/* 8353 */ "fsule.w\t\0" |
| 1007 |
/* 8362 */ "fcne.w\t\0" |
1007 |
/* 8362 */ "fcne.w\t\0" |
| 1008 |
/* 8370 */ "fsne.w\t\0" |
1008 |
/* 8370 */ "fsne.w\t\0" |
| 1009 |
/* 8378 */ "fcune.w\t\0" |
1009 |
/* 8378 */ "fcune.w\t\0" |
| 1010 |
/* 8387 */ "fsune.w\t\0" |
1010 |
/* 8387 */ "fsune.w\t\0" |
| 1011 |
/* 8396 */ "insve.w\t\0" |
1011 |
/* 8396 */ "insve.w\t\0" |
| 1012 |
/* 8405 */ "fcaf.w\t\0" |
1012 |
/* 8405 */ "fcaf.w\t\0" |
| 1013 |
/* 8413 */ "fsaf.w\t\0" |
1013 |
/* 8413 */ "fsaf.w\t\0" |
| 1014 |
/* 8421 */ "vshf.w\t\0" |
1014 |
/* 8421 */ "vshf.w\t\0" |
| 1015 |
/* 8429 */ "bneg.w\t\0" |
1015 |
/* 8429 */ "bneg.w\t\0" |
| 1016 |
/* 8437 */ "precr_sra.ph.w\t\0" |
1016 |
/* 8437 */ "precr_sra.ph.w\t\0" |
| 1017 |
/* 8453 */ "precrq.ph.w\t\0" |
1017 |
/* 8453 */ "precrq.ph.w\t\0" |
| 1018 |
/* 8466 */ "precr_sra_r.ph.w\t\0" |
1018 |
/* 8466 */ "precr_sra_r.ph.w\t\0" |
| 1019 |
/* 8484 */ "precrq_rs.ph.w\t\0" |
1019 |
/* 8484 */ "precrq_rs.ph.w\t\0" |
| 1020 |
/* 8500 */ "subqh.w\t\0" |
1020 |
/* 8500 */ "subqh.w\t\0" |
| 1021 |
/* 8509 */ "addqh.w\t\0" |
1021 |
/* 8509 */ "addqh.w\t\0" |
| 1022 |
/* 8518 */ "srai.w\t\0" |
1022 |
/* 8518 */ "srai.w\t\0" |
| 1023 |
/* 8526 */ "sldi.w\t\0" |
1023 |
/* 8526 */ "sldi.w\t\0" |
| 1024 |
/* 8534 */ "bnegi.w\t\0" |
1024 |
/* 8534 */ "bnegi.w\t\0" |
| 1025 |
/* 8543 */ "slli.w\t\0" |
1025 |
/* 8543 */ "slli.w\t\0" |
| 1026 |
/* 8551 */ "srli.w\t\0" |
1026 |
/* 8551 */ "srli.w\t\0" |
| 1027 |
/* 8559 */ "binsli.w\t\0" |
1027 |
/* 8559 */ "binsli.w\t\0" |
| 1028 |
/* 8569 */ "ceqi.w\t\0" |
1028 |
/* 8569 */ "ceqi.w\t\0" |
| 1029 |
/* 8577 */ "srari.w\t\0" |
1029 |
/* 8577 */ "srari.w\t\0" |
| 1030 |
/* 8586 */ "bclri.w\t\0" |
1030 |
/* 8586 */ "bclri.w\t\0" |
| 1031 |
/* 8595 */ "srlri.w\t\0" |
1031 |
/* 8595 */ "srlri.w\t\0" |
| 1032 |
/* 8604 */ "binsri.w\t\0" |
1032 |
/* 8604 */ "binsri.w\t\0" |
| 1033 |
/* 8614 */ "splati.w\t\0" |
1033 |
/* 8614 */ "splati.w\t\0" |
| 1034 |
/* 8624 */ "bseti.w\t\0" |
1034 |
/* 8624 */ "bseti.w\t\0" |
| 1035 |
/* 8633 */ "subvi.w\t\0" |
1035 |
/* 8633 */ "subvi.w\t\0" |
| 1036 |
/* 8642 */ "addvi.w\t\0" |
1036 |
/* 8642 */ "addvi.w\t\0" |
| 1037 |
/* 8651 */ "dpaq_sa.l.w\t\0" |
1037 |
/* 8651 */ "dpaq_sa.l.w\t\0" |
| 1038 |
/* 8664 */ "dpsq_sa.l.w\t\0" |
1038 |
/* 8664 */ "dpsq_sa.l.w\t\0" |
| 1039 |
/* 8677 */ "fill.w\t\0" |
1039 |
/* 8677 */ "fill.w\t\0" |
| 1040 |
/* 8685 */ "sll.w\t\0" |
1040 |
/* 8685 */ "sll.w\t\0" |
| 1041 |
/* 8692 */ "fexupl.w\t\0" |
1041 |
/* 8692 */ "fexupl.w\t\0" |
| 1042 |
/* 8702 */ "ffql.w\t\0" |
1042 |
/* 8702 */ "ffql.w\t\0" |
| 1043 |
/* 8710 */ "srl.w\t\0" |
1043 |
/* 8710 */ "srl.w\t\0" |
| 1044 |
/* 8717 */ "binsl.w\t\0" |
1044 |
/* 8717 */ "binsl.w\t\0" |
| 1045 |
/* 8726 */ "fmul.w\t\0" |
1045 |
/* 8726 */ "fmul.w\t\0" |
| 1046 |
/* 8734 */ "ilvl.w\t\0" |
1046 |
/* 8734 */ "ilvl.w\t\0" |
| 1047 |
/* 8742 */ "fmin.w\t\0" |
1047 |
/* 8742 */ "fmin.w\t\0" |
| 1048 |
/* 8750 */ "fcun.w\t\0" |
1048 |
/* 8750 */ "fcun.w\t\0" |
| 1049 |
/* 8758 */ "fsun.w\t\0" |
1049 |
/* 8758 */ "fsun.w\t\0" |
| 1050 |
/* 8766 */ "fexdo.w\t\0" |
1050 |
/* 8766 */ "fexdo.w\t\0" |
| 1051 |
/* 8775 */ "frcp.w\t\0" |
1051 |
/* 8775 */ "frcp.w\t\0" |
| 1052 |
/* 8783 */ "msub_q.w\t\0" |
1052 |
/* 8783 */ "msub_q.w\t\0" |
| 1053 |
/* 8793 */ "madd_q.w\t\0" |
1053 |
/* 8793 */ "madd_q.w\t\0" |
| 1054 |
/* 8803 */ "mul_q.w\t\0" |
1054 |
/* 8803 */ "mul_q.w\t\0" |
| 1055 |
/* 8812 */ "msubr_q.w\t\0" |
1055 |
/* 8812 */ "msubr_q.w\t\0" |
| 1056 |
/* 8823 */ "maddr_q.w\t\0" |
1056 |
/* 8823 */ "maddr_q.w\t\0" |
| 1057 |
/* 8834 */ "mulr_q.w\t\0" |
1057 |
/* 8834 */ "mulr_q.w\t\0" |
| 1058 |
/* 8844 */ "fceq.w\t\0" |
1058 |
/* 8844 */ "fceq.w\t\0" |
| 1059 |
/* 8852 */ "fseq.w\t\0" |
1059 |
/* 8852 */ "fseq.w\t\0" |
| 1060 |
/* 8860 */ "fcueq.w\t\0" |
1060 |
/* 8860 */ "fcueq.w\t\0" |
| 1061 |
/* 8869 */ "fsueq.w\t\0" |
1061 |
/* 8869 */ "fsueq.w\t\0" |
| 1062 |
/* 8878 */ "ftq.w\t\0" |
1062 |
/* 8878 */ "ftq.w\t\0" |
| 1063 |
/* 8885 */ "shra_r.w\t\0" |
1063 |
/* 8885 */ "shra_r.w\t\0" |
| 1064 |
/* 8895 */ "subqh_r.w\t\0" |
1064 |
/* 8895 */ "subqh_r.w\t\0" |
| 1065 |
/* 8906 */ "addqh_r.w\t\0" |
1065 |
/* 8906 */ "addqh_r.w\t\0" |
| 1066 |
/* 8917 */ "extr_r.w\t\0" |
1066 |
/* 8917 */ "extr_r.w\t\0" |
| 1067 |
/* 8927 */ "shrav_r.w\t\0" |
1067 |
/* 8927 */ "shrav_r.w\t\0" |
| 1068 |
/* 8938 */ "extrv_r.w\t\0" |
1068 |
/* 8938 */ "extrv_r.w\t\0" |
| 1069 |
/* 8949 */ "srar.w\t\0" |
1069 |
/* 8949 */ "srar.w\t\0" |
| 1070 |
/* 8957 */ "bclr.w\t\0" |
1070 |
/* 8957 */ "bclr.w\t\0" |
| 1071 |
/* 8965 */ "srlr.w\t\0" |
1071 |
/* 8965 */ "srlr.w\t\0" |
| 1072 |
/* 8973 */ "fcor.w\t\0" |
1072 |
/* 8973 */ "fcor.w\t\0" |
| 1073 |
/* 8981 */ "fsor.w\t\0" |
1073 |
/* 8981 */ "fsor.w\t\0" |
| 1074 |
/* 8989 */ "fexupr.w\t\0" |
1074 |
/* 8989 */ "fexupr.w\t\0" |
| 1075 |
/* 8999 */ "ffqr.w\t\0" |
1075 |
/* 8999 */ "ffqr.w\t\0" |
| 1076 |
/* 9007 */ "binsr.w\t\0" |
1076 |
/* 9007 */ "binsr.w\t\0" |
| 1077 |
/* 9016 */ "extr.w\t\0" |
1077 |
/* 9016 */ "extr.w\t\0" |
| 1078 |
/* 9024 */ "ilvr.w\t\0" |
1078 |
/* 9024 */ "ilvr.w\t\0" |
| 1079 |
/* 9032 */ "cvt.s.w\t\0" |
1079 |
/* 9032 */ "cvt.s.w\t\0" |
| 1080 |
/* 9041 */ "asub_s.w\t\0" |
1080 |
/* 9041 */ "asub_s.w\t\0" |
| 1081 |
/* 9051 */ "hsub_s.w\t\0" |
1081 |
/* 9051 */ "hsub_s.w\t\0" |
| 1082 |
/* 9061 */ "dpsub_s.w\t\0" |
1082 |
/* 9061 */ "dpsub_s.w\t\0" |
| 1083 |
/* 9072 */ "ftrunc_s.w\t\0" |
1083 |
/* 9072 */ "ftrunc_s.w\t\0" |
| 1084 |
/* 9084 */ "hadd_s.w\t\0" |
1084 |
/* 9084 */ "hadd_s.w\t\0" |
| 1085 |
/* 9094 */ "dpadd_s.w\t\0" |
1085 |
/* 9094 */ "dpadd_s.w\t\0" |
| 1086 |
/* 9105 */ "mod_s.w\t\0" |
1086 |
/* 9105 */ "mod_s.w\t\0" |
| 1087 |
/* 9114 */ "cle_s.w\t\0" |
1087 |
/* 9114 */ "cle_s.w\t\0" |
| 1088 |
/* 9123 */ "ave_s.w\t\0" |
1088 |
/* 9123 */ "ave_s.w\t\0" |
| 1089 |
/* 9132 */ "clei_s.w\t\0" |
1089 |
/* 9132 */ "clei_s.w\t\0" |
| 1090 |
/* 9142 */ "mini_s.w\t\0" |
1090 |
/* 9142 */ "mini_s.w\t\0" |
| 1091 |
/* 9152 */ "clti_s.w\t\0" |
1091 |
/* 9152 */ "clti_s.w\t\0" |
| 1092 |
/* 9162 */ "maxi_s.w\t\0" |
1092 |
/* 9162 */ "maxi_s.w\t\0" |
| 1093 |
/* 9172 */ "shll_s.w\t\0" |
1093 |
/* 9172 */ "shll_s.w\t\0" |
| 1094 |
/* 9182 */ "min_s.w\t\0" |
1094 |
/* 9182 */ "min_s.w\t\0" |
| 1095 |
/* 9191 */ "dotp_s.w\t\0" |
1095 |
/* 9191 */ "dotp_s.w\t\0" |
| 1096 |
/* 9201 */ "subq_s.w\t\0" |
1096 |
/* 9201 */ "subq_s.w\t\0" |
| 1097 |
/* 9211 */ "addq_s.w\t\0" |
1097 |
/* 9211 */ "addq_s.w\t\0" |
| 1098 |
/* 9221 */ "mulq_s.w\t\0" |
1098 |
/* 9221 */ "mulq_s.w\t\0" |
| 1099 |
/* 9231 */ "absq_s.w\t\0" |
1099 |
/* 9231 */ "absq_s.w\t\0" |
| 1100 |
/* 9241 */ "aver_s.w\t\0" |
1100 |
/* 9241 */ "aver_s.w\t\0" |
| 1101 |
/* 9251 */ "subs_s.w\t\0" |
1101 |
/* 9251 */ "subs_s.w\t\0" |
| 1102 |
/* 9261 */ "adds_s.w\t\0" |
1102 |
/* 9261 */ "adds_s.w\t\0" |
| 1103 |
/* 9271 */ "sat_s.w\t\0" |
1103 |
/* 9271 */ "sat_s.w\t\0" |
| 1104 |
/* 9280 */ "clt_s.w\t\0" |
1104 |
/* 9280 */ "clt_s.w\t\0" |
| 1105 |
/* 9289 */ "ffint_s.w\t\0" |
1105 |
/* 9289 */ "ffint_s.w\t\0" |
| 1106 |
/* 9300 */ "ftint_s.w\t\0" |
1106 |
/* 9300 */ "ftint_s.w\t\0" |
| 1107 |
/* 9311 */ "subsuu_s.w\t\0" |
1107 |
/* 9311 */ "subsuu_s.w\t\0" |
| 1108 |
/* 9323 */ "div_s.w\t\0" |
1108 |
/* 9323 */ "div_s.w\t\0" |
| 1109 |
/* 9332 */ "shllv_s.w\t\0" |
1109 |
/* 9332 */ "shllv_s.w\t\0" |
| 1110 |
/* 9343 */ "max_s.w\t\0" |
1110 |
/* 9343 */ "max_s.w\t\0" |
| 1111 |
/* 9352 */ "copy_s.w\t\0" |
1111 |
/* 9352 */ "copy_s.w\t\0" |
| 1112 |
/* 9362 */ "mulq_rs.w\t\0" |
1112 |
/* 9362 */ "mulq_rs.w\t\0" |
| 1113 |
/* 9373 */ "extr_rs.w\t\0" |
1113 |
/* 9373 */ "extr_rs.w\t\0" |
| 1114 |
/* 9384 */ "extrv_rs.w\t\0" |
1114 |
/* 9384 */ "extrv_rs.w\t\0" |
| 1115 |
/* 9396 */ "fclass.w\t\0" |
1115 |
/* 9396 */ "fclass.w\t\0" |
| 1116 |
/* 9406 */ "splat.w\t\0" |
1116 |
/* 9406 */ "splat.w\t\0" |
| 1117 |
/* 9415 */ "bset.w\t\0" |
1117 |
/* 9415 */ "bset.w\t\0" |
| 1118 |
/* 9423 */ "fclt.w\t\0" |
1118 |
/* 9423 */ "fclt.w\t\0" |
| 1119 |
/* 9431 */ "fslt.w\t\0" |
1119 |
/* 9431 */ "fslt.w\t\0" |
| 1120 |
/* 9439 */ "fcult.w\t\0" |
1120 |
/* 9439 */ "fcult.w\t\0" |
| 1121 |
/* 9448 */ "fsult.w\t\0" |
1121 |
/* 9448 */ "fsult.w\t\0" |
| 1122 |
/* 9457 */ "pcnt.w\t\0" |
1122 |
/* 9457 */ "pcnt.w\t\0" |
| 1123 |
/* 9465 */ "frint.w\t\0" |
1123 |
/* 9465 */ "frint.w\t\0" |
| 1124 |
/* 9474 */ "insert.w\t\0" |
1124 |
/* 9474 */ "insert.w\t\0" |
| 1125 |
/* 9484 */ "fsqrt.w\t\0" |
1125 |
/* 9484 */ "fsqrt.w\t\0" |
| 1126 |
/* 9493 */ "frsqrt.w\t\0" |
1126 |
/* 9493 */ "frsqrt.w\t\0" |
| 1127 |
/* 9503 */ "st.w\t\0" |
1127 |
/* 9503 */ "st.w\t\0" |
| 1128 |
/* 9509 */ "asub_u.w\t\0" |
1128 |
/* 9509 */ "asub_u.w\t\0" |
| 1129 |
/* 9519 */ "hsub_u.w\t\0" |
1129 |
/* 9519 */ "hsub_u.w\t\0" |
| 1130 |
/* 9529 */ "dpsub_u.w\t\0" |
1130 |
/* 9529 */ "dpsub_u.w\t\0" |
| 1131 |
/* 9540 */ "ftrunc_u.w\t\0" |
1131 |
/* 9540 */ "ftrunc_u.w\t\0" |
| 1132 |
/* 9552 */ "hadd_u.w\t\0" |
1132 |
/* 9552 */ "hadd_u.w\t\0" |
| 1133 |
/* 9562 */ "dpadd_u.w\t\0" |
1133 |
/* 9562 */ "dpadd_u.w\t\0" |
| 1134 |
/* 9573 */ "mod_u.w\t\0" |
1134 |
/* 9573 */ "mod_u.w\t\0" |
| 1135 |
/* 9582 */ "cle_u.w\t\0" |
1135 |
/* 9582 */ "cle_u.w\t\0" |
| 1136 |
/* 9591 */ "ave_u.w\t\0" |
1136 |
/* 9591 */ "ave_u.w\t\0" |
| 1137 |
/* 9600 */ "clei_u.w\t\0" |
1137 |
/* 9600 */ "clei_u.w\t\0" |
| 1138 |
/* 9610 */ "mini_u.w\t\0" |
1138 |
/* 9610 */ "mini_u.w\t\0" |
| 1139 |
/* 9620 */ "clti_u.w\t\0" |
1139 |
/* 9620 */ "clti_u.w\t\0" |
| 1140 |
/* 9630 */ "maxi_u.w\t\0" |
1140 |
/* 9630 */ "maxi_u.w\t\0" |
| 1141 |
/* 9640 */ "min_u.w\t\0" |
1141 |
/* 9640 */ "min_u.w\t\0" |
| 1142 |
/* 9649 */ "dotp_u.w\t\0" |
1142 |
/* 9649 */ "dotp_u.w\t\0" |
| 1143 |
/* 9659 */ "aver_u.w\t\0" |
1143 |
/* 9659 */ "aver_u.w\t\0" |
| 1144 |
/* 9669 */ "subs_u.w\t\0" |
1144 |
/* 9669 */ "subs_u.w\t\0" |
| 1145 |
/* 9679 */ "adds_u.w\t\0" |
1145 |
/* 9679 */ "adds_u.w\t\0" |
| 1146 |
/* 9689 */ "subsus_u.w\t\0" |
1146 |
/* 9689 */ "subsus_u.w\t\0" |
| 1147 |
/* 9701 */ "sat_u.w\t\0" |
1147 |
/* 9701 */ "sat_u.w\t\0" |
| 1148 |
/* 9710 */ "clt_u.w\t\0" |
1148 |
/* 9710 */ "clt_u.w\t\0" |
| 1149 |
/* 9719 */ "ffint_u.w\t\0" |
1149 |
/* 9719 */ "ffint_u.w\t\0" |
| 1150 |
/* 9730 */ "ftint_u.w\t\0" |
1150 |
/* 9730 */ "ftint_u.w\t\0" |
| 1151 |
/* 9741 */ "div_u.w\t\0" |
1151 |
/* 9741 */ "div_u.w\t\0" |
| 1152 |
/* 9750 */ "max_u.w\t\0" |
1152 |
/* 9750 */ "max_u.w\t\0" |
| 1153 |
/* 9759 */ "copy_u.w\t\0" |
1153 |
/* 9759 */ "copy_u.w\t\0" |
| 1154 |
/* 9769 */ "msubv.w\t\0" |
1154 |
/* 9769 */ "msubv.w\t\0" |
| 1155 |
/* 9778 */ "maddv.w\t\0" |
1155 |
/* 9778 */ "maddv.w\t\0" |
| 1156 |
/* 9787 */ "pckev.w\t\0" |
1156 |
/* 9787 */ "pckev.w\t\0" |
| 1157 |
/* 9796 */ "ilvev.w\t\0" |
1157 |
/* 9796 */ "ilvev.w\t\0" |
| 1158 |
/* 9805 */ "fdiv.w\t\0" |
1158 |
/* 9805 */ "fdiv.w\t\0" |
| 1159 |
/* 9813 */ "mulv.w\t\0" |
1159 |
/* 9813 */ "mulv.w\t\0" |
| 1160 |
/* 9821 */ "extrv.w\t\0" |
1160 |
/* 9821 */ "extrv.w\t\0" |
| 1161 |
/* 9830 */ "fmax.w\t\0" |
1161 |
/* 9830 */ "fmax.w\t\0" |
| 1162 |
/* 9838 */ "bz.w\t\0" |
1162 |
/* 9838 */ "bz.w\t\0" |
| 1163 |
/* 9844 */ "bnz.w\t\0" |
1163 |
/* 9844 */ "bnz.w\t\0" |
| 1164 |
/* 9851 */ "crc32w\t\0" |
1164 |
/* 9851 */ "crc32w\t\0" |
| 1165 |
/* 9859 */ "crc32cw\t\0" |
1165 |
/* 9859 */ "crc32cw\t\0" |
| 1166 |
/* 9868 */ "ulw\t\0" |
1166 |
/* 9868 */ "ulw\t\0" |
| 1167 |
/* 9873 */ "cvt.ps.pw\t\0" |
1167 |
/* 9873 */ "cvt.ps.pw\t\0" |
| 1168 |
/* 9884 */ "usw\t\0" |
1168 |
/* 9884 */ "usw\t\0" |
| 1169 |
/* 9889 */ "prefx\t\0" |
1169 |
/* 9889 */ "prefx\t\0" |
| 1170 |
/* 9896 */ "lhx\t\0" |
1170 |
/* 9896 */ "lhx\t\0" |
| 1171 |
/* 9901 */ "jalx\t\0" |
1171 |
/* 9901 */ "jalx\t\0" |
| 1172 |
/* 9907 */ "lbux\t\0" |
1172 |
/* 9907 */ "lbux\t\0" |
| 1173 |
/* 9913 */ "lwx\t\0" |
1173 |
/* 9913 */ "lwx\t\0" |
| 1174 |
/* 9918 */ "bgez\t\0" |
1174 |
/* 9918 */ "bgez\t\0" |
| 1175 |
/* 9924 */ "blez\t\0" |
1175 |
/* 9924 */ "blez\t\0" |
| 1176 |
/* 9930 */ "bnez\t\0" |
1176 |
/* 9930 */ "bnez\t\0" |
| 1177 |
/* 9936 */ "selnez\t\0" |
1177 |
/* 9936 */ "selnez\t\0" |
| 1178 |
/* 9944 */ "btnez\t\0" |
1178 |
/* 9944 */ "btnez\t\0" |
| 1179 |
/* 9951 */ "dclz\t\0" |
1179 |
/* 9951 */ "dclz\t\0" |
| 1180 |
/* 9957 */ "beqz\t\0" |
1180 |
/* 9957 */ "beqz\t\0" |
| 1181 |
/* 9963 */ "seleqz\t\0" |
1181 |
/* 9963 */ "seleqz\t\0" |
| 1182 |
/* 9971 */ "bteqz\t\0" |
1182 |
/* 9971 */ "bteqz\t\0" |
| 1183 |
/* 9978 */ "bgtz\t\0" |
1183 |
/* 9978 */ "bgtz\t\0" |
| 1184 |
/* 9984 */ "bltz\t\0" |
1184 |
/* 9984 */ "bltz\t\0" |
| 1185 |
/* 9990 */ "movz\t\0" |
1185 |
/* 9990 */ "movz\t\0" |
| 1186 |
/* 9996 */ "seb\t \0" |
1186 |
/* 9996 */ "seb\t \0" |
| 1187 |
/* 10002 */ "seh\t \0" |
1187 |
/* 10002 */ "seh\t \0" |
| 1188 |
/* 10008 */ "ddivu\t$zero, \0" |
1188 |
/* 10008 */ "ddivu\t$zero, \0" |
| 1189 |
/* 10022 */ "ddiv\t$zero, \0" |
1189 |
/* 10022 */ "ddiv\t$zero, \0" |
| 1190 |
/* 10035 */ "addiu\t$sp, \0" |
1190 |
/* 10035 */ "addiu\t$sp, \0" |
| 1191 |
/* 10047 */ "mftc0 \0" |
1191 |
/* 10047 */ "mftc0 \0" |
| 1192 |
/* 10054 */ "mttc0 \0" |
1192 |
/* 10054 */ "mttc0 \0" |
| 1193 |
/* 10061 */ "mfthc1 \0" |
1193 |
/* 10061 */ "mfthc1 \0" |
| 1194 |
/* 10069 */ "mtthc1 \0" |
1194 |
/* 10069 */ "mtthc1 \0" |
| 1195 |
/* 10077 */ "cftc1 \0" |
1195 |
/* 10077 */ "cftc1 \0" |
| 1196 |
/* 10084 */ "mftc1 \0" |
1196 |
/* 10084 */ "mftc1 \0" |
| 1197 |
/* 10091 */ "cttc1 \0" |
1197 |
/* 10091 */ "cttc1 \0" |
| 1198 |
/* 10098 */ "mttc1 \0" |
1198 |
/* 10098 */ "mttc1 \0" |
| 1199 |
/* 10105 */ "sync \0" |
1199 |
/* 10105 */ "sync \0" |
| 1200 |
/* 10111 */ "ld \0" |
1200 |
/* 10111 */ "ld \0" |
| 1201 |
/* 10115 */ "\t.word \0" |
1201 |
/* 10115 */ "\t.word \0" |
| 1202 |
/* 10123 */ "sd \0" |
1202 |
/* 10123 */ "sd \0" |
| 1203 |
/* 10127 */ "sne \0" |
1203 |
/* 10127 */ "sne \0" |
| 1204 |
/* 10132 */ "mfthi \0" |
1204 |
/* 10132 */ "mfthi \0" |
| 1205 |
/* 10139 */ "mtthi \0" |
1205 |
/* 10139 */ "mtthi \0" |
| 1206 |
/* 10146 */ "mftlo \0" |
1206 |
/* 10146 */ "mftlo \0" |
| 1207 |
/* 10153 */ "mttlo \0" |
1207 |
/* 10153 */ "mttlo \0" |
| 1208 |
/* 10160 */ "mftdsp \0" |
1208 |
/* 10160 */ "mftdsp \0" |
| 1209 |
/* 10168 */ "mttdsp \0" |
1209 |
/* 10168 */ "mttdsp \0" |
| 1210 |
/* 10176 */ "seq \0" |
1210 |
/* 10176 */ "seq \0" |
| 1211 |
/* 10181 */ "mftgpr \0" |
1211 |
/* 10181 */ "mftgpr \0" |
| 1212 |
/* 10189 */ "mttgpr \0" |
1212 |
/* 10189 */ "mttgpr \0" |
| 1213 |
/* 10197 */ "dext \0" |
1213 |
/* 10197 */ "dext \0" |
| 1214 |
/* 10203 */ "mftacx \0" |
1214 |
/* 10203 */ "mftacx \0" |
| 1215 |
/* 10211 */ "mttacx \0" |
1215 |
/* 10211 */ "mttacx \0" |
| 1216 |
/* 10219 */ "bc1nez \0" |
1216 |
/* 10219 */ "bc1nez \0" |
| 1217 |
/* 10227 */ "bc2nez \0" |
1217 |
/* 10227 */ "bc2nez \0" |
| 1218 |
/* 10235 */ "bc1eqz \0" |
1218 |
/* 10235 */ "bc1eqz \0" |
| 1219 |
/* 10243 */ "bc2eqz \0" |
1219 |
/* 10243 */ "bc2eqz \0" |
| 1220 |
/* 10251 */ "# XRay Function Patchable RET.\0" |
1220 |
/* 10251 */ "# XRay Function Patchable RET.\0" |
| 1221 |
/* 10282 */ "c.\0" |
1221 |
/* 10282 */ "c.\0" |
| 1222 |
/* 10285 */ "# XRay Typed Event Log.\0" |
1222 |
/* 10285 */ "# XRay Typed Event Log.\0" |
| 1223 |
/* 10309 */ "# XRay Custom Event Log.\0" |
1223 |
/* 10309 */ "# XRay Custom Event Log.\0" |
| 1224 |
/* 10334 */ "# XRay Function Enter.\0" |
1224 |
/* 10334 */ "# XRay Function Enter.\0" |
| 1225 |
/* 10357 */ "# XRay Tail Call Exit.\0" |
1225 |
/* 10357 */ "# XRay Tail Call Exit.\0" |
| 1226 |
/* 10380 */ "# XRay Function Exit.\0" |
1226 |
/* 10380 */ "# XRay Function Exit.\0" |
| 1227 |
/* 10402 */ "break 0\0" |
1227 |
/* 10402 */ "break 0\0" |
| 1228 |
/* 10410 */ "LIFETIME_END\0" |
1228 |
/* 10410 */ "LIFETIME_END\0" |
| 1229 |
/* 10423 */ "PSEUDO_PROBE\0" |
1229 |
/* 10423 */ "PSEUDO_PROBE\0" |
| 1230 |
/* 10436 */ "BUNDLE\0" |
1230 |
/* 10436 */ "BUNDLE\0" |
| 1231 |
/* 10443 */ "DBG_VALUE\0" |
1231 |
/* 10443 */ "DBG_VALUE\0" |
| 1232 |
/* 10453 */ "DBG_INSTR_REF\0" |
1232 |
/* 10453 */ "DBG_INSTR_REF\0" |
| 1233 |
/* 10467 */ "DBG_PHI\0" |
1233 |
/* 10467 */ "DBG_PHI\0" |
| 1234 |
/* 10475 */ "DBG_LABEL\0" |
1234 |
/* 10475 */ "DBG_LABEL\0" |
| 1235 |
/* 10485 */ "LIFETIME_START\0" |
1235 |
/* 10485 */ "LIFETIME_START\0" |
| 1236 |
/* 10500 */ "DBG_VALUE_LIST\0" |
1236 |
/* 10500 */ "DBG_VALUE_LIST\0" |
| 1237 |
/* 10515 */ "jrc\t$ra\0" |
1237 |
/* 10515 */ "jrc\t$ra\0" |
| 1238 |
/* 10523 */ "jr\t$ra\0" |
1238 |
/* 10523 */ "jr\t$ra\0" |
| 1239 |
/* 10530 */ "ehb\0" |
1239 |
/* 10530 */ "ehb\0" |
| 1240 |
/* 10534 */ "eretnc\0" |
1240 |
/* 10534 */ "eretnc\0" |
| 1241 |
/* 10541 */ "pause\0" |
1241 |
/* 10541 */ "pause\0" |
| 1242 |
/* 10547 */ "tlbinvf\0" |
1242 |
/* 10547 */ "tlbinvf\0" |
| 1243 |
/* 10555 */ "tlbginvf\0" |
1243 |
/* 10555 */ "tlbginvf\0" |
| 1244 |
/* 10564 */ "tlbwi\0" |
1244 |
/* 10564 */ "tlbwi\0" |
| 1245 |
/* 10570 */ "tlbgwi\0" |
1245 |
/* 10570 */ "tlbgwi\0" |
| 1246 |
/* 10577 */ "# FEntry call\0" |
1246 |
/* 10577 */ "# FEntry call\0" |
| 1247 |
/* 10591 */ "foo\0" |
1247 |
/* 10591 */ "foo\0" |
| 1248 |
/* 10595 */ "tlbp\0" |
1248 |
/* 10595 */ "tlbp\0" |
| 1249 |
/* 10600 */ "tlbgp\0" |
1249 |
/* 10600 */ "tlbgp\0" |
| 1250 |
/* 10606 */ "ssnop\0" |
1250 |
/* 10606 */ "ssnop\0" |
| 1251 |
/* 10612 */ "tlbr\0" |
1251 |
/* 10612 */ "tlbr\0" |
| 1252 |
/* 10617 */ "tlbgr\0" |
1252 |
/* 10617 */ "tlbgr\0" |
| 1253 |
/* 10623 */ "tlbwr\0" |
1253 |
/* 10623 */ "tlbwr\0" |
| 1254 |
/* 10629 */ "tlbgwr\0" |
1254 |
/* 10629 */ "tlbgwr\0" |
| 1255 |
/* 10636 */ "deret\0" |
1255 |
/* 10636 */ "deret\0" |
| 1256 |
/* 10642 */ "wait\0" |
1256 |
/* 10642 */ "wait\0" |
| 1257 |
/* 10647 */ "tlbinv\0" |
1257 |
/* 10647 */ "tlbinv\0" |
| 1258 |
/* 10654 */ "tlbginv\0" |
1258 |
/* 10654 */ "tlbginv\0" |
| 1259 |
}; |
1259 |
}; |
| 1260 |
#ifdef __GNUC__ |
1260 |
#ifdef __GNUC__ |
| 1261 |
#pragma GCC diagnostic pop |
1261 |
#pragma GCC diagnostic pop |
| 1262 |
#endif |
1262 |
#endif |
| 1263 |
|
1263 |
|
| 1264 |
static const uint32_t OpInfo0[] = { |
1264 |
static const uint32_t OpInfo0[] = { |
| 1265 |
0U, // PHI |
1265 |
0U, // PHI |
| 1266 |
0U, // INLINEASM |
1266 |
0U, // INLINEASM |
| 1267 |
0U, // INLINEASM_BR |
1267 |
0U, // INLINEASM_BR |
| 1268 |
0U, // CFI_INSTRUCTION |
1268 |
0U, // CFI_INSTRUCTION |
| 1269 |
0U, // EH_LABEL |
1269 |
0U, // EH_LABEL |
| 1270 |
0U, // GC_LABEL |
1270 |
0U, // GC_LABEL |
| 1271 |
0U, // ANNOTATION_LABEL |
1271 |
0U, // ANNOTATION_LABEL |
| 1272 |
0U, // KILL |
1272 |
0U, // KILL |
| 1273 |
0U, // EXTRACT_SUBREG |
1273 |
0U, // EXTRACT_SUBREG |
| 1274 |
0U, // INSERT_SUBREG |
1274 |
0U, // INSERT_SUBREG |
| 1275 |
0U, // IMPLICIT_DEF |
1275 |
0U, // IMPLICIT_DEF |
| 1276 |
0U, // SUBREG_TO_REG |
1276 |
0U, // SUBREG_TO_REG |
| 1277 |
0U, // COPY_TO_REGCLASS |
1277 |
0U, // COPY_TO_REGCLASS |
| 1278 |
10444U, // DBG_VALUE |
1278 |
10444U, // DBG_VALUE |
| 1279 |
10501U, // DBG_VALUE_LIST |
1279 |
10501U, // DBG_VALUE_LIST |
| 1280 |
10454U, // DBG_INSTR_REF |
1280 |
10454U, // DBG_INSTR_REF |
| 1281 |
10468U, // DBG_PHI |
1281 |
10468U, // DBG_PHI |
| 1282 |
10476U, // DBG_LABEL |
1282 |
10476U, // DBG_LABEL |
| 1283 |
0U, // REG_SEQUENCE |
1283 |
0U, // REG_SEQUENCE |
| 1284 |
0U, // COPY |
1284 |
0U, // COPY |
| 1285 |
10437U, // BUNDLE |
1285 |
10437U, // BUNDLE |
| 1286 |
10486U, // LIFETIME_START |
1286 |
10486U, // LIFETIME_START |
| 1287 |
10411U, // LIFETIME_END |
1287 |
10411U, // LIFETIME_END |
| 1288 |
10424U, // PSEUDO_PROBE |
1288 |
10424U, // PSEUDO_PROBE |
| 1289 |
0U, // ARITH_FENCE |
1289 |
0U, // ARITH_FENCE |
| 1290 |
0U, // STACKMAP |
1290 |
0U, // STACKMAP |
| 1291 |
10578U, // FENTRY_CALL |
1291 |
10578U, // FENTRY_CALL |
| 1292 |
0U, // PATCHPOINT |
1292 |
0U, // PATCHPOINT |
| 1293 |
0U, // LOAD_STACK_GUARD |
1293 |
0U, // LOAD_STACK_GUARD |
| 1294 |
0U, // PREALLOCATED_SETUP |
1294 |
0U, // PREALLOCATED_SETUP |
| 1295 |
0U, // PREALLOCATED_ARG |
1295 |
0U, // PREALLOCATED_ARG |
| 1296 |
0U, // STATEPOINT |
1296 |
0U, // STATEPOINT |
| 1297 |
0U, // LOCAL_ESCAPE |
1297 |
0U, // LOCAL_ESCAPE |
| 1298 |
0U, // FAULTING_OP |
1298 |
0U, // FAULTING_OP |
| 1299 |
0U, // PATCHABLE_OP |
1299 |
0U, // PATCHABLE_OP |
| 1300 |
10335U, // PATCHABLE_FUNCTION_ENTER |
1300 |
10335U, // PATCHABLE_FUNCTION_ENTER |
| 1301 |
10252U, // PATCHABLE_RET |
1301 |
10252U, // PATCHABLE_RET |
| 1302 |
10381U, // PATCHABLE_FUNCTION_EXIT |
1302 |
10381U, // PATCHABLE_FUNCTION_EXIT |
| 1303 |
10358U, // PATCHABLE_TAIL_CALL |
1303 |
10358U, // PATCHABLE_TAIL_CALL |
| 1304 |
10310U, // PATCHABLE_EVENT_CALL |
1304 |
10310U, // PATCHABLE_EVENT_CALL |
| 1305 |
10286U, // PATCHABLE_TYPED_EVENT_CALL |
1305 |
10286U, // PATCHABLE_TYPED_EVENT_CALL |
| 1306 |
0U, // ICALL_BRANCH_FUNNEL |
1306 |
0U, // ICALL_BRANCH_FUNNEL |
| 1307 |
0U, // MEMBARRIER |
1307 |
0U, // MEMBARRIER |
| 1308 |
0U, // G_ASSERT_SEXT |
1308 |
0U, // G_ASSERT_SEXT |
| 1309 |
0U, // G_ASSERT_ZEXT |
1309 |
0U, // G_ASSERT_ZEXT |
| 1310 |
0U, // G_ASSERT_ALIGN |
1310 |
0U, // G_ASSERT_ALIGN |
| 1311 |
0U, // G_ADD |
1311 |
0U, // G_ADD |
| 1312 |
0U, // G_SUB |
1312 |
0U, // G_SUB |
| 1313 |
0U, // G_MUL |
1313 |
0U, // G_MUL |
| 1314 |
0U, // G_SDIV |
1314 |
0U, // G_SDIV |
| 1315 |
0U, // G_UDIV |
1315 |
0U, // G_UDIV |
| 1316 |
0U, // G_SREM |
1316 |
0U, // G_SREM |
| 1317 |
0U, // G_UREM |
1317 |
0U, // G_UREM |
| 1318 |
0U, // G_SDIVREM |
1318 |
0U, // G_SDIVREM |
| 1319 |
0U, // G_UDIVREM |
1319 |
0U, // G_UDIVREM |
| 1320 |
0U, // G_AND |
1320 |
0U, // G_AND |
| 1321 |
0U, // G_OR |
1321 |
0U, // G_OR |
| 1322 |
0U, // G_XOR |
1322 |
0U, // G_XOR |
| 1323 |
0U, // G_IMPLICIT_DEF |
1323 |
0U, // G_IMPLICIT_DEF |
| 1324 |
0U, // G_PHI |
1324 |
0U, // G_PHI |
| 1325 |
0U, // G_FRAME_INDEX |
1325 |
0U, // G_FRAME_INDEX |
| 1326 |
0U, // G_GLOBAL_VALUE |
1326 |
0U, // G_GLOBAL_VALUE |
| 1327 |
0U, // G_CONSTANT_POOL |
1327 |
0U, // G_CONSTANT_POOL |
| 1328 |
0U, // G_EXTRACT |
1328 |
0U, // G_EXTRACT |
| 1329 |
0U, // G_UNMERGE_VALUES |
1329 |
0U, // G_UNMERGE_VALUES |
| 1330 |
0U, // G_INSERT |
1330 |
0U, // G_INSERT |
| 1331 |
0U, // G_MERGE_VALUES |
1331 |
0U, // G_MERGE_VALUES |
| 1332 |
0U, // G_BUILD_VECTOR |
1332 |
0U, // G_BUILD_VECTOR |
| 1333 |
0U, // G_BUILD_VECTOR_TRUNC |
1333 |
0U, // G_BUILD_VECTOR_TRUNC |
| 1334 |
0U, // G_CONCAT_VECTORS |
1334 |
0U, // G_CONCAT_VECTORS |
| 1335 |
0U, // G_PTRTOINT |
1335 |
0U, // G_PTRTOINT |
| 1336 |
0U, // G_INTTOPTR |
1336 |
0U, // G_INTTOPTR |
| 1337 |
0U, // G_BITCAST |
1337 |
0U, // G_BITCAST |
| 1338 |
0U, // G_FREEZE |
1338 |
0U, // G_FREEZE |
| 1339 |
0U, // G_CONSTANT_FOLD_BARRIER |
1339 |
0U, // G_CONSTANT_FOLD_BARRIER |
| 1340 |
0U, // G_INTRINSIC_FPTRUNC_ROUND |
1340 |
0U, // G_INTRINSIC_FPTRUNC_ROUND |
| 1341 |
0U, // G_INTRINSIC_TRUNC |
1341 |
0U, // G_INTRINSIC_TRUNC |
| 1342 |
0U, // G_INTRINSIC_ROUND |
1342 |
0U, // G_INTRINSIC_ROUND |
| 1343 |
0U, // G_INTRINSIC_LRINT |
1343 |
0U, // G_INTRINSIC_LRINT |
| 1344 |
0U, // G_INTRINSIC_ROUNDEVEN |
1344 |
0U, // G_INTRINSIC_ROUNDEVEN |
| 1345 |
0U, // G_READCYCLECOUNTER |
1345 |
0U, // G_READCYCLECOUNTER |
| 1346 |
0U, // G_LOAD |
1346 |
0U, // G_LOAD |
| 1347 |
0U, // G_SEXTLOAD |
1347 |
0U, // G_SEXTLOAD |
| 1348 |
0U, // G_ZEXTLOAD |
1348 |
0U, // G_ZEXTLOAD |
| 1349 |
0U, // G_INDEXED_LOAD |
1349 |
0U, // G_INDEXED_LOAD |
| 1350 |
0U, // G_INDEXED_SEXTLOAD |
1350 |
0U, // G_INDEXED_SEXTLOAD |
| 1351 |
0U, // G_INDEXED_ZEXTLOAD |
1351 |
0U, // G_INDEXED_ZEXTLOAD |
| 1352 |
0U, // G_STORE |
1352 |
0U, // G_STORE |
| 1353 |
0U, // G_INDEXED_STORE |
1353 |
0U, // G_INDEXED_STORE |
| 1354 |
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
1354 |
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 1355 |
0U, // G_ATOMIC_CMPXCHG |
1355 |
0U, // G_ATOMIC_CMPXCHG |
| 1356 |
0U, // G_ATOMICRMW_XCHG |
1356 |
0U, // G_ATOMICRMW_XCHG |
| 1357 |
0U, // G_ATOMICRMW_ADD |
1357 |
0U, // G_ATOMICRMW_ADD |
| 1358 |
0U, // G_ATOMICRMW_SUB |
1358 |
0U, // G_ATOMICRMW_SUB |
| 1359 |
0U, // G_ATOMICRMW_AND |
1359 |
0U, // G_ATOMICRMW_AND |
| 1360 |
0U, // G_ATOMICRMW_NAND |
1360 |
0U, // G_ATOMICRMW_NAND |
| 1361 |
0U, // G_ATOMICRMW_OR |
1361 |
0U, // G_ATOMICRMW_OR |
| 1362 |
0U, // G_ATOMICRMW_XOR |
1362 |
0U, // G_ATOMICRMW_XOR |
| 1363 |
0U, // G_ATOMICRMW_MAX |
1363 |
0U, // G_ATOMICRMW_MAX |
| 1364 |
0U, // G_ATOMICRMW_MIN |
1364 |
0U, // G_ATOMICRMW_MIN |
| 1365 |
0U, // G_ATOMICRMW_UMAX |
1365 |
0U, // G_ATOMICRMW_UMAX |
| 1366 |
0U, // G_ATOMICRMW_UMIN |
1366 |
0U, // G_ATOMICRMW_UMIN |
| 1367 |
0U, // G_ATOMICRMW_FADD |
1367 |
0U, // G_ATOMICRMW_FADD |
| 1368 |
0U, // G_ATOMICRMW_FSUB |
1368 |
0U, // G_ATOMICRMW_FSUB |
| 1369 |
0U, // G_ATOMICRMW_FMAX |
1369 |
0U, // G_ATOMICRMW_FMAX |
| 1370 |
0U, // G_ATOMICRMW_FMIN |
1370 |
0U, // G_ATOMICRMW_FMIN |
| 1371 |
0U, // G_ATOMICRMW_UINC_WRAP |
1371 |
0U, // G_ATOMICRMW_UINC_WRAP |
| 1372 |
0U, // G_ATOMICRMW_UDEC_WRAP |
1372 |
0U, // G_ATOMICRMW_UDEC_WRAP |
| 1373 |
0U, // G_FENCE |
1373 |
0U, // G_FENCE |
| 1374 |
0U, // G_BRCOND |
1374 |
0U, // G_BRCOND |
| 1375 |
0U, // G_BRINDIRECT |
1375 |
0U, // G_BRINDIRECT |
| 1376 |
0U, // G_INVOKE_REGION_START |
1376 |
0U, // G_INVOKE_REGION_START |
| 1377 |
0U, // G_INTRINSIC |
1377 |
0U, // G_INTRINSIC |
| 1378 |
0U, // G_INTRINSIC_W_SIDE_EFFECTS |
1378 |
0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 1379 |
0U, // G_ANYEXT |
1379 |
0U, // G_ANYEXT |
| 1380 |
0U, // G_TRUNC |
1380 |
0U, // G_TRUNC |
| 1381 |
0U, // G_CONSTANT |
1381 |
0U, // G_CONSTANT |
| 1382 |
0U, // G_FCONSTANT |
1382 |
0U, // G_FCONSTANT |
| 1383 |
0U, // G_VASTART |
1383 |
0U, // G_VASTART |
| 1384 |
0U, // G_VAARG |
1384 |
0U, // G_VAARG |
| 1385 |
0U, // G_SEXT |
1385 |
0U, // G_SEXT |
| 1386 |
0U, // G_SEXT_INREG |
1386 |
0U, // G_SEXT_INREG |
| 1387 |
0U, // G_ZEXT |
1387 |
0U, // G_ZEXT |
| 1388 |
0U, // G_SHL |
1388 |
0U, // G_SHL |
| 1389 |
0U, // G_LSHR |
1389 |
0U, // G_LSHR |
| 1390 |
0U, // G_ASHR |
1390 |
0U, // G_ASHR |
| 1391 |
0U, // G_FSHL |
1391 |
0U, // G_FSHL |
| 1392 |
0U, // G_FSHR |
1392 |
0U, // G_FSHR |
| 1393 |
0U, // G_ROTR |
1393 |
0U, // G_ROTR |
| 1394 |
0U, // G_ROTL |
1394 |
0U, // G_ROTL |
| 1395 |
0U, // G_ICMP |
1395 |
0U, // G_ICMP |
| 1396 |
0U, // G_FCMP |
1396 |
0U, // G_FCMP |
| 1397 |
0U, // G_SELECT |
1397 |
0U, // G_SELECT |
| 1398 |
0U, // G_UADDO |
1398 |
0U, // G_UADDO |
| 1399 |
0U, // G_UADDE |
1399 |
0U, // G_UADDE |
| 1400 |
0U, // G_USUBO |
1400 |
0U, // G_USUBO |
| 1401 |
0U, // G_USUBE |
1401 |
0U, // G_USUBE |
| 1402 |
0U, // G_SADDO |
1402 |
0U, // G_SADDO |
| 1403 |
0U, // G_SADDE |
1403 |
0U, // G_SADDE |
| 1404 |
0U, // G_SSUBO |
1404 |
0U, // G_SSUBO |
| 1405 |
0U, // G_SSUBE |
1405 |
0U, // G_SSUBE |
| 1406 |
0U, // G_UMULO |
1406 |
0U, // G_UMULO |
| 1407 |
0U, // G_SMULO |
1407 |
0U, // G_SMULO |
| 1408 |
0U, // G_UMULH |
1408 |
0U, // G_UMULH |
| 1409 |
0U, // G_SMULH |
1409 |
0U, // G_SMULH |
| 1410 |
0U, // G_UADDSAT |
1410 |
0U, // G_UADDSAT |
| 1411 |
0U, // G_SADDSAT |
1411 |
0U, // G_SADDSAT |
| 1412 |
0U, // G_USUBSAT |
1412 |
0U, // G_USUBSAT |
| 1413 |
0U, // G_SSUBSAT |
1413 |
0U, // G_SSUBSAT |
| 1414 |
0U, // G_USHLSAT |
1414 |
0U, // G_USHLSAT |
| 1415 |
0U, // G_SSHLSAT |
1415 |
0U, // G_SSHLSAT |
| 1416 |
0U, // G_SMULFIX |
1416 |
0U, // G_SMULFIX |
| 1417 |
0U, // G_UMULFIX |
1417 |
0U, // G_UMULFIX |
| 1418 |
0U, // G_SMULFIXSAT |
1418 |
0U, // G_SMULFIXSAT |
| 1419 |
0U, // G_UMULFIXSAT |
1419 |
0U, // G_UMULFIXSAT |
| 1420 |
0U, // G_SDIVFIX |
1420 |
0U, // G_SDIVFIX |
| 1421 |
0U, // G_UDIVFIX |
1421 |
0U, // G_UDIVFIX |
| 1422 |
0U, // G_SDIVFIXSAT |
1422 |
0U, // G_SDIVFIXSAT |
| 1423 |
0U, // G_UDIVFIXSAT |
1423 |
0U, // G_UDIVFIXSAT |
| 1424 |
0U, // G_FADD |
1424 |
0U, // G_FADD |
| 1425 |
0U, // G_FSUB |
1425 |
0U, // G_FSUB |
| 1426 |
0U, // G_FMUL |
1426 |
0U, // G_FMUL |
| 1427 |
0U, // G_FMA |
1427 |
0U, // G_FMA |
| 1428 |
0U, // G_FMAD |
1428 |
0U, // G_FMAD |
| 1429 |
0U, // G_FDIV |
1429 |
0U, // G_FDIV |
| 1430 |
0U, // G_FREM |
1430 |
0U, // G_FREM |
| 1431 |
0U, // G_FPOW |
1431 |
0U, // G_FPOW |
| 1432 |
0U, // G_FPOWI |
1432 |
0U, // G_FPOWI |
| 1433 |
0U, // G_FEXP |
1433 |
0U, // G_FEXP |
| 1434 |
0U, // G_FEXP2 |
1434 |
0U, // G_FEXP2 |
| 1435 |
0U, // G_FLOG |
1435 |
0U, // G_FLOG |
| 1436 |
0U, // G_FLOG2 |
1436 |
0U, // G_FLOG2 |
| 1437 |
0U, // G_FLOG10 |
1437 |
0U, // G_FLOG10 |
| 1438 |
0U, // G_FLDEXP |
1438 |
0U, // G_FLDEXP |
| 1439 |
0U, // G_FFREXP |
1439 |
0U, // G_FFREXP |
| 1440 |
0U, // G_FNEG |
1440 |
0U, // G_FNEG |
| 1441 |
0U, // G_FPEXT |
1441 |
0U, // G_FPEXT |
| 1442 |
0U, // G_FPTRUNC |
1442 |
0U, // G_FPTRUNC |
| 1443 |
0U, // G_FPTOSI |
1443 |
0U, // G_FPTOSI |
| 1444 |
0U, // G_FPTOUI |
1444 |
0U, // G_FPTOUI |
| 1445 |
0U, // G_SITOFP |
1445 |
0U, // G_SITOFP |
| 1446 |
0U, // G_UITOFP |
1446 |
0U, // G_UITOFP |
| 1447 |
0U, // G_FABS |
1447 |
0U, // G_FABS |
| 1448 |
0U, // G_FCOPYSIGN |
1448 |
0U, // G_FCOPYSIGN |
| 1449 |
0U, // G_IS_FPCLASS |
1449 |
0U, // G_IS_FPCLASS |
| 1450 |
0U, // G_FCANONICALIZE |
1450 |
0U, // G_FCANONICALIZE |
| 1451 |
0U, // G_FMINNUM |
1451 |
0U, // G_FMINNUM |
| 1452 |
0U, // G_FMAXNUM |
1452 |
0U, // G_FMAXNUM |
| 1453 |
0U, // G_FMINNUM_IEEE |
1453 |
0U, // G_FMINNUM_IEEE |
| 1454 |
0U, // G_FMAXNUM_IEEE |
1454 |
0U, // G_FMAXNUM_IEEE |
| 1455 |
0U, // G_FMINIMUM |
1455 |
0U, // G_FMINIMUM |
| 1456 |
0U, // G_FMAXIMUM |
1456 |
0U, // G_FMAXIMUM |
| 1457 |
0U, // G_PTR_ADD |
1457 |
0U, // G_PTR_ADD |
| 1458 |
0U, // G_PTRMASK |
1458 |
0U, // G_PTRMASK |
| 1459 |
0U, // G_SMIN |
1459 |
0U, // G_SMIN |
| 1460 |
0U, // G_SMAX |
1460 |
0U, // G_SMAX |
| 1461 |
0U, // G_UMIN |
1461 |
0U, // G_UMIN |
| 1462 |
0U, // G_UMAX |
1462 |
0U, // G_UMAX |
| 1463 |
0U, // G_ABS |
1463 |
0U, // G_ABS |
| 1464 |
0U, // G_LROUND |
1464 |
0U, // G_LROUND |
| 1465 |
0U, // G_LLROUND |
1465 |
0U, // G_LLROUND |
| 1466 |
0U, // G_BR |
1466 |
0U, // G_BR |
| 1467 |
0U, // G_BRJT |
1467 |
0U, // G_BRJT |
| 1468 |
0U, // G_INSERT_VECTOR_ELT |
1468 |
0U, // G_INSERT_VECTOR_ELT |
| 1469 |
0U, // G_EXTRACT_VECTOR_ELT |
1469 |
0U, // G_EXTRACT_VECTOR_ELT |
| 1470 |
0U, // G_SHUFFLE_VECTOR |
1470 |
0U, // G_SHUFFLE_VECTOR |
| 1471 |
0U, // G_CTTZ |
1471 |
0U, // G_CTTZ |
| 1472 |
0U, // G_CTTZ_ZERO_UNDEF |
1472 |
0U, // G_CTTZ_ZERO_UNDEF |
| 1473 |
0U, // G_CTLZ |
1473 |
0U, // G_CTLZ |
| 1474 |
0U, // G_CTLZ_ZERO_UNDEF |
1474 |
0U, // G_CTLZ_ZERO_UNDEF |
| 1475 |
0U, // G_CTPOP |
1475 |
0U, // G_CTPOP |
| 1476 |
0U, // G_BSWAP |
1476 |
0U, // G_BSWAP |
| 1477 |
0U, // G_BITREVERSE |
1477 |
0U, // G_BITREVERSE |
| 1478 |
0U, // G_FCEIL |
1478 |
0U, // G_FCEIL |
| 1479 |
0U, // G_FCOS |
1479 |
0U, // G_FCOS |
| 1480 |
0U, // G_FSIN |
1480 |
0U, // G_FSIN |
| 1481 |
0U, // G_FSQRT |
1481 |
0U, // G_FSQRT |
| 1482 |
0U, // G_FFLOOR |
1482 |
0U, // G_FFLOOR |
| 1483 |
0U, // G_FRINT |
1483 |
0U, // G_FRINT |
| 1484 |
0U, // G_FNEARBYINT |
1484 |
0U, // G_FNEARBYINT |
| 1485 |
0U, // G_ADDRSPACE_CAST |
1485 |
0U, // G_ADDRSPACE_CAST |
| 1486 |
0U, // G_BLOCK_ADDR |
1486 |
0U, // G_BLOCK_ADDR |
| 1487 |
0U, // G_JUMP_TABLE |
1487 |
0U, // G_JUMP_TABLE |
| 1488 |
0U, // G_DYN_STACKALLOC |
1488 |
0U, // G_DYN_STACKALLOC |
| 1489 |
0U, // G_STRICT_FADD |
1489 |
0U, // G_STRICT_FADD |
| 1490 |
0U, // G_STRICT_FSUB |
1490 |
0U, // G_STRICT_FSUB |
| 1491 |
0U, // G_STRICT_FMUL |
1491 |
0U, // G_STRICT_FMUL |
| 1492 |
0U, // G_STRICT_FDIV |
1492 |
0U, // G_STRICT_FDIV |
| 1493 |
0U, // G_STRICT_FREM |
1493 |
0U, // G_STRICT_FREM |
| 1494 |
0U, // G_STRICT_FMA |
1494 |
0U, // G_STRICT_FMA |
| 1495 |
0U, // G_STRICT_FSQRT |
1495 |
0U, // G_STRICT_FSQRT |
| 1496 |
0U, // G_STRICT_FLDEXP |
1496 |
0U, // G_STRICT_FLDEXP |
| 1497 |
0U, // G_READ_REGISTER |
1497 |
0U, // G_READ_REGISTER |
| 1498 |
0U, // G_WRITE_REGISTER |
1498 |
0U, // G_WRITE_REGISTER |
| 1499 |
0U, // G_MEMCPY |
1499 |
0U, // G_MEMCPY |
| 1500 |
0U, // G_MEMCPY_INLINE |
1500 |
0U, // G_MEMCPY_INLINE |
| 1501 |
0U, // G_MEMMOVE |
1501 |
0U, // G_MEMMOVE |
| 1502 |
0U, // G_MEMSET |
1502 |
0U, // G_MEMSET |
| 1503 |
0U, // G_BZERO |
1503 |
0U, // G_BZERO |
| 1504 |
0U, // G_VECREDUCE_SEQ_FADD |
1504 |
0U, // G_VECREDUCE_SEQ_FADD |
| 1505 |
0U, // G_VECREDUCE_SEQ_FMUL |
1505 |
0U, // G_VECREDUCE_SEQ_FMUL |
| 1506 |
0U, // G_VECREDUCE_FADD |
1506 |
0U, // G_VECREDUCE_FADD |
| 1507 |
0U, // G_VECREDUCE_FMUL |
1507 |
0U, // G_VECREDUCE_FMUL |
| 1508 |
0U, // G_VECREDUCE_FMAX |
1508 |
0U, // G_VECREDUCE_FMAX |
| 1509 |
0U, // G_VECREDUCE_FMIN |
1509 |
0U, // G_VECREDUCE_FMIN |
| 1510 |
0U, // G_VECREDUCE_ADD |
1510 |
0U, // G_VECREDUCE_ADD |
| 1511 |
0U, // G_VECREDUCE_MUL |
1511 |
0U, // G_VECREDUCE_MUL |
| 1512 |
0U, // G_VECREDUCE_AND |
1512 |
0U, // G_VECREDUCE_AND |
| 1513 |
0U, // G_VECREDUCE_OR |
1513 |
0U, // G_VECREDUCE_OR |
| 1514 |
0U, // G_VECREDUCE_XOR |
1514 |
0U, // G_VECREDUCE_XOR |
| 1515 |
0U, // G_VECREDUCE_SMAX |
1515 |
0U, // G_VECREDUCE_SMAX |
| 1516 |
0U, // G_VECREDUCE_SMIN |
1516 |
0U, // G_VECREDUCE_SMIN |
| 1517 |
0U, // G_VECREDUCE_UMAX |
1517 |
0U, // G_VECREDUCE_UMAX |
| 1518 |
0U, // G_VECREDUCE_UMIN |
1518 |
0U, // G_VECREDUCE_UMIN |
| 1519 |
0U, // G_SBFX |
1519 |
0U, // G_SBFX |
| 1520 |
0U, // G_UBFX |
1520 |
0U, // G_UBFX |
| 1521 |
23974U, // ABSMacro |
1521 |
23974U, // ABSMacro |
| 1522 |
0U, // ADJCALLSTACKDOWN |
1522 |
0U, // ADJCALLSTACKDOWN |
| 1523 |
0U, // ADJCALLSTACKUP |
1523 |
0U, // ADJCALLSTACKUP |
| 1524 |
0U, // AND_V_D_PSEUDO |
1524 |
0U, // AND_V_D_PSEUDO |
| 1525 |
0U, // AND_V_H_PSEUDO |
1525 |
0U, // AND_V_H_PSEUDO |
| 1526 |
0U, // AND_V_W_PSEUDO |
1526 |
0U, // AND_V_W_PSEUDO |
| 1527 |
0U, // ATOMIC_CMP_SWAP_I16 |
1527 |
0U, // ATOMIC_CMP_SWAP_I16 |
| 1528 |
0U, // ATOMIC_CMP_SWAP_I16_POSTRA |
1528 |
0U, // ATOMIC_CMP_SWAP_I16_POSTRA |
| 1529 |
0U, // ATOMIC_CMP_SWAP_I32 |
1529 |
0U, // ATOMIC_CMP_SWAP_I32 |
| 1530 |
0U, // ATOMIC_CMP_SWAP_I32_POSTRA |
1530 |
0U, // ATOMIC_CMP_SWAP_I32_POSTRA |
| 1531 |
0U, // ATOMIC_CMP_SWAP_I64 |
1531 |
0U, // ATOMIC_CMP_SWAP_I64 |
| 1532 |
0U, // ATOMIC_CMP_SWAP_I64_POSTRA |
1532 |
0U, // ATOMIC_CMP_SWAP_I64_POSTRA |
| 1533 |
0U, // ATOMIC_CMP_SWAP_I8 |
1533 |
0U, // ATOMIC_CMP_SWAP_I8 |
| 1534 |
0U, // ATOMIC_CMP_SWAP_I8_POSTRA |
1534 |
0U, // ATOMIC_CMP_SWAP_I8_POSTRA |
| 1535 |
0U, // ATOMIC_LOAD_ADD_I16 |
1535 |
0U, // ATOMIC_LOAD_ADD_I16 |
| 1536 |
0U, // ATOMIC_LOAD_ADD_I16_POSTRA |
1536 |
0U, // ATOMIC_LOAD_ADD_I16_POSTRA |
| 1537 |
0U, // ATOMIC_LOAD_ADD_I32 |
1537 |
0U, // ATOMIC_LOAD_ADD_I32 |
| 1538 |
0U, // ATOMIC_LOAD_ADD_I32_POSTRA |
1538 |
0U, // ATOMIC_LOAD_ADD_I32_POSTRA |
| 1539 |
0U, // ATOMIC_LOAD_ADD_I64 |
1539 |
0U, // ATOMIC_LOAD_ADD_I64 |
| 1540 |
0U, // ATOMIC_LOAD_ADD_I64_POSTRA |
1540 |
0U, // ATOMIC_LOAD_ADD_I64_POSTRA |
| 1541 |
0U, // ATOMIC_LOAD_ADD_I8 |
1541 |
0U, // ATOMIC_LOAD_ADD_I8 |
| 1542 |
0U, // ATOMIC_LOAD_ADD_I8_POSTRA |
1542 |
0U, // ATOMIC_LOAD_ADD_I8_POSTRA |
| 1543 |
0U, // ATOMIC_LOAD_AND_I16 |
1543 |
0U, // ATOMIC_LOAD_AND_I16 |
| 1544 |
0U, // ATOMIC_LOAD_AND_I16_POSTRA |
1544 |
0U, // ATOMIC_LOAD_AND_I16_POSTRA |
| 1545 |
0U, // ATOMIC_LOAD_AND_I32 |
1545 |
0U, // ATOMIC_LOAD_AND_I32 |
| 1546 |
0U, // ATOMIC_LOAD_AND_I32_POSTRA |
1546 |
0U, // ATOMIC_LOAD_AND_I32_POSTRA |
| 1547 |
0U, // ATOMIC_LOAD_AND_I64 |
1547 |
0U, // ATOMIC_LOAD_AND_I64 |
| 1548 |
0U, // ATOMIC_LOAD_AND_I64_POSTRA |
1548 |
0U, // ATOMIC_LOAD_AND_I64_POSTRA |
| 1549 |
0U, // ATOMIC_LOAD_AND_I8 |
1549 |
0U, // ATOMIC_LOAD_AND_I8 |
| 1550 |
0U, // ATOMIC_LOAD_AND_I8_POSTRA |
1550 |
0U, // ATOMIC_LOAD_AND_I8_POSTRA |
| 1551 |
0U, // ATOMIC_LOAD_MAX_I16 |
1551 |
0U, // ATOMIC_LOAD_MAX_I16 |
| 1552 |
0U, // ATOMIC_LOAD_MAX_I16_POSTRA |
1552 |
0U, // ATOMIC_LOAD_MAX_I16_POSTRA |
| 1553 |
0U, // ATOMIC_LOAD_MAX_I32 |
1553 |
0U, // ATOMIC_LOAD_MAX_I32 |
| 1554 |
0U, // ATOMIC_LOAD_MAX_I32_POSTRA |
1554 |
0U, // ATOMIC_LOAD_MAX_I32_POSTRA |
| 1555 |
0U, // ATOMIC_LOAD_MAX_I64 |
1555 |
0U, // ATOMIC_LOAD_MAX_I64 |
| 1556 |
0U, // ATOMIC_LOAD_MAX_I64_POSTRA |
1556 |
0U, // ATOMIC_LOAD_MAX_I64_POSTRA |
| 1557 |
0U, // ATOMIC_LOAD_MAX_I8 |
1557 |
0U, // ATOMIC_LOAD_MAX_I8 |
| 1558 |
0U, // ATOMIC_LOAD_MAX_I8_POSTRA |
1558 |
0U, // ATOMIC_LOAD_MAX_I8_POSTRA |
| 1559 |
0U, // ATOMIC_LOAD_MIN_I16 |
1559 |
0U, // ATOMIC_LOAD_MIN_I16 |
| 1560 |
0U, // ATOMIC_LOAD_MIN_I16_POSTRA |
1560 |
0U, // ATOMIC_LOAD_MIN_I16_POSTRA |
| 1561 |
0U, // ATOMIC_LOAD_MIN_I32 |
1561 |
0U, // ATOMIC_LOAD_MIN_I32 |
| 1562 |
0U, // ATOMIC_LOAD_MIN_I32_POSTRA |
1562 |
0U, // ATOMIC_LOAD_MIN_I32_POSTRA |
| 1563 |
0U, // ATOMIC_LOAD_MIN_I64 |
1563 |
0U, // ATOMIC_LOAD_MIN_I64 |
| 1564 |
0U, // ATOMIC_LOAD_MIN_I64_POSTRA |
1564 |
0U, // ATOMIC_LOAD_MIN_I64_POSTRA |
| 1565 |
0U, // ATOMIC_LOAD_MIN_I8 |
1565 |
0U, // ATOMIC_LOAD_MIN_I8 |
| 1566 |
0U, // ATOMIC_LOAD_MIN_I8_POSTRA |
1566 |
0U, // ATOMIC_LOAD_MIN_I8_POSTRA |
| 1567 |
0U, // ATOMIC_LOAD_NAND_I16 |
1567 |
0U, // ATOMIC_LOAD_NAND_I16 |
| 1568 |
0U, // ATOMIC_LOAD_NAND_I16_POSTRA |
1568 |
0U, // ATOMIC_LOAD_NAND_I16_POSTRA |
| 1569 |
0U, // ATOMIC_LOAD_NAND_I32 |
1569 |
0U, // ATOMIC_LOAD_NAND_I32 |
| 1570 |
0U, // ATOMIC_LOAD_NAND_I32_POSTRA |
1570 |
0U, // ATOMIC_LOAD_NAND_I32_POSTRA |
| 1571 |
0U, // ATOMIC_LOAD_NAND_I64 |
1571 |
0U, // ATOMIC_LOAD_NAND_I64 |
| 1572 |
0U, // ATOMIC_LOAD_NAND_I64_POSTRA |
1572 |
0U, // ATOMIC_LOAD_NAND_I64_POSTRA |
| 1573 |
0U, // ATOMIC_LOAD_NAND_I8 |
1573 |
0U, // ATOMIC_LOAD_NAND_I8 |
| 1574 |
0U, // ATOMIC_LOAD_NAND_I8_POSTRA |
1574 |
0U, // ATOMIC_LOAD_NAND_I8_POSTRA |
| 1575 |
0U, // ATOMIC_LOAD_OR_I16 |
1575 |
0U, // ATOMIC_LOAD_OR_I16 |
| 1576 |
0U, // ATOMIC_LOAD_OR_I16_POSTRA |
1576 |
0U, // ATOMIC_LOAD_OR_I16_POSTRA |
| 1577 |
0U, // ATOMIC_LOAD_OR_I32 |
1577 |
0U, // ATOMIC_LOAD_OR_I32 |
| 1578 |
0U, // ATOMIC_LOAD_OR_I32_POSTRA |
1578 |
0U, // ATOMIC_LOAD_OR_I32_POSTRA |
| 1579 |
0U, // ATOMIC_LOAD_OR_I64 |
1579 |
0U, // ATOMIC_LOAD_OR_I64 |
| 1580 |
0U, // ATOMIC_LOAD_OR_I64_POSTRA |
1580 |
0U, // ATOMIC_LOAD_OR_I64_POSTRA |
| 1581 |
0U, // ATOMIC_LOAD_OR_I8 |
1581 |
0U, // ATOMIC_LOAD_OR_I8 |
| 1582 |
0U, // ATOMIC_LOAD_OR_I8_POSTRA |
1582 |
0U, // ATOMIC_LOAD_OR_I8_POSTRA |
| 1583 |
0U, // ATOMIC_LOAD_SUB_I16 |
1583 |
0U, // ATOMIC_LOAD_SUB_I16 |
| 1584 |
0U, // ATOMIC_LOAD_SUB_I16_POSTRA |
1584 |
0U, // ATOMIC_LOAD_SUB_I16_POSTRA |
| 1585 |
0U, // ATOMIC_LOAD_SUB_I32 |
1585 |
0U, // ATOMIC_LOAD_SUB_I32 |
| 1586 |
0U, // ATOMIC_LOAD_SUB_I32_POSTRA |
1586 |
0U, // ATOMIC_LOAD_SUB_I32_POSTRA |
| 1587 |
0U, // ATOMIC_LOAD_SUB_I64 |
1587 |
0U, // ATOMIC_LOAD_SUB_I64 |
| 1588 |
0U, // ATOMIC_LOAD_SUB_I64_POSTRA |
1588 |
0U, // ATOMIC_LOAD_SUB_I64_POSTRA |
| 1589 |
0U, // ATOMIC_LOAD_SUB_I8 |
1589 |
0U, // ATOMIC_LOAD_SUB_I8 |
| 1590 |
0U, // ATOMIC_LOAD_SUB_I8_POSTRA |
1590 |
0U, // ATOMIC_LOAD_SUB_I8_POSTRA |
| 1591 |
0U, // ATOMIC_LOAD_UMAX_I16 |
1591 |
0U, // ATOMIC_LOAD_UMAX_I16 |
| 1592 |
0U, // ATOMIC_LOAD_UMAX_I16_POSTRA |
1592 |
0U, // ATOMIC_LOAD_UMAX_I16_POSTRA |
| 1593 |
0U, // ATOMIC_LOAD_UMAX_I32 |
1593 |
0U, // ATOMIC_LOAD_UMAX_I32 |
| 1594 |
0U, // ATOMIC_LOAD_UMAX_I32_POSTRA |
1594 |
0U, // ATOMIC_LOAD_UMAX_I32_POSTRA |
| 1595 |
0U, // ATOMIC_LOAD_UMAX_I64 |
1595 |
0U, // ATOMIC_LOAD_UMAX_I64 |
| 1596 |
0U, // ATOMIC_LOAD_UMAX_I64_POSTRA |
1596 |
0U, // ATOMIC_LOAD_UMAX_I64_POSTRA |
| 1597 |
0U, // ATOMIC_LOAD_UMAX_I8 |
1597 |
0U, // ATOMIC_LOAD_UMAX_I8 |
| 1598 |
0U, // ATOMIC_LOAD_UMAX_I8_POSTRA |
1598 |
0U, // ATOMIC_LOAD_UMAX_I8_POSTRA |
| 1599 |
0U, // ATOMIC_LOAD_UMIN_I16 |
1599 |
0U, // ATOMIC_LOAD_UMIN_I16 |
| 1600 |
0U, // ATOMIC_LOAD_UMIN_I16_POSTRA |
1600 |
0U, // ATOMIC_LOAD_UMIN_I16_POSTRA |
| 1601 |
0U, // ATOMIC_LOAD_UMIN_I32 |
1601 |
0U, // ATOMIC_LOAD_UMIN_I32 |
| 1602 |
0U, // ATOMIC_LOAD_UMIN_I32_POSTRA |
1602 |
0U, // ATOMIC_LOAD_UMIN_I32_POSTRA |
| 1603 |
0U, // ATOMIC_LOAD_UMIN_I64 |
1603 |
0U, // ATOMIC_LOAD_UMIN_I64 |
| 1604 |
0U, // ATOMIC_LOAD_UMIN_I64_POSTRA |
1604 |
0U, // ATOMIC_LOAD_UMIN_I64_POSTRA |
| 1605 |
0U, // ATOMIC_LOAD_UMIN_I8 |
1605 |
0U, // ATOMIC_LOAD_UMIN_I8 |
| 1606 |
0U, // ATOMIC_LOAD_UMIN_I8_POSTRA |
1606 |
0U, // ATOMIC_LOAD_UMIN_I8_POSTRA |
| 1607 |
0U, // ATOMIC_LOAD_XOR_I16 |
1607 |
0U, // ATOMIC_LOAD_XOR_I16 |
| 1608 |
0U, // ATOMIC_LOAD_XOR_I16_POSTRA |
1608 |
0U, // ATOMIC_LOAD_XOR_I16_POSTRA |
| 1609 |
0U, // ATOMIC_LOAD_XOR_I32 |
1609 |
0U, // ATOMIC_LOAD_XOR_I32 |
| 1610 |
0U, // ATOMIC_LOAD_XOR_I32_POSTRA |
1610 |
0U, // ATOMIC_LOAD_XOR_I32_POSTRA |
| 1611 |
0U, // ATOMIC_LOAD_XOR_I64 |
1611 |
0U, // ATOMIC_LOAD_XOR_I64 |
| 1612 |
0U, // ATOMIC_LOAD_XOR_I64_POSTRA |
1612 |
0U, // ATOMIC_LOAD_XOR_I64_POSTRA |
| 1613 |
0U, // ATOMIC_LOAD_XOR_I8 |
1613 |
0U, // ATOMIC_LOAD_XOR_I8 |
| 1614 |
0U, // ATOMIC_LOAD_XOR_I8_POSTRA |
1614 |
0U, // ATOMIC_LOAD_XOR_I8_POSTRA |
| 1615 |
0U, // ATOMIC_SWAP_I16 |
1615 |
0U, // ATOMIC_SWAP_I16 |
| 1616 |
0U, // ATOMIC_SWAP_I16_POSTRA |
1616 |
0U, // ATOMIC_SWAP_I16_POSTRA |
| 1617 |
0U, // ATOMIC_SWAP_I32 |
1617 |
0U, // ATOMIC_SWAP_I32 |
| 1618 |
0U, // ATOMIC_SWAP_I32_POSTRA |
1618 |
0U, // ATOMIC_SWAP_I32_POSTRA |
| 1619 |
0U, // ATOMIC_SWAP_I64 |
1619 |
0U, // ATOMIC_SWAP_I64 |
| 1620 |
0U, // ATOMIC_SWAP_I64_POSTRA |
1620 |
0U, // ATOMIC_SWAP_I64_POSTRA |
| 1621 |
0U, // ATOMIC_SWAP_I8 |
1621 |
0U, // ATOMIC_SWAP_I8 |
| 1622 |
0U, // ATOMIC_SWAP_I8_POSTRA |
1622 |
0U, // ATOMIC_SWAP_I8_POSTRA |
| 1623 |
0U, // B |
1623 |
0U, // B |
| 1624 |
0U, // BAL_BR |
1624 |
0U, // BAL_BR |
| 1625 |
0U, // BAL_BR_MM |
1625 |
0U, // BAL_BR_MM |
| 1626 |
536893669U, // BEQLImmMacro |
1626 |
536893669U, // BEQLImmMacro |
| 1627 |
536891521U, // BGE |
1627 |
536891521U, // BGE |
| 1628 |
536891521U, // BGEImmMacro |
1628 |
536891521U, // BGEImmMacro |
| 1629 |
536893530U, // BGEL |
1629 |
536893530U, // BGEL |
| 1630 |
536893530U, // BGELImmMacro |
1630 |
536893530U, // BGELImmMacro |
| 1631 |
536895156U, // BGEU |
1631 |
536895156U, // BGEU |
| 1632 |
536895156U, // BGEUImmMacro |
1632 |
536895156U, // BGEUImmMacro |
| 1633 |
536893700U, // BGEUL |
1633 |
536893700U, // BGEUL |
| 1634 |
536893700U, // BGEULImmMacro |
1634 |
536893700U, // BGEULImmMacro |
| 1635 |
536895037U, // BGT |
1635 |
536895037U, // BGT |
| 1636 |
536895037U, // BGTImmMacro |
1636 |
536895037U, // BGTImmMacro |
| 1637 |
536893688U, // BGTL |
1637 |
536893688U, // BGTL |
| 1638 |
536893688U, // BGTLImmMacro |
1638 |
536893688U, // BGTLImmMacro |
| 1639 |
536895282U, // BGTU |
1639 |
536895282U, // BGTU |
| 1640 |
536895282U, // BGTUImmMacro |
1640 |
536895282U, // BGTUImmMacro |
| 1641 |
536893720U, // BGTUL |
1641 |
536893720U, // BGTUL |
| 1642 |
536893720U, // BGTULImmMacro |
1642 |
536893720U, // BGTULImmMacro |
| 1643 |
536891561U, // BLE |
1643 |
536891561U, // BLE |
| 1644 |
536891561U, // BLEImmMacro |
1644 |
536891561U, // BLEImmMacro |
| 1645 |
536893536U, // BLEL |
1645 |
536893536U, // BLEL |
| 1646 |
536893536U, // BLELImmMacro |
1646 |
536893536U, // BLELImmMacro |
| 1647 |
536895174U, // BLEU |
1647 |
536895174U, // BLEU |
| 1648 |
536895174U, // BLEUImmMacro |
1648 |
536895174U, // BLEUImmMacro |
| 1649 |
536893707U, // BLEUL |
1649 |
536893707U, // BLEUL |
| 1650 |
536893707U, // BLEULImmMacro |
1650 |
536893707U, // BLEULImmMacro |
| 1651 |
536895053U, // BLT |
1651 |
536895053U, // BLT |
| 1652 |
536895053U, // BLTImmMacro |
1652 |
536895053U, // BLTImmMacro |
| 1653 |
536893694U, // BLTL |
1653 |
536893694U, // BLTL |
| 1654 |
536893694U, // BLTLImmMacro |
1654 |
536893694U, // BLTLImmMacro |
| 1655 |
536895294U, // BLTU |
1655 |
536895294U, // BLTU |
| 1656 |
536895294U, // BLTUImmMacro |
1656 |
536895294U, // BLTUImmMacro |
| 1657 |
536893727U, // BLTUL |
1657 |
536893727U, // BLTUL |
| 1658 |
536893727U, // BLTULImmMacro |
1658 |
536893727U, // BLTULImmMacro |
| 1659 |
536893542U, // BNELImmMacro |
1659 |
536893542U, // BNELImmMacro |
| 1660 |
0U, // BPOSGE32_PSEUDO |
1660 |
0U, // BPOSGE32_PSEUDO |
| 1661 |
0U, // BSEL_D_PSEUDO |
1661 |
0U, // BSEL_D_PSEUDO |
| 1662 |
0U, // BSEL_FD_PSEUDO |
1662 |
0U, // BSEL_FD_PSEUDO |
| 1663 |
0U, // BSEL_FW_PSEUDO |
1663 |
0U, // BSEL_FW_PSEUDO |
| 1664 |
0U, // BSEL_H_PSEUDO |
1664 |
0U, // BSEL_H_PSEUDO |
| 1665 |
0U, // BSEL_W_PSEUDO |
1665 |
0U, // BSEL_W_PSEUDO |
| 1666 |
0U, // B_MM |
1666 |
0U, // B_MM |
| 1667 |
557807U, // B_MMR6_Pseudo |
1667 |
557807U, // B_MMR6_Pseudo |
| 1668 |
557807U, // B_MM_Pseudo |
1668 |
557807U, // B_MM_Pseudo |
| 1669 |
536894020U, // BeqImm |
1669 |
536894020U, // BeqImm |
| 1670 |
536891588U, // BneImm |
1670 |
536891588U, // BneImm |
| 1671 |
1073764808U, // BteqzT8CmpX16 |
1671 |
1073764808U, // BteqzT8CmpX16 |
| 1672 |
1073764241U, // BteqzT8CmpiX16 |
1672 |
1073764241U, // BteqzT8CmpiX16 |
| 1673 |
1073765970U, // BteqzT8SltX16 |
1673 |
1073765970U, // BteqzT8SltX16 |
| 1674 |
1073764271U, // BteqzT8SltiX16 |
1674 |
1073764271U, // BteqzT8SltiX16 |
| 1675 |
1073766126U, // BteqzT8SltiuX16 |
1675 |
1073766126U, // BteqzT8SltiuX16 |
| 1676 |
1073766212U, // BteqzT8SltuX16 |
1676 |
1073766212U, // BteqzT8SltuX16 |
| 1677 |
1610635720U, // BtnezT8CmpX16 |
1677 |
1610635720U, // BtnezT8CmpX16 |
| 1678 |
1610635153U, // BtnezT8CmpiX16 |
1678 |
1610635153U, // BtnezT8CmpiX16 |
| 1679 |
1610636882U, // BtnezT8SltX16 |
1679 |
1610636882U, // BtnezT8SltX16 |
| 1680 |
1610635183U, // BtnezT8SltiX16 |
1680 |
1610635183U, // BtnezT8SltiX16 |
| 1681 |
1610637038U, // BtnezT8SltiuX16 |
1681 |
1610637038U, // BtnezT8SltiuX16 |
| 1682 |
1610637124U, // BtnezT8SltuX16 |
1682 |
1610637124U, // BtnezT8SltuX16 |
| 1683 |
0U, // BuildPairF64 |
1683 |
0U, // BuildPairF64 |
| 1684 |
0U, // BuildPairF64_64 |
1684 |
0U, // BuildPairF64_64 |
| 1685 |
26462U, // CFTC1 |
1685 |
26462U, // CFTC1 |
| 1686 |
10592U, // CONSTPOOL_ENTRY |
1686 |
10592U, // CONSTPOOL_ENTRY |
| 1687 |
0U, // COPY_FD_PSEUDO |
1687 |
0U, // COPY_FD_PSEUDO |
| 1688 |
0U, // COPY_FW_PSEUDO |
1688 |
0U, // COPY_FW_PSEUDO |
| 1689 |
17885036U, // CTTC1 |
1689 |
17885036U, // CTTC1 |
| 1690 |
550788U, // Constant32 |
1690 |
550788U, // Constant32 |
| 1691 |
536893714U, // DMULImmMacro |
1691 |
536893714U, // DMULImmMacro |
| 1692 |
536893714U, // DMULMacro |
1692 |
536893714U, // DMULMacro |
| 1693 |
536893849U, // DMULOMacro |
1693 |
536893849U, // DMULOMacro |
| 1694 |
536895257U, // DMULOUMacro |
1694 |
536895257U, // DMULOUMacro |
| 1695 |
536893653U, // DROL |
1695 |
536893653U, // DROL |
| 1696 |
536893653U, // DROLImm |
1696 |
536893653U, // DROLImm |
| 1697 |
536894187U, // DROR |
1697 |
536894187U, // DROR |
| 1698 |
536894187U, // DRORImm |
1698 |
536894187U, // DRORImm |
| 1699 |
536895419U, // DSDivIMacro |
1699 |
536895419U, // DSDivIMacro |
| 1700 |
536895419U, // DSDivMacro |
1700 |
536895419U, // DSDivMacro |
| 1701 |
536893772U, // DSRemIMacro |
1701 |
536893772U, // DSRemIMacro |
| 1702 |
536893772U, // DSRemMacro |
1702 |
536893772U, // DSRemMacro |
| 1703 |
536895327U, // DUDivIMacro |
1703 |
536895327U, // DUDivIMacro |
| 1704 |
536895327U, // DUDivMacro |
1704 |
536895327U, // DUDivMacro |
| 1705 |
536895250U, // DURemIMacro |
1705 |
536895250U, // DURemIMacro |
| 1706 |
536895250U, // DURemMacro |
1706 |
536895250U, // DURemMacro |
| 1707 |
0U, // ERet |
1707 |
0U, // ERet |
| 1708 |
0U, // ExtractElementF64 |
1708 |
0U, // ExtractElementF64 |
| 1709 |
0U, // ExtractElementF64_64 |
1709 |
0U, // ExtractElementF64_64 |
| 1710 |
0U, // FABS_D |
1710 |
0U, // FABS_D |
| 1711 |
0U, // FABS_W |
1711 |
0U, // FABS_W |
| 1712 |
0U, // FEXP2_D_1_PSEUDO |
1712 |
0U, // FEXP2_D_1_PSEUDO |
| 1713 |
0U, // FEXP2_W_1_PSEUDO |
1713 |
0U, // FEXP2_W_1_PSEUDO |
| 1714 |
0U, // FILL_FD_PSEUDO |
1714 |
0U, // FILL_FD_PSEUDO |
| 1715 |
0U, // FILL_FW_PSEUDO |
1715 |
0U, // FILL_FW_PSEUDO |
| 1716 |
2181060488U, // GotPrologue16 |
1716 |
2181060488U, // GotPrologue16 |
| 1717 |
0U, // INSERT_B_VIDX64_PSEUDO |
1717 |
0U, // INSERT_B_VIDX64_PSEUDO |
| 1718 |
0U, // INSERT_B_VIDX_PSEUDO |
1718 |
0U, // INSERT_B_VIDX_PSEUDO |
| 1719 |
0U, // INSERT_D_VIDX64_PSEUDO |
1719 |
0U, // INSERT_D_VIDX64_PSEUDO |
| 1720 |
0U, // INSERT_D_VIDX_PSEUDO |
1720 |
0U, // INSERT_D_VIDX_PSEUDO |
| 1721 |
0U, // INSERT_FD_PSEUDO |
1721 |
0U, // INSERT_FD_PSEUDO |
| 1722 |
0U, // INSERT_FD_VIDX64_PSEUDO |
1722 |
0U, // INSERT_FD_VIDX64_PSEUDO |
| 1723 |
0U, // INSERT_FD_VIDX_PSEUDO |
1723 |
0U, // INSERT_FD_VIDX_PSEUDO |
| 1724 |
0U, // INSERT_FW_PSEUDO |
1724 |
0U, // INSERT_FW_PSEUDO |
| 1725 |
0U, // INSERT_FW_VIDX64_PSEUDO |
1725 |
0U, // INSERT_FW_VIDX64_PSEUDO |
| 1726 |
0U, // INSERT_FW_VIDX_PSEUDO |
1726 |
0U, // INSERT_FW_VIDX_PSEUDO |
| 1727 |
0U, // INSERT_H_VIDX64_PSEUDO |
1727 |
0U, // INSERT_H_VIDX64_PSEUDO |
| 1728 |
0U, // INSERT_H_VIDX_PSEUDO |
1728 |
0U, // INSERT_H_VIDX_PSEUDO |
| 1729 |
0U, // INSERT_W_VIDX64_PSEUDO |
1729 |
0U, // INSERT_W_VIDX64_PSEUDO |
| 1730 |
0U, // INSERT_W_VIDX_PSEUDO |
1730 |
0U, // INSERT_W_VIDX_PSEUDO |
| 1731 |
0U, // JALR64Pseudo |
1731 |
0U, // JALR64Pseudo |
| 1732 |
0U, // JALRHB64Pseudo |
1732 |
0U, // JALRHB64Pseudo |
| 1733 |
0U, // JALRHBPseudo |
1733 |
0U, // JALRHBPseudo |
| 1734 |
0U, // JALRPseudo |
1734 |
0U, // JALRPseudo |
| 1735 |
0U, // JAL_MMR6 |
1735 |
0U, // JAL_MMR6 |
| 1736 |
546804U, // JalOneReg |
1736 |
546804U, // JalOneReg |
| 1737 |
22516U, // JalTwoReg |
1737 |
22516U, // JalTwoReg |
| 1738 |
50358144U, // LDMacro |
1738 |
50358144U, // LDMacro |
| 1739 |
0U, // LDR_D |
1739 |
0U, // LDR_D |
| 1740 |
0U, // LDR_W |
1740 |
0U, // LDR_W |
| 1741 |
0U, // LD_F16 |
1741 |
0U, // LD_F16 |
| 1742 |
50348038U, // LOAD_ACC128 |
1742 |
50348038U, // LOAD_ACC128 |
| 1743 |
50348038U, // LOAD_ACC64 |
1743 |
50348038U, // LOAD_ACC64 |
| 1744 |
50348038U, // LOAD_ACC64DSP |
1744 |
50348038U, // LOAD_ACC64DSP |
| 1745 |
50354654U, // LOAD_CCOND_DSP |
1745 |
50354654U, // LOAD_CCOND_DSP |
| 1746 |
0U, // LONG_BRANCH_ADDiu |
1746 |
0U, // LONG_BRANCH_ADDiu |
| 1747 |
0U, // LONG_BRANCH_ADDiu2Op |
1747 |
0U, // LONG_BRANCH_ADDiu2Op |
| 1748 |
0U, // LONG_BRANCH_DADDiu |
1748 |
0U, // LONG_BRANCH_DADDiu |
| 1749 |
0U, // LONG_BRANCH_DADDiu2Op |
1749 |
0U, // LONG_BRANCH_DADDiu2Op |
| 1750 |
0U, // LONG_BRANCH_LUi |
1750 |
0U, // LONG_BRANCH_LUi |
| 1751 |
0U, // LONG_BRANCH_LUi2Op |
1751 |
0U, // LONG_BRANCH_LUi2Op |
| 1752 |
0U, // LONG_BRANCH_LUi2Op_64 |
1752 |
0U, // LONG_BRANCH_LUi2Op_64 |
| 1753 |
72032U, // LWM_MM |
1753 |
72032U, // LWM_MM |
| 1754 |
17042U, // LoadAddrImm32 |
1754 |
17042U, // LoadAddrImm32 |
| 1755 |
17063U, // LoadAddrImm64 |
1755 |
17063U, // LoadAddrImm64 |
| 1756 |
50348690U, // LoadAddrReg32 |
1756 |
50348690U, // LoadAddrReg32 |
| 1757 |
50348711U, // LoadAddrReg64 |
1757 |
50348711U, // LoadAddrReg64 |
| 1758 |
22408U, // LoadImm32 |
1758 |
22408U, // LoadImm32 |
| 1759 |
22412U, // LoadImm64 |
1759 |
22412U, // LoadImm64 |
| 1760 |
19107U, // LoadImmDoubleFGR |
1760 |
19107U, // LoadImmDoubleFGR |
| 1761 |
19107U, // LoadImmDoubleFGR_32 |
1761 |
19107U, // LoadImmDoubleFGR_32 |
| 1762 |
19107U, // LoadImmDoubleGPR |
1762 |
19107U, // LoadImmDoubleGPR |
| 1763 |
23539U, // LoadImmSingleFGR |
1763 |
23539U, // LoadImmSingleFGR |
| 1764 |
23539U, // LoadImmSingleGPR |
1764 |
23539U, // LoadImmSingleGPR |
| 1765 |
1599118U, // LwConstant32 |
1765 |
1599118U, // LwConstant32 |
| 1766 |
26588U, // MFTACX |
1766 |
26588U, // MFTACX |
| 1767 |
536897344U, // MFTC0 |
1767 |
536897344U, // MFTC0 |
| 1768 |
26469U, // MFTC1 |
1768 |
26469U, // MFTC1 |
| 1769 |
550833U, // MFTDSP |
1769 |
550833U, // MFTDSP |
| 1770 |
26566U, // MFTGPR |
1770 |
26566U, // MFTGPR |
| 1771 |
26446U, // MFTHC1 |
1771 |
26446U, // MFTHC1 |
| 1772 |
26517U, // MFTHI |
1772 |
26517U, // MFTHI |
| 1773 |
26531U, // MFTLO |
1773 |
26531U, // MFTLO |
| 1774 |
0U, // MIPSeh_return32 |
1774 |
0U, // MIPSeh_return32 |
| 1775 |
0U, // MIPSeh_return64 |
1775 |
0U, // MIPSeh_return64 |
| 1776 |
0U, // MSA_FP_EXTEND_D_PSEUDO |
1776 |
0U, // MSA_FP_EXTEND_D_PSEUDO |
| 1777 |
0U, // MSA_FP_EXTEND_W_PSEUDO |
1777 |
0U, // MSA_FP_EXTEND_W_PSEUDO |
| 1778 |
0U, // MSA_FP_ROUND_D_PSEUDO |
1778 |
0U, // MSA_FP_ROUND_D_PSEUDO |
| 1779 |
0U, // MSA_FP_ROUND_W_PSEUDO |
1779 |
0U, // MSA_FP_ROUND_W_PSEUDO |
| 1780 |
17885156U, // MTTACX |
1780 |
17885156U, // MTTACX |
| 1781 |
2752571207U, // MTTC0 |
1781 |
2752571207U, // MTTC0 |
| 1782 |
17885043U, // MTTC1 |
1782 |
17885043U, // MTTC1 |
| 1783 |
550841U, // MTTDSP |
1783 |
550841U, // MTTDSP |
| 1784 |
17885134U, // MTTGPR |
1784 |
17885134U, // MTTGPR |
| 1785 |
17885014U, // MTTHC1 |
1785 |
17885014U, // MTTHC1 |
| 1786 |
17885084U, // MTTHI |
1786 |
17885084U, // MTTHI |
| 1787 |
17885098U, // MTTLO |
1787 |
17885098U, // MTTLO |
| 1788 |
536893715U, // MULImmMacro |
1788 |
536893715U, // MULImmMacro |
| 1789 |
536893850U, // MULOMacro |
1789 |
536893850U, // MULOMacro |
| 1790 |
536895258U, // MULOUMacro |
1790 |
536895258U, // MULOUMacro |
| 1791 |
24157U, // MultRxRy16 |
1791 |
24157U, // MultRxRy16 |
| 1792 |
86040157U, // MultRxRyRz16 |
1792 |
86040157U, // MultRxRyRz16 |
| 1793 |
24401U, // MultuRxRy16 |
1793 |
24401U, // MultuRxRy16 |
| 1794 |
86040401U, // MultuRxRyRz16 |
1794 |
86040401U, // MultuRxRyRz16 |
| 1795 |
0U, // NOP |
1795 |
0U, // NOP |
| 1796 |
536894182U, // NORImm |
1796 |
536894182U, // NORImm |
| 1797 |
536894182U, // NORImm64 |
1797 |
536894182U, // NORImm64 |
| 1798 |
0U, // NOR_V_D_PSEUDO |
1798 |
0U, // NOR_V_D_PSEUDO |
| 1799 |
0U, // NOR_V_H_PSEUDO |
1799 |
0U, // NOR_V_H_PSEUDO |
| 1800 |
0U, // NOR_V_W_PSEUDO |
1800 |
0U, // NOR_V_W_PSEUDO |
| 1801 |
0U, // OR_V_D_PSEUDO |
1801 |
0U, // OR_V_D_PSEUDO |
| 1802 |
0U, // OR_V_H_PSEUDO |
1802 |
0U, // OR_V_H_PSEUDO |
| 1803 |
0U, // OR_V_W_PSEUDO |
1803 |
0U, // OR_V_W_PSEUDO |
| 1804 |
0U, // PseudoCMPU_EQ_QB |
1804 |
0U, // PseudoCMPU_EQ_QB |
| 1805 |
0U, // PseudoCMPU_LE_QB |
1805 |
0U, // PseudoCMPU_LE_QB |
| 1806 |
0U, // PseudoCMPU_LT_QB |
1806 |
0U, // PseudoCMPU_LT_QB |
| 1807 |
0U, // PseudoCMP_EQ_PH |
1807 |
0U, // PseudoCMP_EQ_PH |
| 1808 |
0U, // PseudoCMP_LE_PH |
1808 |
0U, // PseudoCMP_LE_PH |
| 1809 |
0U, // PseudoCMP_LT_PH |
1809 |
0U, // PseudoCMP_LT_PH |
| 1810 |
16390U, // PseudoCVT_D32_W |
1810 |
16390U, // PseudoCVT_D32_W |
| 1811 |
16390U, // PseudoCVT_D64_L |
1811 |
16390U, // PseudoCVT_D64_L |
| 1812 |
16390U, // PseudoCVT_D64_W |
1812 |
16390U, // PseudoCVT_D64_W |
| 1813 |
16390U, // PseudoCVT_S_L |
1813 |
16390U, // PseudoCVT_S_L |
| 1814 |
16390U, // PseudoCVT_S_W |
1814 |
16390U, // PseudoCVT_S_W |
| 1815 |
0U, // PseudoDMULT |
1815 |
0U, // PseudoDMULT |
| 1816 |
0U, // PseudoDMULTu |
1816 |
0U, // PseudoDMULTu |
| 1817 |
0U, // PseudoDSDIV |
1817 |
0U, // PseudoDSDIV |
| 1818 |
0U, // PseudoDUDIV |
1818 |
0U, // PseudoDUDIV |
| 1819 |
0U, // PseudoD_SELECT_I |
1819 |
0U, // PseudoD_SELECT_I |
| 1820 |
0U, // PseudoD_SELECT_I64 |
1820 |
0U, // PseudoD_SELECT_I64 |
| 1821 |
0U, // PseudoIndirectBranch |
1821 |
0U, // PseudoIndirectBranch |
| 1822 |
0U, // PseudoIndirectBranch64 |
1822 |
0U, // PseudoIndirectBranch64 |
| 1823 |
0U, // PseudoIndirectBranch64R6 |
1823 |
0U, // PseudoIndirectBranch64R6 |
| 1824 |
0U, // PseudoIndirectBranchR6 |
1824 |
0U, // PseudoIndirectBranchR6 |
| 1825 |
0U, // PseudoIndirectBranch_MM |
1825 |
0U, // PseudoIndirectBranch_MM |
| 1826 |
0U, // PseudoIndirectBranch_MMR6 |
1826 |
0U, // PseudoIndirectBranch_MMR6 |
| 1827 |
0U, // PseudoIndirectHazardBranch |
1827 |
0U, // PseudoIndirectHazardBranch |
| 1828 |
0U, // PseudoIndirectHazardBranch64 |
1828 |
0U, // PseudoIndirectHazardBranch64 |
| 1829 |
0U, // PseudoIndrectHazardBranch64R6 |
1829 |
0U, // PseudoIndrectHazardBranch64R6 |
| 1830 |
0U, // PseudoIndrectHazardBranchR6 |
1830 |
0U, // PseudoIndrectHazardBranchR6 |
| 1831 |
0U, // PseudoMADD |
1831 |
0U, // PseudoMADD |
| 1832 |
0U, // PseudoMADDU |
1832 |
0U, // PseudoMADDU |
| 1833 |
0U, // PseudoMADDU_MM |
1833 |
0U, // PseudoMADDU_MM |
| 1834 |
0U, // PseudoMADD_MM |
1834 |
0U, // PseudoMADD_MM |
| 1835 |
0U, // PseudoMFHI |
1835 |
0U, // PseudoMFHI |
| 1836 |
0U, // PseudoMFHI64 |
1836 |
0U, // PseudoMFHI64 |
| 1837 |
0U, // PseudoMFHI_MM |
1837 |
0U, // PseudoMFHI_MM |
| 1838 |
0U, // PseudoMFLO |
1838 |
0U, // PseudoMFLO |
| 1839 |
0U, // PseudoMFLO64 |
1839 |
0U, // PseudoMFLO64 |
| 1840 |
0U, // PseudoMFLO_MM |
1840 |
0U, // PseudoMFLO_MM |
| 1841 |
0U, // PseudoMSUB |
1841 |
0U, // PseudoMSUB |
| 1842 |
0U, // PseudoMSUBU |
1842 |
0U, // PseudoMSUBU |
| 1843 |
0U, // PseudoMSUBU_MM |
1843 |
0U, // PseudoMSUBU_MM |
| 1844 |
0U, // PseudoMSUB_MM |
1844 |
0U, // PseudoMSUB_MM |
| 1845 |
0U, // PseudoMTLOHI |
1845 |
0U, // PseudoMTLOHI |
| 1846 |
0U, // PseudoMTLOHI64 |
1846 |
0U, // PseudoMTLOHI64 |
| 1847 |
0U, // PseudoMTLOHI_DSP |
1847 |
0U, // PseudoMTLOHI_DSP |
| 1848 |
0U, // PseudoMTLOHI_MM |
1848 |
0U, // PseudoMTLOHI_MM |
| 1849 |
0U, // PseudoMULT |
1849 |
0U, // PseudoMULT |
| 1850 |
0U, // PseudoMULT_MM |
1850 |
0U, // PseudoMULT_MM |
| 1851 |
0U, // PseudoMULTu |
1851 |
0U, // PseudoMULTu |
| 1852 |
0U, // PseudoMULTu_MM |
1852 |
0U, // PseudoMULTu_MM |
| 1853 |
0U, // PseudoPICK_PH |
1853 |
0U, // PseudoPICK_PH |
| 1854 |
0U, // PseudoPICK_QB |
1854 |
0U, // PseudoPICK_QB |
| 1855 |
0U, // PseudoReturn |
1855 |
0U, // PseudoReturn |
| 1856 |
0U, // PseudoReturn64 |
1856 |
0U, // PseudoReturn64 |
| 1857 |
0U, // PseudoSDIV |
1857 |
0U, // PseudoSDIV |
| 1858 |
0U, // PseudoSELECTFP_F_D32 |
1858 |
0U, // PseudoSELECTFP_F_D32 |
| 1859 |
0U, // PseudoSELECTFP_F_D64 |
1859 |
0U, // PseudoSELECTFP_F_D64 |
| 1860 |
0U, // PseudoSELECTFP_F_I |
1860 |
0U, // PseudoSELECTFP_F_I |
| 1861 |
0U, // PseudoSELECTFP_F_I64 |
1861 |
0U, // PseudoSELECTFP_F_I64 |
| 1862 |
0U, // PseudoSELECTFP_F_S |
1862 |
0U, // PseudoSELECTFP_F_S |
| 1863 |
0U, // PseudoSELECTFP_T_D32 |
1863 |
0U, // PseudoSELECTFP_T_D32 |
| 1864 |
0U, // PseudoSELECTFP_T_D64 |
1864 |
0U, // PseudoSELECTFP_T_D64 |
| 1865 |
0U, // PseudoSELECTFP_T_I |
1865 |
0U, // PseudoSELECTFP_T_I |
| 1866 |
0U, // PseudoSELECTFP_T_I64 |
1866 |
0U, // PseudoSELECTFP_T_I64 |
| 1867 |
0U, // PseudoSELECTFP_T_S |
1867 |
0U, // PseudoSELECTFP_T_S |
| 1868 |
0U, // PseudoSELECT_D32 |
1868 |
0U, // PseudoSELECT_D32 |
| 1869 |
0U, // PseudoSELECT_D64 |
1869 |
0U, // PseudoSELECT_D64 |
| 1870 |
0U, // PseudoSELECT_I |
1870 |
0U, // PseudoSELECT_I |
| 1871 |
0U, // PseudoSELECT_I64 |
1871 |
0U, // PseudoSELECT_I64 |
| 1872 |
0U, // PseudoSELECT_S |
1872 |
0U, // PseudoSELECT_S |
| 1873 |
536891300U, // PseudoTRUNC_W_D |
1873 |
536891300U, // PseudoTRUNC_W_D |
| 1874 |
536891300U, // PseudoTRUNC_W_D32 |
1874 |
536891300U, // PseudoTRUNC_W_D32 |
| 1875 |
536894799U, // PseudoTRUNC_W_S |
1875 |
536894799U, // PseudoTRUNC_W_S |
| 1876 |
0U, // PseudoUDIV |
1876 |
0U, // PseudoUDIV |
| 1877 |
536893654U, // ROL |
1877 |
536893654U, // ROL |
| 1878 |
536893654U, // ROLImm |
1878 |
536893654U, // ROLImm |
| 1879 |
536894188U, // ROR |
1879 |
536894188U, // ROR |
| 1880 |
536894188U, // RORImm |
1880 |
536894188U, // RORImm |
| 1881 |
0U, // RetRA |
1881 |
0U, // RetRA |
| 1882 |
0U, // RetRA16 |
1882 |
0U, // RetRA16 |
| 1883 |
50351255U, // SDC1_M1 |
1883 |
50351255U, // SDC1_M1 |
| 1884 |
0U, // SDIV_MM_Pseudo |
1884 |
0U, // SDIV_MM_Pseudo |
| 1885 |
50358156U, // SDMacro |
1885 |
50358156U, // SDMacro |
| 1886 |
536895420U, // SDivIMacro |
1886 |
536895420U, // SDivIMacro |
| 1887 |
536895420U, // SDivMacro |
1887 |
536895420U, // SDivMacro |
| 1888 |
536897473U, // SEQIMacro |
1888 |
536897473U, // SEQIMacro |
| 1889 |
536897473U, // SEQMacro |
1889 |
536897473U, // SEQMacro |
| 1890 |
536891526U, // SGE |
1890 |
536891526U, // SGE |
| 1891 |
536891526U, // SGEImm |
1891 |
536891526U, // SGEImm |
| 1892 |
536891526U, // SGEImm64 |
1892 |
536891526U, // SGEImm64 |
| 1893 |
536895162U, // SGEU |
1893 |
536895162U, // SGEU |
| 1894 |
536895162U, // SGEUImm |
1894 |
536895162U, // SGEUImm |
| 1895 |
536895162U, // SGEUImm64 |
1895 |
536895162U, // SGEUImm64 |
| 1896 |
536895042U, // SGTImm |
1896 |
536895042U, // SGTImm |
| 1897 |
536895042U, // SGTImm64 |
1897 |
536895042U, // SGTImm64 |
| 1898 |
536895288U, // SGTUImm |
1898 |
536895288U, // SGTUImm |
| 1899 |
536895288U, // SGTUImm64 |
1899 |
536895288U, // SGTUImm64 |
| 1900 |
536891571U, // SLE |
1900 |
536891571U, // SLE |
| 1901 |
536891571U, // SLEImm |
1901 |
536891571U, // SLEImm |
| 1902 |
536891571U, // SLEImm64 |
1902 |
536891571U, // SLEImm64 |
| 1903 |
536895180U, // SLEU |
1903 |
536895180U, // SLEU |
| 1904 |
536895180U, // SLEUImm |
1904 |
536895180U, // SLEUImm |
| 1905 |
536895180U, // SLEUImm64 |
1905 |
536895180U, // SLEUImm64 |
| 1906 |
536895058U, // SLTImm64 |
1906 |
536895058U, // SLTImm64 |
| 1907 |
536895300U, // SLTUImm64 |
1907 |
536895300U, // SLTUImm64 |
| 1908 |
536897424U, // SNEIMacro |
1908 |
536897424U, // SNEIMacro |
| 1909 |
536897424U, // SNEMacro |
1909 |
536897424U, // SNEMacro |
| 1910 |
0U, // SNZ_B_PSEUDO |
1910 |
0U, // SNZ_B_PSEUDO |
| 1911 |
0U, // SNZ_D_PSEUDO |
1911 |
0U, // SNZ_D_PSEUDO |
| 1912 |
0U, // SNZ_H_PSEUDO |
1912 |
0U, // SNZ_H_PSEUDO |
| 1913 |
0U, // SNZ_V_PSEUDO |
1913 |
0U, // SNZ_V_PSEUDO |
| 1914 |
0U, // SNZ_W_PSEUDO |
1914 |
0U, // SNZ_W_PSEUDO |
| 1915 |
536893773U, // SRemIMacro |
1915 |
536893773U, // SRemIMacro |
| 1916 |
536893773U, // SRemMacro |
1916 |
536893773U, // SRemMacro |
| 1917 |
50348038U, // STORE_ACC128 |
1917 |
50348038U, // STORE_ACC128 |
| 1918 |
50348038U, // STORE_ACC64 |
1918 |
50348038U, // STORE_ACC64 |
| 1919 |
50348038U, // STORE_ACC64DSP |
1919 |
50348038U, // STORE_ACC64DSP |
| 1920 |
50354670U, // STORE_CCOND_DSP |
1920 |
50354670U, // STORE_CCOND_DSP |
| 1921 |
0U, // STR_D |
1921 |
0U, // STR_D |
| 1922 |
0U, // STR_W |
1922 |
0U, // STR_W |
| 1923 |
0U, // ST_F16 |
1923 |
0U, // ST_F16 |
| 1924 |
72037U, // SWM_MM |
1924 |
72037U, // SWM_MM |
| 1925 |
0U, // SZ_B_PSEUDO |
1925 |
0U, // SZ_B_PSEUDO |
| 1926 |
0U, // SZ_D_PSEUDO |
1926 |
0U, // SZ_D_PSEUDO |
| 1927 |
0U, // SZ_H_PSEUDO |
1927 |
0U, // SZ_H_PSEUDO |
| 1928 |
0U, // SZ_V_PSEUDO |
1928 |
0U, // SZ_V_PSEUDO |
| 1929 |
0U, // SZ_W_PSEUDO |
1929 |
0U, // SZ_W_PSEUDO |
| 1930 |
50348673U, // SaaAddr |
1930 |
50348673U, // SaaAddr |
| 1931 |
50352145U, // SaadAddr |
1931 |
50352145U, // SaadAddr |
| 1932 |
2713318U, // SelBeqZ |
1932 |
2713318U, // SelBeqZ |
| 1933 |
2713291U, // SelBneZ |
1933 |
2713291U, // SelBneZ |
| 1934 |
3321977288U, // SelTBteqZCmp |
1934 |
3321977288U, // SelTBteqZCmp |
| 1935 |
3321976721U, // SelTBteqZCmpi |
1935 |
3321976721U, // SelTBteqZCmpi |
| 1936 |
3321978450U, // SelTBteqZSlt |
1936 |
3321978450U, // SelTBteqZSlt |
| 1937 |
3321976751U, // SelTBteqZSlti |
1937 |
3321976751U, // SelTBteqZSlti |
| 1938 |
3321978606U, // SelTBteqZSltiu |
1938 |
3321978606U, // SelTBteqZSltiu |
| 1939 |
3321978692U, // SelTBteqZSltu |
1939 |
3321978692U, // SelTBteqZSltu |
| 1940 |
3858848200U, // SelTBtneZCmp |
1940 |
3858848200U, // SelTBtneZCmp |
| 1941 |
3858847633U, // SelTBtneZCmpi |
1941 |
3858847633U, // SelTBtneZCmpi |
| 1942 |
3858849362U, // SelTBtneZSlt |
1942 |
3858849362U, // SelTBtneZSlt |
| 1943 |
3858847663U, // SelTBtneZSlti |
1943 |
3858847663U, // SelTBtneZSlti |
| 1944 |
3858849518U, // SelTBtneZSltiu |
1944 |
3858849518U, // SelTBtneZSltiu |
| 1945 |
3858849604U, // SelTBtneZSltu |
1945 |
3858849604U, // SelTBtneZSltu |
| 1946 |
119594578U, // SltCCRxRy16 |
1946 |
119594578U, // SltCCRxRy16 |
| 1947 |
119592879U, // SltiCCRxImmX16 |
1947 |
119592879U, // SltiCCRxImmX16 |
| 1948 |
119594734U, // SltiuCCRxImmX16 |
1948 |
119594734U, // SltiuCCRxImmX16 |
| 1949 |
119594820U, // SltuCCRxRy16 |
1949 |
119594820U, // SltuCCRxRy16 |
| 1950 |
119594820U, // SltuRxRyRz16 |
1950 |
119594820U, // SltuRxRyRz16 |
| 1951 |
0U, // TAILCALL |
1951 |
0U, // TAILCALL |
| 1952 |
0U, // TAILCALL64R6REG |
1952 |
0U, // TAILCALL64R6REG |
| 1953 |
0U, // TAILCALLHB64R6REG |
1953 |
0U, // TAILCALLHB64R6REG |
| 1954 |
0U, // TAILCALLHBR6REG |
1954 |
0U, // TAILCALLHBR6REG |
| 1955 |
0U, // TAILCALLR6REG |
1955 |
0U, // TAILCALLR6REG |
| 1956 |
0U, // TAILCALLREG |
1956 |
0U, // TAILCALLREG |
| 1957 |
0U, // TAILCALLREG64 |
1957 |
0U, // TAILCALLREG64 |
| 1958 |
0U, // TAILCALLREGHB |
1958 |
0U, // TAILCALLREGHB |
| 1959 |
0U, // TAILCALLREGHB64 |
1959 |
0U, // TAILCALLREGHB64 |
| 1960 |
0U, // TAILCALLREG_MM |
1960 |
0U, // TAILCALLREG_MM |
| 1961 |
0U, // TAILCALLREG_MMR6 |
1961 |
0U, // TAILCALLREG_MMR6 |
| 1962 |
0U, // TAILCALL_MM |
1962 |
0U, // TAILCALL_MM |
| 1963 |
0U, // TAILCALL_MMR6 |
1963 |
0U, // TAILCALL_MMR6 |
| 1964 |
0U, // TRAP |
1964 |
0U, // TRAP |
| 1965 |
0U, // TRAP_MM |
1965 |
0U, // TRAP_MM |
| 1966 |
0U, // UDIV_MM_Pseudo |
1966 |
0U, // UDIV_MM_Pseudo |
| 1967 |
536895328U, // UDivIMacro |
1967 |
536895328U, // UDivIMacro |
| 1968 |
536895328U, // UDivMacro |
1968 |
536895328U, // UDivMacro |
| 1969 |
536895251U, // URemIMacro |
1969 |
536895251U, // URemIMacro |
| 1970 |
536895251U, // URemMacro |
1970 |
536895251U, // URemMacro |
| 1971 |
50353426U, // Ulh |
1971 |
50353426U, // Ulh |
| 1972 |
50355922U, // Ulhu |
1972 |
50355922U, // Ulhu |
| 1973 |
50357901U, // Ulw |
1973 |
50357901U, // Ulw |
| 1974 |
50353979U, // Ush |
1974 |
50353979U, // Ush |
| 1975 |
50357917U, // Usw |
1975 |
50357917U, // Usw |
| 1976 |
0U, // XOR_V_D_PSEUDO |
1976 |
0U, // XOR_V_D_PSEUDO |
| 1977 |
0U, // XOR_V_H_PSEUDO |
1977 |
0U, // XOR_V_H_PSEUDO |
| 1978 |
0U, // XOR_V_W_PSEUDO |
1978 |
0U, // XOR_V_W_PSEUDO |
| 1979 |
22052U, // ABSQ_S_PH |
1979 |
22052U, // ABSQ_S_PH |
| 1980 |
22052U, // ABSQ_S_PH_MM |
1980 |
22052U, // ABSQ_S_PH_MM |
| 1981 |
18197U, // ABSQ_S_QB |
1981 |
18197U, // ABSQ_S_QB |
| 1982 |
18197U, // ABSQ_S_QB_MMR2 |
1982 |
18197U, // ABSQ_S_QB_MMR2 |
| 1983 |
25616U, // ABSQ_S_W |
1983 |
25616U, // ABSQ_S_W |
| 1984 |
25616U, // ABSQ_S_W_MM |
1984 |
25616U, // ABSQ_S_W_MM |
| 1985 |
536891430U, // ADD |
1985 |
536891430U, // ADD |
| 1986 |
18483U, // ADDIUPC |
1986 |
18483U, // ADDIUPC |
| 1987 |
18483U, // ADDIUPC_MM |
1987 |
18483U, // ADDIUPC_MM |
| 1988 |
18483U, // ADDIUPC_MMR6 |
1988 |
18483U, // ADDIUPC_MMR6 |
| 1989 |
22995U, // ADDIUR1SP_MM |
1989 |
22995U, // ADDIUR1SP_MM |
| 1990 |
536887674U, // ADDIUR2_MM |
1990 |
536887674U, // ADDIUR2_MM |
| 1991 |
18923931U, // ADDIUS5_MM |
1991 |
18923931U, // ADDIUS5_MM |
| 1992 |
547344U, // ADDIUSP_MM |
1992 |
547344U, // ADDIUSP_MM |
| 1993 |
536895200U, // ADDIU_MMR6 |
1993 |
536895200U, // ADDIU_MMR6 |
| 1994 |
536892769U, // ADDQH_PH |
1994 |
536892769U, // ADDQH_PH |
| 1995 |
536892769U, // ADDQH_PH_MMR2 |
1995 |
536892769U, // ADDQH_PH_MMR2 |
| 1996 |
536892886U, // ADDQH_R_PH |
1996 |
536892886U, // ADDQH_R_PH |
| 1997 |
536892886U, // ADDQH_R_PH_MMR2 |
1997 |
536892886U, // ADDQH_R_PH_MMR2 |
| 1998 |
536896203U, // ADDQH_R_W |
1998 |
536896203U, // ADDQH_R_W |
| 1999 |
536896203U, // ADDQH_R_W_MMR2 |
1999 |
536896203U, // ADDQH_R_W_MMR2 |
| 2000 |
536895806U, // ADDQH_W |
2000 |
536895806U, // ADDQH_W |
| 2001 |
536895806U, // ADDQH_W_MMR2 |
2001 |
536895806U, // ADDQH_W_MMR2 |
| 2002 |
536892843U, // ADDQ_PH |
2002 |
536892843U, // ADDQ_PH |
| 2003 |
536892843U, // ADDQ_PH_MM |
2003 |
536892843U, // ADDQ_PH_MM |
| 2004 |
536892942U, // ADDQ_S_PH |
2004 |
536892942U, // ADDQ_S_PH |
| 2005 |
536892942U, // ADDQ_S_PH_MM |
2005 |
536892942U, // ADDQ_S_PH_MM |
| 2006 |
536896508U, // ADDQ_S_W |
2006 |
536896508U, // ADDQ_S_W |
| 2007 |
536896508U, // ADDQ_S_W_MM |
2007 |
536896508U, // ADDQ_S_W_MM |
| 2008 |
536894967U, // ADDR_PS64 |
2008 |
536894967U, // ADDR_PS64 |
| 2009 |
536889435U, // ADDSC |
2009 |
536889435U, // ADDSC |
| 2010 |
536889435U, // ADDSC_MM |
2010 |
536889435U, // ADDSC_MM |
| 2011 |
536888059U, // ADDS_A_B |
2011 |
536888059U, // ADDS_A_B |
| 2012 |
536889596U, // ADDS_A_D |
2012 |
536889596U, // ADDS_A_D |
| 2013 |
536891696U, // ADDS_A_H |
2013 |
536891696U, // ADDS_A_H |
| 2014 |
536895514U, // ADDS_A_W |
2014 |
536895514U, // ADDS_A_W |
| 2015 |
536888527U, // ADDS_S_B |
2015 |
536888527U, // ADDS_S_B |
| 2016 |
536890694U, // ADDS_S_D |
2016 |
536890694U, // ADDS_S_D |
| 2017 |
536892253U, // ADDS_S_H |
2017 |
536892253U, // ADDS_S_H |
| 2018 |
536896558U, // ADDS_S_W |
2018 |
536896558U, // ADDS_S_W |
| 2019 |
536888742U, // ADDS_U_B |
2019 |
536888742U, // ADDS_U_B |
| 2020 |
536891161U, // ADDS_U_D |
2020 |
536891161U, // ADDS_U_D |
| 2021 |
536892531U, // ADDS_U_H |
2021 |
536892531U, // ADDS_U_H |
| 2022 |
536896976U, // ADDS_U_W |
2022 |
536896976U, // ADDS_U_W |
| 2023 |
536887894U, // ADDU16_MM |
2023 |
536887894U, // ADDU16_MM |
| 2024 |
536887894U, // ADDU16_MMR6 |
2024 |
536887894U, // ADDU16_MMR6 |
| 2025 |
536888977U, // ADDUH_QB |
2025 |
536888977U, // ADDUH_QB |
| 2026 |
536888977U, // ADDUH_QB_MMR2 |
2026 |
536888977U, // ADDUH_QB_MMR2 |
| 2027 |
536889085U, // ADDUH_R_QB |
2027 |
536889085U, // ADDUH_R_QB |
| 2028 |
536889085U, // ADDUH_R_QB_MMR2 |
2028 |
536889085U, // ADDUH_R_QB_MMR2 |
| 2029 |
536895129U, // ADDU_MMR6 |
2029 |
536895129U, // ADDU_MMR6 |
| 2030 |
536893041U, // ADDU_PH |
2030 |
536893041U, // ADDU_PH |
| 2031 |
536893041U, // ADDU_PH_MMR2 |
2031 |
536893041U, // ADDU_PH_MMR2 |
| 2032 |
536889190U, // ADDU_QB |
2032 |
536889190U, // ADDU_QB |
| 2033 |
536889190U, // ADDU_QB_MM |
2033 |
536889190U, // ADDU_QB_MM |
| 2034 |
536892986U, // ADDU_S_PH |
2034 |
536892986U, // ADDU_S_PH |
| 2035 |
536892986U, // ADDU_S_PH_MMR2 |
2035 |
536892986U, // ADDU_S_PH_MMR2 |
| 2036 |
536889131U, // ADDU_S_QB |
2036 |
536889131U, // ADDU_S_QB |
| 2037 |
536889131U, // ADDU_S_QB_MM |
2037 |
536889131U, // ADDU_S_QB_MM |
| 2038 |
536888308U, // ADDVI_B |
2038 |
536888308U, // ADDVI_B |
| 2039 |
536890116U, // ADDVI_D |
2039 |
536890116U, // ADDVI_D |
| 2040 |
536891912U, // ADDVI_H |
2040 |
536891912U, // ADDVI_H |
| 2041 |
536895939U, // ADDVI_W |
2041 |
536895939U, // ADDVI_W |
| 2042 |
536888820U, // ADDV_B |
2042 |
536888820U, // ADDV_B |
| 2043 |
536891251U, // ADDV_D |
2043 |
536891251U, // ADDV_D |
| 2044 |
536892609U, // ADDV_H |
2044 |
536892609U, // ADDV_H |
| 2045 |
536897076U, // ADDV_W |
2045 |
536897076U, // ADDV_W |
| 2046 |
536889474U, // ADDWC |
2046 |
536889474U, // ADDWC |
| 2047 |
536889474U, // ADDWC_MM |
2047 |
536889474U, // ADDWC_MM |
| 2048 |
536888041U, // ADD_A_B |
2048 |
536888041U, // ADD_A_B |
| 2049 |
536889577U, // ADD_A_D |
2049 |
536889577U, // ADD_A_D |
| 2050 |
536891678U, // ADD_A_H |
2050 |
536891678U, // ADD_A_H |
| 2051 |
536895495U, // ADD_A_W |
2051 |
536895495U, // ADD_A_W |
| 2052 |
536891430U, // ADD_MM |
2052 |
536891430U, // ADD_MM |
| 2053 |
536891430U, // ADD_MMR6 |
2053 |
536891430U, // ADD_MMR6 |
| 2054 |
536893262U, // ADDi |
2054 |
536893262U, // ADDi |
| 2055 |
536893262U, // ADDi_MM |
2055 |
536893262U, // ADDi_MM |
| 2056 |
536895200U, // ADDiu |
2056 |
536895200U, // ADDiu |
| 2057 |
536895200U, // ADDiu_MM |
2057 |
536895200U, // ADDiu_MM |
| 2058 |
536895129U, // ADDu |
2058 |
536895129U, // ADDu |
| 2059 |
536895129U, // ADDu_MM |
2059 |
536895129U, // ADDu_MM |
| 2060 |
536893803U, // ALIGN |
2060 |
536893803U, // ALIGN |
| 2061 |
536893803U, // ALIGN_MMR6 |
2061 |
536893803U, // ALIGN_MMR6 |
| 2062 |
18475U, // ALUIPC |
2062 |
18475U, // ALUIPC |
| 2063 |
18475U, // ALUIPC_MMR6 |
2063 |
18475U, // ALUIPC_MMR6 |
| 2064 |
536891459U, // AND |
2064 |
536891459U, // AND |
| 2065 |
20021705U, // AND16_MM |
2065 |
20021705U, // AND16_MM |
| 2066 |
20021705U, // AND16_MMR6 |
2066 |
20021705U, // AND16_MMR6 |
| 2067 |
536891459U, // AND64 |
2067 |
536891459U, // AND64 |
| 2068 |
536887774U, // ANDI16_MM |
2068 |
536887774U, // ANDI16_MM |
| 2069 |
536887774U, // ANDI16_MMR6 |
2069 |
536887774U, // ANDI16_MMR6 |
| 2070 |
536888167U, // ANDI_B |
2070 |
536888167U, // ANDI_B |
| 2071 |
536893268U, // ANDI_MMR6 |
2071 |
536893268U, // ANDI_MMR6 |
| 2072 |
536891459U, // AND_MM |
2072 |
536891459U, // AND_MM |
| 2073 |
536891459U, // AND_MMR6 |
2073 |
536891459U, // AND_MMR6 |
| 2074 |
536895339U, // AND_V |
2074 |
536895339U, // AND_V |
| 2075 |
536893268U, // ANDi |
2075 |
536893268U, // ANDi |
| 2076 |
536893268U, // ANDi64 |
2076 |
536893268U, // ANDi64 |
| 2077 |
536893268U, // ANDi_MM |
2077 |
536893268U, // ANDi_MM |
| 2078 |
536891473U, // APPEND |
2078 |
536891473U, // APPEND |
| 2079 |
536891473U, // APPEND_MMR2 |
2079 |
536891473U, // APPEND_MMR2 |
| 2080 |
536888421U, // ASUB_S_B |
2080 |
536888421U, // ASUB_S_B |
| 2081 |
536890524U, // ASUB_S_D |
2081 |
536890524U, // ASUB_S_D |
| 2082 |
536892085U, // ASUB_S_H |
2082 |
536892085U, // ASUB_S_H |
| 2083 |
536896338U, // ASUB_S_W |
2083 |
536896338U, // ASUB_S_W |
| 2084 |
536888636U, // ASUB_U_B |
2084 |
536888636U, // ASUB_U_B |
| 2085 |
536890991U, // ASUB_U_D |
2085 |
536890991U, // ASUB_U_D |
| 2086 |
536892373U, // ASUB_U_H |
2086 |
536892373U, // ASUB_U_H |
| 2087 |
536896806U, // ASUB_U_W |
2087 |
536896806U, // ASUB_U_W |
| 2088 |
536893372U, // AUI |
2088 |
536893372U, // AUI |
| 2089 |
18468U, // AUIPC |
2089 |
18468U, // AUIPC |
| 2090 |
18468U, // AUIPC_MMR6 |
2090 |
18468U, // AUIPC_MMR6 |
| 2091 |
536893372U, // AUI_MMR6 |
2091 |
536893372U, // AUI_MMR6 |
| 2092 |
536888507U, // AVER_S_B |
2092 |
536888507U, // AVER_S_B |
| 2093 |
536890674U, // AVER_S_D |
2093 |
536890674U, // AVER_S_D |
| 2094 |
536892223U, // AVER_S_H |
2094 |
536892223U, // AVER_S_H |
| 2095 |
536896538U, // AVER_S_W |
2095 |
536896538U, // AVER_S_W |
| 2096 |
536888722U, // AVER_U_B |
2096 |
536888722U, // AVER_U_B |
| 2097 |
536891141U, // AVER_U_D |
2097 |
536891141U, // AVER_U_D |
| 2098 |
536892511U, // AVER_U_H |
2098 |
536892511U, // AVER_U_H |
| 2099 |
536896956U, // AVER_U_W |
2099 |
536896956U, // AVER_U_W |
| 2100 |
536888449U, // AVE_S_B |
2100 |
536888449U, // AVE_S_B |
| 2101 |
536890606U, // AVE_S_D |
2101 |
536890606U, // AVE_S_D |
| 2102 |
536892155U, // AVE_S_H |
2102 |
536892155U, // AVE_S_H |
| 2103 |
536896420U, // AVE_S_W |
2103 |
536896420U, // AVE_S_W |
| 2104 |
536888664U, // AVE_U_B |
2104 |
536888664U, // AVE_U_B |
| 2105 |
536891073U, // AVE_U_D |
2105 |
536891073U, // AVE_U_D |
| 2106 |
536892443U, // AVE_U_H |
2106 |
536892443U, // AVE_U_H |
| 2107 |
536896888U, // AVE_U_W |
2107 |
536896888U, // AVE_U_W |
| 2108 |
24288U, // AddiuRxImmX16 |
2108 |
24288U, // AddiuRxImmX16 |
| 2109 |
3694304U, // AddiuRxPcImmX16 |
2109 |
3694304U, // AddiuRxPcImmX16 |
| 2110 |
33578720U, // AddiuRxRxImm16 |
2110 |
33578720U, // AddiuRxRxImm16 |
| 2111 |
33578720U, // AddiuRxRxImmX16 |
2111 |
33578720U, // AddiuRxRxImmX16 |
| 2112 |
134242016U, // AddiuRxRyOffMemX16 |
2112 |
134242016U, // AddiuRxRyOffMemX16 |
| 2113 |
4220724U, // AddiuSpImm16 |
2113 |
4220724U, // AddiuSpImm16 |
| 2114 |
550708U, // AddiuSpImmX16 |
2114 |
550708U, // AddiuSpImmX16 |
| 2115 |
536895129U, // AdduRxRyRz16 |
2115 |
536895129U, // AdduRxRyRz16 |
| 2116 |
33574979U, // AndRxRxRy16 |
2116 |
33574979U, // AndRxRxRy16 |
| 2117 |
557477U, // B16_MM |
2117 |
557477U, // B16_MM |
| 2118 |
536895128U, // BADDu |
2118 |
536895128U, // BADDu |
| 2119 |
563183U, // BAL |
2119 |
563183U, // BAL |
| 2120 |
559061U, // BALC |
2120 |
559061U, // BALC |
| 2121 |
559061U, // BALC_MMR6 |
2121 |
559061U, // BALC_MMR6 |
| 2122 |
536893802U, // BALIGN |
2122 |
536893802U, // BALIGN |
| 2123 |
536893802U, // BALIGN_MMR2 |
2123 |
536893802U, // BALIGN_MMR2 |
| 2124 |
151011407U, // BBIT0 |
2124 |
151011407U, // BBIT0 |
| 2125 |
151011539U, // BBIT032 |
2125 |
151011539U, // BBIT032 |
| 2126 |
151011532U, // BBIT1 |
2126 |
151011532U, // BBIT1 |
| 2127 |
151011548U, // BBIT132 |
2127 |
151011548U, // BBIT132 |
| 2128 |
559040U, // BC |
2128 |
559040U, // BC |
| 2129 |
557482U, // BC16_MMR6 |
2129 |
557482U, // BC16_MMR6 |
| 2130 |
167798780U, // BC1EQZ |
2130 |
167798780U, // BC1EQZ |
| 2131 |
167790768U, // BC1EQZC_MMR6 |
2131 |
167790768U, // BC1EQZC_MMR6 |
| 2132 |
167792903U, // BC1F |
2132 |
167792903U, // BC1F |
| 2133 |
167794796U, // BC1FL |
2133 |
167794796U, // BC1FL |
| 2134 |
167792903U, // BC1F_MM |
2134 |
167792903U, // BC1F_MM |
| 2135 |
167798764U, // BC1NEZ |
2135 |
167798764U, // BC1NEZ |
| 2136 |
167790743U, // BC1NEZC_MMR6 |
2136 |
167790743U, // BC1NEZC_MMR6 |
| 2137 |
167796279U, // BC1T |
2137 |
167796279U, // BC1T |
| 2138 |
167794929U, // BC1TL |
2138 |
167794929U, // BC1TL |
| 2139 |
167796279U, // BC1T_MM |
2139 |
167796279U, // BC1T_MM |
| 2140 |
167798788U, // BC2EQZ |
2140 |
167798788U, // BC2EQZ |
| 2141 |
167790777U, // BC2EQZC_MMR6 |
2141 |
167790777U, // BC2EQZC_MMR6 |
| 2142 |
167798772U, // BC2NEZ |
2142 |
167798772U, // BC2NEZ |
| 2143 |
167790752U, // BC2NEZC_MMR6 |
2143 |
167790752U, // BC2NEZC_MMR6 |
| 2144 |
536888236U, // BCLRI_B |
2144 |
536888236U, // BCLRI_B |
| 2145 |
536890060U, // BCLRI_D |
2145 |
536890060U, // BCLRI_D |
| 2146 |
536891856U, // BCLRI_H |
2146 |
536891856U, // BCLRI_H |
| 2147 |
536895883U, // BCLRI_W |
2147 |
536895883U, // BCLRI_W |
| 2148 |
536888388U, // BCLR_B |
2148 |
536888388U, // BCLR_B |
| 2149 |
536890448U, // BCLR_D |
2149 |
536890448U, // BCLR_D |
| 2150 |
536892052U, // BCLR_H |
2150 |
536892052U, // BCLR_H |
| 2151 |
536896254U, // BCLR_W |
2151 |
536896254U, // BCLR_W |
| 2152 |
559040U, // BC_MMR6 |
2152 |
559040U, // BC_MMR6 |
| 2153 |
536894020U, // BEQ |
2153 |
536894020U, // BEQ |
| 2154 |
536894020U, // BEQ64 |
2154 |
536894020U, // BEQ64 |
| 2155 |
536889417U, // BEQC |
2155 |
536889417U, // BEQC |
| 2156 |
536889417U, // BEQC64 |
2156 |
536889417U, // BEQC64 |
| 2157 |
536889417U, // BEQC_MMR6 |
2157 |
536889417U, // BEQC_MMR6 |
| 2158 |
536893669U, // BEQL |
2158 |
536893669U, // BEQL |
| 2159 |
167789177U, // BEQZ16_MM |
2159 |
167789177U, // BEQZ16_MM |
| 2160 |
167790589U, // BEQZALC |
2160 |
167790589U, // BEQZALC |
| 2161 |
167790589U, // BEQZALC_MMR6 |
2161 |
167790589U, // BEQZALC_MMR6 |
| 2162 |
167790786U, // BEQZC |
2162 |
167790786U, // BEQZC |
| 2163 |
167788992U, // BEQZC16_MMR6 |
2163 |
167788992U, // BEQZC16_MMR6 |
| 2164 |
167790786U, // BEQZC64 |
2164 |
167790786U, // BEQZC64 |
| 2165 |
167790786U, // BEQZC_MM |
2165 |
167790786U, // BEQZC_MM |
| 2166 |
167790786U, // BEQZC_MMR6 |
2166 |
167790786U, // BEQZC_MMR6 |
| 2167 |
536894020U, // BEQ_MM |
2167 |
536894020U, // BEQ_MM |
| 2168 |
536889284U, // BGEC |
2168 |
536889284U, // BGEC |
| 2169 |
536889284U, // BGEC64 |
2169 |
536889284U, // BGEC64 |
| 2170 |
536889284U, // BGEC_MMR6 |
2170 |
536889284U, // BGEC_MMR6 |
| 2171 |
536889448U, // BGEUC |
2171 |
536889448U, // BGEUC |
| 2172 |
536889448U, // BGEUC64 |
2172 |
536889448U, // BGEUC64 |
| 2173 |
536889448U, // BGEUC_MMR6 |
2173 |
536889448U, // BGEUC_MMR6 |
| 2174 |
167798463U, // BGEZ |
2174 |
167798463U, // BGEZ |
| 2175 |
167798463U, // BGEZ64 |
2175 |
167798463U, // BGEZ64 |
| 2176 |
167794681U, // BGEZAL |
2176 |
167794681U, // BGEZAL |
| 2177 |
167790562U, // BGEZALC |
2177 |
167790562U, // BGEZALC |
| 2178 |
167790562U, // BGEZALC_MMR6 |
2178 |
167790562U, // BGEZALC_MMR6 |
| 2179 |
167794877U, // BGEZALL |
2179 |
167794877U, // BGEZALL |
| 2180 |
167796145U, // BGEZALS_MM |
2180 |
167796145U, // BGEZALS_MM |
| 2181 |
167794681U, // BGEZAL_MM |
2181 |
167794681U, // BGEZAL_MM |
| 2182 |
167790729U, // BGEZC |
2182 |
167790729U, // BGEZC |
| 2183 |
167790729U, // BGEZC64 |
2183 |
167790729U, // BGEZC64 |
| 2184 |
167790729U, // BGEZC_MMR6 |
2184 |
167790729U, // BGEZC_MMR6 |
| 2185 |
167794992U, // BGEZL |
2185 |
167794992U, // BGEZL |
| 2186 |
167798463U, // BGEZ_MM |
2186 |
167798463U, // BGEZ_MM |
| 2187 |
167798523U, // BGTZ |
2187 |
167798523U, // BGTZ |
| 2188 |
167798523U, // BGTZ64 |
2188 |
167798523U, // BGTZ64 |
| 2189 |
167790598U, // BGTZALC |
2189 |
167790598U, // BGTZALC |
| 2190 |
167790598U, // BGTZALC_MMR6 |
2190 |
167790598U, // BGTZALC_MMR6 |
| 2191 |
167790793U, // BGTZC |
2191 |
167790793U, // BGTZC |
| 2192 |
167790793U, // BGTZC64 |
2192 |
167790793U, // BGTZC64 |
| 2193 |
167790793U, // BGTZC_MMR6 |
2193 |
167790793U, // BGTZC_MMR6 |
| 2194 |
167795006U, // BGTZL |
2194 |
167795006U, // BGTZL |
| 2195 |
167798523U, // BGTZ_MM |
2195 |
167798523U, // BGTZ_MM |
| 2196 |
570442641U, // BINSLI_B |
2196 |
570442641U, // BINSLI_B |
| 2197 |
570444465U, // BINSLI_D |
2197 |
570444465U, // BINSLI_D |
| 2198 |
570446261U, // BINSLI_H |
2198 |
570446261U, // BINSLI_H |
| 2199 |
570450288U, // BINSLI_W |
2199 |
570450288U, // BINSLI_W |
| 2200 |
570442788U, // BINSL_B |
2200 |
570442788U, // BINSL_B |
| 2201 |
570444665U, // BINSL_D |
2201 |
570444665U, // BINSL_D |
| 2202 |
570446375U, // BINSL_H |
2202 |
570446375U, // BINSL_H |
| 2203 |
570450446U, // BINSL_W |
2203 |
570450446U, // BINSL_W |
| 2204 |
570442702U, // BINSRI_B |
2204 |
570442702U, // BINSRI_B |
| 2205 |
570444510U, // BINSRI_D |
2205 |
570444510U, // BINSRI_D |
| 2206 |
570446306U, // BINSRI_H |
2206 |
570446306U, // BINSRI_H |
| 2207 |
570450333U, // BINSRI_W |
2207 |
570450333U, // BINSRI_W |
| 2208 |
570442836U, // BINSR_B |
2208 |
570442836U, // BINSR_B |
| 2209 |
570444930U, // BINSR_D |
2209 |
570444930U, // BINSR_D |
| 2210 |
570446500U, // BINSR_H |
2210 |
570446500U, // BINSR_H |
| 2211 |
570450736U, // BINSR_W |
2211 |
570450736U, // BINSR_W |
| 2212 |
24499U, // BITREV |
2212 |
24499U, // BITREV |
| 2213 |
24499U, // BITREV_MM |
2213 |
24499U, // BITREV_MM |
| 2214 |
22945U, // BITSWAP |
2214 |
22945U, // BITSWAP |
| 2215 |
22945U, // BITSWAP_MMR6 |
2215 |
22945U, // BITSWAP_MMR6 |
| 2216 |
167798469U, // BLEZ |
2216 |
167798469U, // BLEZ |
| 2217 |
167798469U, // BLEZ64 |
2217 |
167798469U, // BLEZ64 |
| 2218 |
167790571U, // BLEZALC |
2218 |
167790571U, // BLEZALC |
| 2219 |
167790571U, // BLEZALC_MMR6 |
2219 |
167790571U, // BLEZALC_MMR6 |
| 2220 |
167790736U, // BLEZC |
2220 |
167790736U, // BLEZC |
| 2221 |
167790736U, // BLEZC64 |
2221 |
167790736U, // BLEZC64 |
| 2222 |
167790736U, // BLEZC_MMR6 |
2222 |
167790736U, // BLEZC_MMR6 |
| 2223 |
167794999U, // BLEZL |
2223 |
167794999U, // BLEZL |
| 2224 |
167798469U, // BLEZ_MM |
2224 |
167798469U, // BLEZ_MM |
| 2225 |
536889442U, // BLTC |
2225 |
536889442U, // BLTC |
| 2226 |
536889442U, // BLTC64 |
2226 |
536889442U, // BLTC64 |
| 2227 |
536889442U, // BLTC_MMR6 |
2227 |
536889442U, // BLTC_MMR6 |
| 2228 |
536889455U, // BLTUC |
2228 |
536889455U, // BLTUC |
| 2229 |
536889455U, // BLTUC64 |
2229 |
536889455U, // BLTUC64 |
| 2230 |
536889455U, // BLTUC_MMR6 |
2230 |
536889455U, // BLTUC_MMR6 |
| 2231 |
167798529U, // BLTZ |
2231 |
167798529U, // BLTZ |
| 2232 |
167798529U, // BLTZ64 |
2232 |
167798529U, // BLTZ64 |
| 2233 |
167794689U, // BLTZAL |
2233 |
167794689U, // BLTZAL |
| 2234 |
167790607U, // BLTZALC |
2234 |
167790607U, // BLTZALC |
| 2235 |
167790607U, // BLTZALC_MMR6 |
2235 |
167790607U, // BLTZALC_MMR6 |
| 2236 |
167794886U, // BLTZALL |
2236 |
167794886U, // BLTZALL |
| 2237 |
167796154U, // BLTZALS_MM |
2237 |
167796154U, // BLTZALS_MM |
| 2238 |
167794689U, // BLTZAL_MM |
2238 |
167794689U, // BLTZAL_MM |
| 2239 |
167790800U, // BLTZC |
2239 |
167790800U, // BLTZC |
| 2240 |
167790800U, // BLTZC64 |
2240 |
167790800U, // BLTZC64 |
| 2241 |
167790800U, // BLTZC_MMR6 |
2241 |
167790800U, // BLTZC_MMR6 |
| 2242 |
167795013U, // BLTZL |
2242 |
167795013U, // BLTZL |
| 2243 |
167798529U, // BLTZ_MM |
2243 |
167798529U, // BLTZ_MM |
| 2244 |
570442757U, // BMNZI_B |
2244 |
570442757U, // BMNZI_B |
| 2245 |
570449828U, // BMNZ_V |
2245 |
570449828U, // BMNZ_V |
| 2246 |
570442749U, // BMZI_B |
2246 |
570442749U, // BMZI_B |
| 2247 |
570449814U, // BMZ_V |
2247 |
570449814U, // BMZ_V |
| 2248 |
536891588U, // BNE |
2248 |
536891588U, // BNE |
| 2249 |
536891588U, // BNE64 |
2249 |
536891588U, // BNE64 |
| 2250 |
536889290U, // BNEC |
2250 |
536889290U, // BNEC |
| 2251 |
536889290U, // BNEC64 |
2251 |
536889290U, // BNEC64 |
| 2252 |
536889290U, // BNEC_MMR6 |
2252 |
536889290U, // BNEC_MMR6 |
| 2253 |
536888175U, // BNEGI_B |
2253 |
536888175U, // BNEGI_B |
| 2254 |
536890008U, // BNEGI_D |
2254 |
536890008U, // BNEGI_D |
| 2255 |
536891804U, // BNEGI_H |
2255 |
536891804U, // BNEGI_H |
| 2256 |
536895831U, // BNEGI_W |
2256 |
536895831U, // BNEGI_W |
| 2257 |
536888143U, // BNEG_B |
2257 |
536888143U, // BNEG_B |
| 2258 |
536889984U, // BNEG_D |
2258 |
536889984U, // BNEG_D |
| 2259 |
536891780U, // BNEG_H |
2259 |
536891780U, // BNEG_H |
| 2260 |
536895726U, // BNEG_W |
2260 |
536895726U, // BNEG_W |
| 2261 |
536893542U, // BNEL |
2261 |
536893542U, // BNEL |
| 2262 |
167789169U, // BNEZ16_MM |
2262 |
167789169U, // BNEZ16_MM |
| 2263 |
167790580U, // BNEZALC |
2263 |
167790580U, // BNEZALC |
| 2264 |
167790580U, // BNEZALC_MMR6 |
2264 |
167790580U, // BNEZALC_MMR6 |
| 2265 |
167790761U, // BNEZC |
2265 |
167790761U, // BNEZC |
| 2266 |
167788983U, // BNEZC16_MMR6 |
2266 |
167788983U, // BNEZC16_MMR6 |
| 2267 |
167790761U, // BNEZC64 |
2267 |
167790761U, // BNEZC64 |
| 2268 |
167790761U, // BNEZC_MM |
2268 |
167790761U, // BNEZC_MM |
| 2269 |
167790761U, // BNEZC_MMR6 |
2269 |
167790761U, // BNEZC_MMR6 |
| 2270 |
536891588U, // BNE_MM |
2270 |
536891588U, // BNE_MM |
| 2271 |
536889462U, // BNVC |
2271 |
536889462U, // BNVC |
| 2272 |
536889462U, // BNVC_MMR6 |
2272 |
536889462U, // BNVC_MMR6 |
| 2273 |
167790108U, // BNZ_B |
2273 |
167790108U, // BNZ_B |
| 2274 |
167792624U, // BNZ_D |
2274 |
167792624U, // BNZ_D |
| 2275 |
167793897U, // BNZ_H |
2275 |
167793897U, // BNZ_H |
| 2276 |
167796637U, // BNZ_V |
2276 |
167796637U, // BNZ_V |
| 2277 |
167798389U, // BNZ_W |
2277 |
167798389U, // BNZ_W |
| 2278 |
536889468U, // BOVC |
2278 |
536889468U, // BOVC |
| 2279 |
536889468U, // BOVC_MMR6 |
2279 |
536889468U, // BOVC_MMR6 |
| 2280 |
557293U, // BPOSGE32 |
2280 |
557293U, // BPOSGE32 |
| 2281 |
559029U, // BPOSGE32C_MMR3 |
2281 |
559029U, // BPOSGE32C_MMR3 |
| 2282 |
557293U, // BPOSGE32_MM |
2282 |
557293U, // BPOSGE32_MM |
| 2283 |
184670160U, // BREAK |
2283 |
184670160U, // BREAK |
| 2284 |
131572U, // BREAK16_MM |
2284 |
131572U, // BREAK16_MM |
| 2285 |
131572U, // BREAK16_MMR6 |
2285 |
131572U, // BREAK16_MMR6 |
| 2286 |
184670160U, // BREAK_MM |
2286 |
184670160U, // BREAK_MM |
| 2287 |
184670160U, // BREAK_MMR6 |
2287 |
184670160U, // BREAK_MMR6 |
| 2288 |
570442616U, // BSELI_B |
2288 |
570442616U, // BSELI_B |
| 2289 |
570449786U, // BSEL_V |
2289 |
570449786U, // BSEL_V |
| 2290 |
536888290U, // BSETI_B |
2290 |
536888290U, // BSETI_B |
| 2291 |
536890098U, // BSETI_D |
2291 |
536890098U, // BSETI_D |
| 2292 |
536891894U, // BSETI_H |
2292 |
536891894U, // BSETI_H |
| 2293 |
536895921U, // BSETI_W |
2293 |
536895921U, // BSETI_W |
| 2294 |
536888604U, // BSET_B |
2294 |
536888604U, // BSET_B |
| 2295 |
536890810U, // BSET_D |
2295 |
536890810U, // BSET_D |
| 2296 |
536892341U, // BSET_H |
2296 |
536892341U, // BSET_H |
| 2297 |
536896712U, // BSET_W |
2297 |
536896712U, // BSET_W |
| 2298 |
167790102U, // BZ_B |
2298 |
167790102U, // BZ_B |
| 2299 |
167792608U, // BZ_D |
2299 |
167792608U, // BZ_D |
| 2300 |
167793891U, // BZ_H |
2300 |
167793891U, // BZ_H |
| 2301 |
167796624U, // BZ_V |
2301 |
167796624U, // BZ_V |
| 2302 |
167798383U, // BZ_W |
2302 |
167798383U, // BZ_W |
| 2303 |
704669414U, // BeqzRxImm16 |
2303 |
704669414U, // BeqzRxImm16 |
| 2304 |
167798502U, // BeqzRxImmX16 |
2304 |
167798502U, // BeqzRxImmX16 |
| 2305 |
4227823U, // Bimm16 |
2305 |
4227823U, // Bimm16 |
| 2306 |
557807U, // BimmX16 |
2306 |
557807U, // BimmX16 |
| 2307 |
704669387U, // BnezRxImm16 |
2307 |
704669387U, // BnezRxImm16 |
| 2308 |
167798475U, // BnezRxImmX16 |
2308 |
167798475U, // BnezRxImmX16 |
| 2309 |
10403U, // Break16 |
2309 |
10403U, // Break16 |
| 2310 |
4744948U, // Bteqz16 |
2310 |
4744948U, // Bteqz16 |
| 2311 |
550644U, // BteqzX16 |
2311 |
550644U, // BteqzX16 |
| 2312 |
4744921U, // Btnez16 |
2312 |
4744921U, // Btnez16 |
| 2313 |
550617U, // BtnezX16 |
2313 |
550617U, // BtnezX16 |
| 2314 |
5394576U, // CACHE |
2314 |
5394576U, // CACHE |
| 2315 |
5394546U, // CACHEE |
2315 |
5394546U, // CACHEE |
| 2316 |
5394546U, // CACHEE_MM |
2316 |
5394546U, // CACHEE_MM |
| 2317 |
5394576U, // CACHE_MM |
2317 |
5394576U, // CACHE_MM |
| 2318 |
5394576U, // CACHE_MMR6 |
2318 |
5394576U, // CACHE_MMR6 |
| 2319 |
5394576U, // CACHE_R6 |
2319 |
5394576U, // CACHE_R6 |
| 2320 |
19235U, // CEIL_L_D64 |
2320 |
19235U, // CEIL_L_D64 |
| 2321 |
19235U, // CEIL_L_D_MMR6 |
2321 |
19235U, // CEIL_L_D_MMR6 |
| 2322 |
23567U, // CEIL_L_S |
2322 |
23567U, // CEIL_L_S |
| 2323 |
23567U, // CEIL_L_S_MMR6 |
2323 |
23567U, // CEIL_L_S_MMR6 |
| 2324 |
20410U, // CEIL_W_D32 |
2324 |
20410U, // CEIL_W_D32 |
| 2325 |
20410U, // CEIL_W_D64 |
2325 |
20410U, // CEIL_W_D64 |
| 2326 |
20410U, // CEIL_W_D_MMR6 |
2326 |
20410U, // CEIL_W_D_MMR6 |
| 2327 |
20410U, // CEIL_W_MM |
2327 |
20410U, // CEIL_W_MM |
| 2328 |
23909U, // CEIL_W_S |
2328 |
23909U, // CEIL_W_S |
| 2329 |
23909U, // CEIL_W_S_MM |
2329 |
23909U, // CEIL_W_S_MM |
| 2330 |
23909U, // CEIL_W_S_MMR6 |
2330 |
23909U, // CEIL_W_S_MMR6 |
| 2331 |
536888219U, // CEQI_B |
2331 |
536888219U, // CEQI_B |
| 2332 |
536890043U, // CEQI_D |
2332 |
536890043U, // CEQI_D |
| 2333 |
536891839U, // CEQI_H |
2333 |
536891839U, // CEQI_H |
| 2334 |
536895866U, // CEQI_W |
2334 |
536895866U, // CEQI_W |
| 2335 |
536888373U, // CEQ_B |
2335 |
536888373U, // CEQ_B |
| 2336 |
536890355U, // CEQ_D |
2336 |
536890355U, // CEQ_D |
| 2337 |
536892030U, // CEQ_H |
2337 |
536892030U, // CEQ_H |
| 2338 |
536896142U, // CEQ_W |
2338 |
536896142U, // CEQ_W |
| 2339 |
16482U, // CFC1 |
2339 |
16482U, // CFC1 |
| 2340 |
16482U, // CFC1_MM |
2340 |
16482U, // CFC1_MM |
| 2341 |
16698U, // CFC2_MM |
2341 |
16698U, // CFC2_MM |
| 2342 |
17113U, // CFCMSA |
2342 |
17113U, // CFCMSA |
| 2343 |
536894915U, // CINS |
2343 |
536894915U, // CINS |
| 2344 |
536887582U, // CINS32 |
2344 |
536887582U, // CINS32 |
| 2345 |
536894915U, // CINS64_32 |
2345 |
536894915U, // CINS64_32 |
| 2346 |
536894915U, // CINS_i32 |
2346 |
536894915U, // CINS_i32 |
| 2347 |
19880U, // CLASS_D |
2347 |
19880U, // CLASS_D |
| 2348 |
19880U, // CLASS_D_MMR6 |
2348 |
19880U, // CLASS_D_MMR6 |
| 2349 |
23760U, // CLASS_S |
2349 |
23760U, // CLASS_S |
| 2350 |
23760U, // CLASS_S_MMR6 |
2350 |
23760U, // CLASS_S_MMR6 |
| 2351 |
536888458U, // CLEI_S_B |
2351 |
536888458U, // CLEI_S_B |
| 2352 |
536890615U, // CLEI_S_D |
2352 |
536890615U, // CLEI_S_D |
| 2353 |
536892164U, // CLEI_S_H |
2353 |
536892164U, // CLEI_S_H |
| 2354 |
536896429U, // CLEI_S_W |
2354 |
536896429U, // CLEI_S_W |
| 2355 |
536888673U, // CLEI_U_B |
2355 |
536888673U, // CLEI_U_B |
| 2356 |
536891082U, // CLEI_U_D |
2356 |
536891082U, // CLEI_U_D |
| 2357 |
536892452U, // CLEI_U_H |
2357 |
536892452U, // CLEI_U_H |
| 2358 |
536896897U, // CLEI_U_W |
2358 |
536896897U, // CLEI_U_W |
| 2359 |
536888440U, // CLE_S_B |
2359 |
536888440U, // CLE_S_B |
| 2360 |
536890597U, // CLE_S_D |
2360 |
536890597U, // CLE_S_D |
| 2361 |
536892146U, // CLE_S_H |
2361 |
536892146U, // CLE_S_H |
| 2362 |
536896411U, // CLE_S_W |
2362 |
536896411U, // CLE_S_W |
| 2363 |
536888655U, // CLE_U_B |
2363 |
536888655U, // CLE_U_B |
| 2364 |
536891064U, // CLE_U_D |
2364 |
536891064U, // CLE_U_D |
| 2365 |
536892434U, // CLE_U_H |
2365 |
536892434U, // CLE_U_H |
| 2366 |
536896879U, // CLE_U_W |
2366 |
536896879U, // CLE_U_W |
| 2367 |
22913U, // CLO |
2367 |
22913U, // CLO |
| 2368 |
22913U, // CLO_MM |
2368 |
22913U, // CLO_MM |
| 2369 |
22913U, // CLO_MMR6 |
2369 |
22913U, // CLO_MMR6 |
| 2370 |
22913U, // CLO_R6 |
2370 |
22913U, // CLO_R6 |
| 2371 |
536888478U, // CLTI_S_B |
2371 |
536888478U, // CLTI_S_B |
| 2372 |
536890635U, // CLTI_S_D |
2372 |
536890635U, // CLTI_S_D |
| 2373 |
536892184U, // CLTI_S_H |
2373 |
536892184U, // CLTI_S_H |
| 2374 |
536896449U, // CLTI_S_W |
2374 |
536896449U, // CLTI_S_W |
| 2375 |
536888693U, // CLTI_U_B |
2375 |
536888693U, // CLTI_U_B |
| 2376 |
536891102U, // CLTI_U_D |
2376 |
536891102U, // CLTI_U_D |
| 2377 |
536892472U, // CLTI_U_H |
2377 |
536892472U, // CLTI_U_H |
| 2378 |
536896917U, // CLTI_U_W |
2378 |
536896917U, // CLTI_U_W |
| 2379 |
536888546U, // CLT_S_B |
2379 |
536888546U, // CLT_S_B |
| 2380 |
536890713U, // CLT_S_D |
2380 |
536890713U, // CLT_S_D |
| 2381 |
536892272U, // CLT_S_H |
2381 |
536892272U, // CLT_S_H |
| 2382 |
536896577U, // CLT_S_W |
2382 |
536896577U, // CLT_S_W |
| 2383 |
536888773U, // CLT_U_B |
2383 |
536888773U, // CLT_U_B |
| 2384 |
536891192U, // CLT_U_D |
2384 |
536891192U, // CLT_U_D |
| 2385 |
536892562U, // CLT_U_H |
2385 |
536892562U, // CLT_U_H |
| 2386 |
536897007U, // CLT_U_W |
2386 |
536897007U, // CLT_U_W |
| 2387 |
26337U, // CLZ |
2387 |
26337U, // CLZ |
| 2388 |
26337U, // CLZ_MM |
2388 |
26337U, // CLZ_MM |
| 2389 |
26337U, // CLZ_MMR6 |
2389 |
26337U, // CLZ_MMR6 |
| 2390 |
26337U, // CLZ_R6 |
2390 |
26337U, // CLZ_R6 |
| 2391 |
536889023U, // CMPGDU_EQ_QB |
2391 |
536889023U, // CMPGDU_EQ_QB |
| 2392 |
536889023U, // CMPGDU_EQ_QB_MMR2 |
2392 |
536889023U, // CMPGDU_EQ_QB_MMR2 |
| 2393 |
536888928U, // CMPGDU_LE_QB |
2393 |
536888928U, // CMPGDU_LE_QB |
| 2394 |
536888928U, // CMPGDU_LE_QB_MMR2 |
2394 |
536888928U, // CMPGDU_LE_QB_MMR2 |
| 2395 |
536889142U, // CMPGDU_LT_QB |
2395 |
536889142U, // CMPGDU_LT_QB |
| 2396 |
536889142U, // CMPGDU_LT_QB_MMR2 |
2396 |
536889142U, // CMPGDU_LT_QB_MMR2 |
| 2397 |
536889037U, // CMPGU_EQ_QB |
2397 |
536889037U, // CMPGU_EQ_QB |
| 2398 |
536889037U, // CMPGU_EQ_QB_MM |
2398 |
536889037U, // CMPGU_EQ_QB_MM |
| 2399 |
536888942U, // CMPGU_LE_QB |
2399 |
536888942U, // CMPGU_LE_QB |
| 2400 |
536888942U, // CMPGU_LE_QB_MM |
2400 |
536888942U, // CMPGU_LE_QB_MM |
| 2401 |
536889156U, // CMPGU_LT_QB |
2401 |
536889156U, // CMPGU_LT_QB |
| 2402 |
536889156U, // CMPGU_LT_QB_MM |
2402 |
536889156U, // CMPGU_LT_QB_MM |
| 2403 |
18138U, // CMPU_EQ_QB |
2403 |
18138U, // CMPU_EQ_QB |
| 2404 |
18138U, // CMPU_EQ_QB_MM |
2404 |
18138U, // CMPU_EQ_QB_MM |
| 2405 |
18043U, // CMPU_LE_QB |
2405 |
18043U, // CMPU_LE_QB |
| 2406 |
18043U, // CMPU_LE_QB_MM |
2406 |
18043U, // CMPU_LE_QB_MM |
| 2407 |
18257U, // CMPU_LT_QB |
2407 |
18257U, // CMPU_LT_QB |
| 2408 |
18257U, // CMPU_LT_QB_MM |
2408 |
18257U, // CMPU_LT_QB_MM |
| 2409 |
536889905U, // CMP_AF_D_MMR6 |
2409 |
536889905U, // CMP_AF_D_MMR6 |
| 2410 |
536894389U, // CMP_AF_S_MMR6 |
2410 |
536894389U, // CMP_AF_S_MMR6 |
| 2411 |
536890344U, // CMP_EQ_D |
2411 |
536890344U, // CMP_EQ_D |
| 2412 |
536890344U, // CMP_EQ_D_MMR6 |
2412 |
536890344U, // CMP_EQ_D_MMR6 |
| 2413 |
21940U, // CMP_EQ_PH |
2413 |
21940U, // CMP_EQ_PH |
| 2414 |
21940U, // CMP_EQ_PH_MM |
2414 |
21940U, // CMP_EQ_PH_MM |
| 2415 |
536894593U, // CMP_EQ_S |
2415 |
536894593U, // CMP_EQ_S |
| 2416 |
536894593U, // CMP_EQ_S_MMR6 |
2416 |
536894593U, // CMP_EQ_S_MMR6 |
| 2417 |
536889905U, // CMP_F_D |
2417 |
536889905U, // CMP_F_D |
| 2418 |
536894389U, // CMP_F_S |
2418 |
536894389U, // CMP_F_S |
| 2419 |
536889749U, // CMP_LE_D |
2419 |
536889749U, // CMP_LE_D |
| 2420 |
536889749U, // CMP_LE_D_MMR6 |
2420 |
536889749U, // CMP_LE_D_MMR6 |
| 2421 |
21836U, // CMP_LE_PH |
2421 |
21836U, // CMP_LE_PH |
| 2422 |
21836U, // CMP_LE_PH_MM |
2422 |
21836U, // CMP_LE_PH_MM |
| 2423 |
536894310U, // CMP_LE_S |
2423 |
536894310U, // CMP_LE_S |
| 2424 |
536894310U, // CMP_LE_S_MMR6 |
2424 |
536894310U, // CMP_LE_S_MMR6 |
| 2425 |
536890835U, // CMP_LT_D |
2425 |
536890835U, // CMP_LT_D |
| 2426 |
536890835U, // CMP_LT_D_MMR6 |
2426 |
536890835U, // CMP_LT_D_MMR6 |
| 2427 |
22109U, // CMP_LT_PH |
2427 |
22109U, // CMP_LT_PH |
| 2428 |
22109U, // CMP_LT_PH_MM |
2428 |
22109U, // CMP_LT_PH_MM |
| 2429 |
536894698U, // CMP_LT_S |
2429 |
536894698U, // CMP_LT_S |
| 2430 |
536894698U, // CMP_LT_S_MMR6 |
2430 |
536894698U, // CMP_LT_S_MMR6 |
| 2431 |
536889923U, // CMP_SAF_D |
2431 |
536889923U, // CMP_SAF_D |
| 2432 |
536889923U, // CMP_SAF_D_MMR6 |
2432 |
536889923U, // CMP_SAF_D_MMR6 |
| 2433 |
536894399U, // CMP_SAF_S |
2433 |
536894399U, // CMP_SAF_S |
| 2434 |
536894399U, // CMP_SAF_S_MMR6 |
2434 |
536894399U, // CMP_SAF_S_MMR6 |
| 2435 |
536890371U, // CMP_SEQ_D |
2435 |
536890371U, // CMP_SEQ_D |
| 2436 |
536890371U, // CMP_SEQ_D_MMR6 |
2436 |
536890371U, // CMP_SEQ_D_MMR6 |
| 2437 |
536894612U, // CMP_SEQ_S |
2437 |
536894612U, // CMP_SEQ_S |
| 2438 |
536894612U, // CMP_SEQ_S_MMR6 |
2438 |
536894612U, // CMP_SEQ_S_MMR6 |
| 2439 |
536889786U, // CMP_SLE_D |
2439 |
536889786U, // CMP_SLE_D |
| 2440 |
536889786U, // CMP_SLE_D_MMR6 |
2440 |
536889786U, // CMP_SLE_D_MMR6 |
| 2441 |
536894339U, // CMP_SLE_S |
2441 |
536894339U, // CMP_SLE_S |
| 2442 |
536894339U, // CMP_SLE_S_MMR6 |
2442 |
536894339U, // CMP_SLE_S_MMR6 |
| 2443 |
536890862U, // CMP_SLT_D |
2443 |
536890862U, // CMP_SLT_D |
| 2444 |
536890862U, // CMP_SLT_D_MMR6 |
2444 |
536890862U, // CMP_SLT_D_MMR6 |
| 2445 |
536894717U, // CMP_SLT_S |
2445 |
536894717U, // CMP_SLT_S |
| 2446 |
536894717U, // CMP_SLT_S_MMR6 |
2446 |
536894717U, // CMP_SLT_S_MMR6 |
| 2447 |
536890419U, // CMP_SUEQ_D |
2447 |
536890419U, // CMP_SUEQ_D |
| 2448 |
536890419U, // CMP_SUEQ_D_MMR6 |
2448 |
536890419U, // CMP_SUEQ_D_MMR6 |
| 2449 |
536894643U, // CMP_SUEQ_S |
2449 |
536894643U, // CMP_SUEQ_S |
| 2450 |
536894643U, // CMP_SUEQ_S_MMR6 |
2450 |
536894643U, // CMP_SUEQ_S_MMR6 |
| 2451 |
536889834U, // CMP_SULE_D |
2451 |
536889834U, // CMP_SULE_D |
| 2452 |
536889834U, // CMP_SULE_D_MMR6 |
2452 |
536889834U, // CMP_SULE_D_MMR6 |
| 2453 |
536894370U, // CMP_SULE_S |
2453 |
536894370U, // CMP_SULE_S |
| 2454 |
536894370U, // CMP_SULE_S_MMR6 |
2454 |
536894370U, // CMP_SULE_S_MMR6 |
| 2455 |
536890910U, // CMP_SULT_D |
2455 |
536890910U, // CMP_SULT_D |
| 2456 |
536890910U, // CMP_SULT_D_MMR6 |
2456 |
536890910U, // CMP_SULT_D_MMR6 |
| 2457 |
536894748U, // CMP_SULT_S |
2457 |
536894748U, // CMP_SULT_S |
| 2458 |
536894748U, // CMP_SULT_S_MMR6 |
2458 |
536894748U, // CMP_SULT_S_MMR6 |
| 2459 |
536890292U, // CMP_SUN_D |
2459 |
536890292U, // CMP_SUN_D |
| 2460 |
536890292U, // CMP_SUN_D_MMR6 |
2460 |
536890292U, // CMP_SUN_D_MMR6 |
| 2461 |
536894557U, // CMP_SUN_S |
2461 |
536894557U, // CMP_SUN_S |
| 2462 |
536894557U, // CMP_SUN_S_MMR6 |
2462 |
536894557U, // CMP_SUN_S_MMR6 |
| 2463 |
536890399U, // CMP_UEQ_D |
2463 |
536890399U, // CMP_UEQ_D |
| 2464 |
536890399U, // CMP_UEQ_D_MMR6 |
2464 |
536890399U, // CMP_UEQ_D_MMR6 |
| 2465 |
536894632U, // CMP_UEQ_S |
2465 |
536894632U, // CMP_UEQ_S |
| 2466 |
536894632U, // CMP_UEQ_S_MMR6 |
2466 |
536894632U, // CMP_UEQ_S_MMR6 |
| 2467 |
536889814U, // CMP_ULE_D |
2467 |
536889814U, // CMP_ULE_D |
| 2468 |
536889814U, // CMP_ULE_D_MMR6 |
2468 |
536889814U, // CMP_ULE_D_MMR6 |
| 2469 |
536894359U, // CMP_ULE_S |
2469 |
536894359U, // CMP_ULE_S |
| 2470 |
536894359U, // CMP_ULE_S_MMR6 |
2470 |
536894359U, // CMP_ULE_S_MMR6 |
| 2471 |
536890890U, // CMP_ULT_D |
2471 |
536890890U, // CMP_ULT_D |
| 2472 |
536890890U, // CMP_ULT_D_MMR6 |
2472 |
536890890U, // CMP_ULT_D_MMR6 |
| 2473 |
536894737U, // CMP_ULT_S |
2473 |
536894737U, // CMP_ULT_S |
| 2474 |
536894737U, // CMP_ULT_S_MMR6 |
2474 |
536894737U, // CMP_ULT_S_MMR6 |
| 2475 |
536890274U, // CMP_UN_D |
2475 |
536890274U, // CMP_UN_D |
| 2476 |
536890274U, // CMP_UN_D_MMR6 |
2476 |
536890274U, // CMP_UN_D_MMR6 |
| 2477 |
536894547U, // CMP_UN_S |
2477 |
536894547U, // CMP_UN_S |
| 2478 |
536894547U, // CMP_UN_S_MMR6 |
2478 |
536894547U, // CMP_UN_S_MMR6 |
| 2479 |
1073759497U, // COPY_S_B |
2479 |
1073759497U, // COPY_S_B |
| 2480 |
1073761686U, // COPY_S_D |
2480 |
1073761686U, // COPY_S_D |
| 2481 |
1073763234U, // COPY_S_H |
2481 |
1073763234U, // COPY_S_H |
| 2482 |
1073767561U, // COPY_S_W |
2482 |
1073767561U, // COPY_S_W |
| 2483 |
1073759712U, // COPY_U_B |
2483 |
1073759712U, // COPY_U_B |
| 2484 |
1073763501U, // COPY_U_H |
2484 |
1073763501U, // COPY_U_H |
| 2485 |
1073767968U, // COPY_U_W |
2485 |
1073767968U, // COPY_U_W |
| 2486 |
536888867U, // CRC32B |
2486 |
536888867U, // CRC32B |
| 2487 |
536888875U, // CRC32CB |
2487 |
536888875U, // CRC32CB |
| 2488 |
536891415U, // CRC32CD |
2488 |
536891415U, // CRC32CD |
| 2489 |
536892676U, // CRC32CH |
2489 |
536892676U, // CRC32CH |
| 2490 |
536897156U, // CRC32CW |
2490 |
536897156U, // CRC32CW |
| 2491 |
536891401U, // CRC32D |
2491 |
536891401U, // CRC32D |
| 2492 |
536892656U, // CRC32H |
2492 |
536892656U, // CRC32H |
| 2493 |
536897148U, // CRC32W |
2493 |
536897148U, // CRC32W |
| 2494 |
17875069U, // CTC1 |
2494 |
17875069U, // CTC1 |
| 2495 |
17875069U, // CTC1_MM |
2495 |
17875069U, // CTC1_MM |
| 2496 |
17875285U, // CTC2_MM |
2496 |
17875285U, // CTC2_MM |
| 2497 |
17121U, // CTCMSA |
2497 |
17121U, // CTCMSA |
| 2498 |
23363U, // CVT_D32_S |
2498 |
23363U, // CVT_D32_S |
| 2499 |
23363U, // CVT_D32_S_MM |
2499 |
23363U, // CVT_D32_S_MM |
| 2500 |
24662U, // CVT_D32_W |
2500 |
24662U, // CVT_D32_W |
| 2501 |
24662U, // CVT_D32_W_MM |
2501 |
24662U, // CVT_D32_W_MM |
| 2502 |
22493U, // CVT_D64_L |
2502 |
22493U, // CVT_D64_L |
| 2503 |
23363U, // CVT_D64_S |
2503 |
23363U, // CVT_D64_S |
| 2504 |
23363U, // CVT_D64_S_MM |
2504 |
23363U, // CVT_D64_S_MM |
| 2505 |
24662U, // CVT_D64_W |
2505 |
24662U, // CVT_D64_W |
| 2506 |
24662U, // CVT_D64_W_MM |
2506 |
24662U, // CVT_D64_W_MM |
| 2507 |
22493U, // CVT_D_L_MMR6 |
2507 |
22493U, // CVT_D_L_MMR6 |
| 2508 |
19256U, // CVT_L_D64 |
2508 |
19256U, // CVT_L_D64 |
| 2509 |
19256U, // CVT_L_D64_MM |
2509 |
19256U, // CVT_L_D64_MM |
| 2510 |
19256U, // CVT_L_D_MMR6 |
2510 |
19256U, // CVT_L_D_MMR6 |
| 2511 |
23588U, // CVT_L_S |
2511 |
23588U, // CVT_L_S |
| 2512 |
23588U, // CVT_L_S_MM |
2512 |
23588U, // CVT_L_S_MM |
| 2513 |
23588U, // CVT_L_S_MMR6 |
2513 |
23588U, // CVT_L_S_MMR6 |
| 2514 |
26258U, // CVT_PS_PW64 |
2514 |
26258U, // CVT_PS_PW64 |
| 2515 |
536894662U, // CVT_PS_S64 |
2515 |
536894662U, // CVT_PS_S64 |
| 2516 |
24089U, // CVT_PW_PS64 |
2516 |
24089U, // CVT_PW_PS64 |
| 2517 |
19603U, // CVT_S_D32 |
2517 |
19603U, // CVT_S_D32 |
| 2518 |
19603U, // CVT_S_D32_MM |
2518 |
19603U, // CVT_S_D32_MM |
| 2519 |
19603U, // CVT_S_D64 |
2519 |
19603U, // CVT_S_D64 |
| 2520 |
19603U, // CVT_S_D64_MM |
2520 |
19603U, // CVT_S_D64_MM |
| 2521 |
22502U, // CVT_S_L |
2521 |
22502U, // CVT_S_L |
| 2522 |
22502U, // CVT_S_L_MMR6 |
2522 |
22502U, // CVT_S_L_MMR6 |
| 2523 |
22747U, // CVT_S_PL64 |
2523 |
22747U, // CVT_S_PL64 |
| 2524 |
24353U, // CVT_S_PU64 |
2524 |
24353U, // CVT_S_PU64 |
| 2525 |
25417U, // CVT_S_W |
2525 |
25417U, // CVT_S_W |
| 2526 |
25417U, // CVT_S_W_MM |
2526 |
25417U, // CVT_S_W_MM |
| 2527 |
25417U, // CVT_S_W_MMR6 |
2527 |
25417U, // CVT_S_W_MMR6 |
| 2528 |
20431U, // CVT_W_D32 |
2528 |
20431U, // CVT_W_D32 |
| 2529 |
20431U, // CVT_W_D32_MM |
2529 |
20431U, // CVT_W_D32_MM |
| 2530 |
20431U, // CVT_W_D64 |
2530 |
20431U, // CVT_W_D64 |
| 2531 |
20431U, // CVT_W_D64_MM |
2531 |
20431U, // CVT_W_D64_MM |
| 2532 |
23930U, // CVT_W_S |
2532 |
23930U, // CVT_W_S |
| 2533 |
23930U, // CVT_W_S_MM |
2533 |
23930U, // CVT_W_S_MM |
| 2534 |
23930U, // CVT_W_S_MMR6 |
2534 |
23930U, // CVT_W_S_MMR6 |
| 2535 |
536890336U, // C_EQ_D32 |
2535 |
536890336U, // C_EQ_D32 |
| 2536 |
536890336U, // C_EQ_D32_MM |
2536 |
536890336U, // C_EQ_D32_MM |
| 2537 |
536890336U, // C_EQ_D64 |
2537 |
536890336U, // C_EQ_D64 |
| 2538 |
536890336U, // C_EQ_D64_MM |
2538 |
536890336U, // C_EQ_D64_MM |
| 2539 |
536894585U, // C_EQ_S |
2539 |
536894585U, // C_EQ_S |
| 2540 |
536894585U, // C_EQ_S_MM |
2540 |
536894585U, // C_EQ_S_MM |
| 2541 |
536889898U, // C_F_D32 |
2541 |
536889898U, // C_F_D32 |
| 2542 |
536889898U, // C_F_D32_MM |
2542 |
536889898U, // C_F_D32_MM |
| 2543 |
536889898U, // C_F_D64 |
2543 |
536889898U, // C_F_D64 |
| 2544 |
536889898U, // C_F_D64_MM |
2544 |
536889898U, // C_F_D64_MM |
| 2545 |
536894382U, // C_F_S |
2545 |
536894382U, // C_F_S |
| 2546 |
536894382U, // C_F_S_MM |
2546 |
536894382U, // C_F_S_MM |
| 2547 |
536889741U, // C_LE_D32 |
2547 |
536889741U, // C_LE_D32 |
| 2548 |
536889741U, // C_LE_D32_MM |
2548 |
536889741U, // C_LE_D32_MM |
| 2549 |
536889741U, // C_LE_D64 |
2549 |
536889741U, // C_LE_D64 |
| 2550 |
536889741U, // C_LE_D64_MM |
2550 |
536889741U, // C_LE_D64_MM |
| 2551 |
536894302U, // C_LE_S |
2551 |
536894302U, // C_LE_S |
| 2552 |
536894302U, // C_LE_S_MM |
2552 |
536894302U, // C_LE_S_MM |
| 2553 |
536890827U, // C_LT_D32 |
2553 |
536890827U, // C_LT_D32 |
| 2554 |
536890827U, // C_LT_D32_MM |
2554 |
536890827U, // C_LT_D32_MM |
| 2555 |
536890827U, // C_LT_D64 |
2555 |
536890827U, // C_LT_D64 |
| 2556 |
536890827U, // C_LT_D64_MM |
2556 |
536890827U, // C_LT_D64_MM |
| 2557 |
536894690U, // C_LT_S |
2557 |
536894690U, // C_LT_S |
| 2558 |
536894690U, // C_LT_S_MM |
2558 |
536894690U, // C_LT_S_MM |
| 2559 |
536889732U, // C_NGE_D32 |
2559 |
536889732U, // C_NGE_D32 |
| 2560 |
536889732U, // C_NGE_D32_MM |
2560 |
536889732U, // C_NGE_D32_MM |
| 2561 |
536889732U, // C_NGE_D64 |
2561 |
536889732U, // C_NGE_D64 |
| 2562 |
536889732U, // C_NGE_D64_MM |
2562 |
536889732U, // C_NGE_D64_MM |
| 2563 |
536894293U, // C_NGE_S |
2563 |
536894293U, // C_NGE_S |
| 2564 |
536894293U, // C_NGE_S_MM |
2564 |
536894293U, // C_NGE_S_MM |
| 2565 |
536889767U, // C_NGLE_D32 |
2565 |
536889767U, // C_NGLE_D32 |
| 2566 |
536889767U, // C_NGLE_D32_MM |
2566 |
536889767U, // C_NGLE_D32_MM |
| 2567 |
536889767U, // C_NGLE_D64 |
2567 |
536889767U, // C_NGLE_D64 |
| 2568 |
536889767U, // C_NGLE_D64_MM |
2568 |
536889767U, // C_NGLE_D64_MM |
| 2569 |
536894320U, // C_NGLE_S |
2569 |
536894320U, // C_NGLE_S |
| 2570 |
536894320U, // C_NGLE_S_MM |
2570 |
536894320U, // C_NGLE_S_MM |
| 2571 |
536890184U, // C_NGL_D32 |
2571 |
536890184U, // C_NGL_D32 |
| 2572 |
536890184U, // C_NGL_D32_MM |
2572 |
536890184U, // C_NGL_D32_MM |
| 2573 |
536890184U, // C_NGL_D64 |
2573 |
536890184U, // C_NGL_D64 |
| 2574 |
536890184U, // C_NGL_D64_MM |
2574 |
536890184U, // C_NGL_D64_MM |
| 2575 |
536894516U, // C_NGL_S |
2575 |
536894516U, // C_NGL_S |
| 2576 |
536894516U, // C_NGL_S_MM |
2576 |
536894516U, // C_NGL_S_MM |
| 2577 |
536890818U, // C_NGT_D32 |
2577 |
536890818U, // C_NGT_D32 |
| 2578 |
536890818U, // C_NGT_D32_MM |
2578 |
536890818U, // C_NGT_D32_MM |
| 2579 |
536890818U, // C_NGT_D64 |
2579 |
536890818U, // C_NGT_D64 |
| 2580 |
536890818U, // C_NGT_D64_MM |
2580 |
536890818U, // C_NGT_D64_MM |
| 2581 |
536894681U, // C_NGT_S |
2581 |
536894681U, // C_NGT_S |
| 2582 |
536894681U, // C_NGT_S_MM |
2582 |
536894681U, // C_NGT_S_MM |
| 2583 |
536889777U, // C_OLE_D32 |
2583 |
536889777U, // C_OLE_D32 |
| 2584 |
536889777U, // C_OLE_D32_MM |
2584 |
536889777U, // C_OLE_D32_MM |
| 2585 |
536889777U, // C_OLE_D64 |
2585 |
536889777U, // C_OLE_D64 |
| 2586 |
536889777U, // C_OLE_D64_MM |
2586 |
536889777U, // C_OLE_D64_MM |
| 2587 |
536894330U, // C_OLE_S |
2587 |
536894330U, // C_OLE_S |
| 2588 |
536894330U, // C_OLE_S_MM |
2588 |
536894330U, // C_OLE_S_MM |
| 2589 |
536890853U, // C_OLT_D32 |
2589 |
536890853U, // C_OLT_D32 |
| 2590 |
536890853U, // C_OLT_D32_MM |
2590 |
536890853U, // C_OLT_D32_MM |
| 2591 |
536890853U, // C_OLT_D64 |
2591 |
536890853U, // C_OLT_D64 |
| 2592 |
536890853U, // C_OLT_D64_MM |
2592 |
536890853U, // C_OLT_D64_MM |
| 2593 |
536894708U, // C_OLT_S |
2593 |
536894708U, // C_OLT_S |
| 2594 |
536894708U, // C_OLT_S_MM |
2594 |
536894708U, // C_OLT_S_MM |
| 2595 |
536890362U, // C_SEQ_D32 |
2595 |
536890362U, // C_SEQ_D32 |
| 2596 |
536890362U, // C_SEQ_D32_MM |
2596 |
536890362U, // C_SEQ_D32_MM |
| 2597 |
536890362U, // C_SEQ_D64 |
2597 |
536890362U, // C_SEQ_D64 |
| 2598 |
536890362U, // C_SEQ_D64_MM |
2598 |
536890362U, // C_SEQ_D64_MM |
| 2599 |
536894603U, // C_SEQ_S |
2599 |
536894603U, // C_SEQ_S |
| 2600 |
536894603U, // C_SEQ_S_MM |
2600 |
536894603U, // C_SEQ_S_MM |
| 2601 |
536889968U, // C_SF_D32 |
2601 |
536889968U, // C_SF_D32 |
| 2602 |
536889968U, // C_SF_D32_MM |
2602 |
536889968U, // C_SF_D32_MM |
| 2603 |
536889968U, // C_SF_D64 |
2603 |
536889968U, // C_SF_D64 |
| 2604 |
536889968U, // C_SF_D64_MM |
2604 |
536889968U, // C_SF_D64_MM |
| 2605 |
536894428U, // C_SF_S |
2605 |
536894428U, // C_SF_S |
| 2606 |
536894428U, // C_SF_S_MM |
2606 |
536894428U, // C_SF_S_MM |
| 2607 |
536890390U, // C_UEQ_D32 |
2607 |
536890390U, // C_UEQ_D32 |
| 2608 |
536890390U, // C_UEQ_D32_MM |
2608 |
536890390U, // C_UEQ_D32_MM |
| 2609 |
536890390U, // C_UEQ_D64 |
2609 |
536890390U, // C_UEQ_D64 |
| 2610 |
536890390U, // C_UEQ_D64_MM |
2610 |
536890390U, // C_UEQ_D64_MM |
| 2611 |
536894623U, // C_UEQ_S |
2611 |
536894623U, // C_UEQ_S |
| 2612 |
536894623U, // C_UEQ_S_MM |
2612 |
536894623U, // C_UEQ_S_MM |
| 2613 |
536889805U, // C_ULE_D32 |
2613 |
536889805U, // C_ULE_D32 |
| 2614 |
536889805U, // C_ULE_D32_MM |
2614 |
536889805U, // C_ULE_D32_MM |
| 2615 |
536889805U, // C_ULE_D64 |
2615 |
536889805U, // C_ULE_D64 |
| 2616 |
536889805U, // C_ULE_D64_MM |
2616 |
536889805U, // C_ULE_D64_MM |
| 2617 |
536894350U, // C_ULE_S |
2617 |
536894350U, // C_ULE_S |
| 2618 |
536894350U, // C_ULE_S_MM |
2618 |
536894350U, // C_ULE_S_MM |
| 2619 |
536890881U, // C_ULT_D32 |
2619 |
536890881U, // C_ULT_D32 |
| 2620 |
536890881U, // C_ULT_D32_MM |
2620 |
536890881U, // C_ULT_D32_MM |
| 2621 |
536890881U, // C_ULT_D64 |
2621 |
536890881U, // C_ULT_D64 |
| 2622 |
536890881U, // C_ULT_D64_MM |
2622 |
536890881U, // C_ULT_D64_MM |
| 2623 |
536894728U, // C_ULT_S |
2623 |
536894728U, // C_ULT_S |
| 2624 |
536894728U, // C_ULT_S_MM |
2624 |
536894728U, // C_ULT_S_MM |
| 2625 |
536890266U, // C_UN_D32 |
2625 |
536890266U, // C_UN_D32 |
| 2626 |
536890266U, // C_UN_D32_MM |
2626 |
536890266U, // C_UN_D32_MM |
| 2627 |
536890266U, // C_UN_D64 |
2627 |
536890266U, // C_UN_D64 |
| 2628 |
536890266U, // C_UN_D64_MM |
2628 |
536890266U, // C_UN_D64_MM |
| 2629 |
536894539U, // C_UN_S |
2629 |
536894539U, // C_UN_S |
| 2630 |
536894539U, // C_UN_S_MM |
2630 |
536894539U, // C_UN_S_MM |
| 2631 |
22984U, // CmpRxRy16 |
2631 |
22984U, // CmpRxRy16 |
| 2632 |
1610635153U, // CmpiRxImm16 |
2632 |
1610635153U, // CmpiRxImm16 |
| 2633 |
22417U, // CmpiRxImmX16 |
2633 |
22417U, // CmpiRxImmX16 |
| 2634 |
536891429U, // DADD |
2634 |
536891429U, // DADD |
| 2635 |
536893261U, // DADDi |
2635 |
536893261U, // DADDi |
| 2636 |
536895199U, // DADDiu |
2636 |
536895199U, // DADDiu |
| 2637 |
536895135U, // DADDu |
2637 |
536895135U, // DADDu |
| 2638 |
536893292U, // DAHI |
2638 |
536893292U, // DAHI |
| 2639 |
536893810U, // DALIGN |
2639 |
536893810U, // DALIGN |
| 2640 |
536893353U, // DATI |
2640 |
536893353U, // DATI |
| 2641 |
536893371U, // DAUI |
2641 |
536893371U, // DAUI |
| 2642 |
22944U, // DBITSWAP |
2642 |
22944U, // DBITSWAP |
| 2643 |
22912U, // DCLO |
2643 |
22912U, // DCLO |
| 2644 |
22912U, // DCLO_R6 |
2644 |
22912U, // DCLO_R6 |
| 2645 |
26336U, // DCLZ |
2645 |
26336U, // DCLZ |
| 2646 |
26336U, // DCLZ_R6 |
2646 |
26336U, // DCLZ_R6 |
| 2647 |
536895419U, // DDIV |
2647 |
536895419U, // DDIV |
| 2648 |
536895327U, // DDIVU |
2648 |
536895327U, // DDIVU |
| 2649 |
10637U, // DERET |
2649 |
10637U, // DERET |
| 2650 |
10637U, // DERET_MM |
2650 |
10637U, // DERET_MM |
| 2651 |
10637U, // DERET_MMR6 |
2651 |
10637U, // DERET_MMR6 |
| 2652 |
536895103U, // DEXT |
2652 |
536895103U, // DEXT |
| 2653 |
536897494U, // DEXT64_32 |
2653 |
536897494U, // DEXT64_32 |
| 2654 |
536893785U, // DEXTM |
2654 |
536893785U, // DEXTM |
| 2655 |
536895320U, // DEXTU |
2655 |
536895320U, // DEXTU |
| 2656 |
546640U, // DI |
2656 |
546640U, // DI |
| 2657 |
536894921U, // DINS |
2657 |
536894921U, // DINS |
| 2658 |
536893778U, // DINSM |
2658 |
536893778U, // DINSM |
| 2659 |
536895275U, // DINSU |
2659 |
536895275U, // DINSU |
| 2660 |
536895420U, // DIV |
2660 |
536895420U, // DIV |
| 2661 |
536895328U, // DIVU |
2661 |
536895328U, // DIVU |
| 2662 |
536895328U, // DIVU_MMR6 |
2662 |
536895328U, // DIVU_MMR6 |
| 2663 |
536895420U, // DIV_MMR6 |
2663 |
536895420U, // DIV_MMR6 |
| 2664 |
536888567U, // DIV_S_B |
2664 |
536888567U, // DIV_S_B |
| 2665 |
536890756U, // DIV_S_D |
2665 |
536890756U, // DIV_S_D |
| 2666 |
536892293U, // DIV_S_H |
2666 |
536892293U, // DIV_S_H |
| 2667 |
536896620U, // DIV_S_W |
2667 |
536896620U, // DIV_S_W |
| 2668 |
536888782U, // DIV_U_B |
2668 |
536888782U, // DIV_U_B |
| 2669 |
536891223U, // DIV_U_D |
2669 |
536891223U, // DIV_U_D |
| 2670 |
536892571U, // DIV_U_H |
2670 |
536892571U, // DIV_U_H |
| 2671 |
536897038U, // DIV_U_W |
2671 |
536897038U, // DIV_U_W |
| 2672 |
546640U, // DI_MM |
2672 |
546640U, // DI_MM |
| 2673 |
546640U, // DI_MMR6 |
2673 |
546640U, // DI_MMR6 |
| 2674 |
536888019U, // DLSA |
2674 |
536888019U, // DLSA |
| 2675 |
536888019U, // DLSA_R6 |
2675 |
536888019U, // DLSA_R6 |
| 2676 |
536887297U, // DMFC0 |
2676 |
536887297U, // DMFC0 |
| 2677 |
16488U, // DMFC1 |
2677 |
16488U, // DMFC1 |
| 2678 |
536887616U, // DMFC2 |
2678 |
536887616U, // DMFC2 |
| 2679 |
201343296U, // DMFC2_OCTEON |
2679 |
201343296U, // DMFC2_OCTEON |
| 2680 |
536887304U, // DMFGC0 |
2680 |
536887304U, // DMFGC0 |
| 2681 |
536891481U, // DMOD |
2681 |
536891481U, // DMOD |
| 2682 |
536895149U, // DMODU |
2682 |
536895149U, // DMODU |
| 2683 |
548451U, // DMT |
2683 |
548451U, // DMT |
| 2684 |
2752561206U, // DMTC0 |
2684 |
2752561206U, // DMTC0 |
| 2685 |
17875075U, // DMTC1 |
2685 |
17875075U, // DMTC1 |
| 2686 |
2752561499U, // DMTC2 |
2686 |
2752561499U, // DMTC2 |
| 2687 |
201343323U, // DMTC2_OCTEON |
2687 |
201343323U, // DMTC2_OCTEON |
| 2688 |
2752561184U, // DMTGC0 |
2688 |
2752561184U, // DMTGC0 |
| 2689 |
536893248U, // DMUH |
2689 |
536893248U, // DMUH |
| 2690 |
536895192U, // DMUHU |
2690 |
536895192U, // DMUHU |
| 2691 |
536893714U, // DMUL |
2691 |
536893714U, // DMUL |
| 2692 |
24156U, // DMULT |
2692 |
24156U, // DMULT |
| 2693 |
24400U, // DMULTu |
2693 |
24400U, // DMULTu |
| 2694 |
536895236U, // DMULU |
2694 |
536895236U, // DMULU |
| 2695 |
536893714U, // DMUL_R6 |
2695 |
536893714U, // DMUL_R6 |
| 2696 |
536890664U, // DOTP_S_D |
2696 |
536890664U, // DOTP_S_D |
| 2697 |
536892213U, // DOTP_S_H |
2697 |
536892213U, // DOTP_S_H |
| 2698 |
536896488U, // DOTP_S_W |
2698 |
536896488U, // DOTP_S_W |
| 2699 |
536891131U, // DOTP_U_D |
2699 |
536891131U, // DOTP_U_D |
| 2700 |
536892501U, // DOTP_U_H |
2700 |
536892501U, // DOTP_U_H |
| 2701 |
536896946U, // DOTP_U_W |
2701 |
536896946U, // DOTP_U_W |
| 2702 |
570445009U, // DPADD_S_D |
2702 |
570445009U, // DPADD_S_D |
| 2703 |
570446558U, // DPADD_S_H |
2703 |
570446558U, // DPADD_S_H |
| 2704 |
570450823U, // DPADD_S_W |
2704 |
570450823U, // DPADD_S_W |
| 2705 |
570445476U, // DPADD_U_D |
2705 |
570445476U, // DPADD_U_D |
| 2706 |
570446846U, // DPADD_U_H |
2706 |
570446846U, // DPADD_U_H |
| 2707 |
570451291U, // DPADD_U_W |
2707 |
570451291U, // DPADD_U_W |
| 2708 |
536893100U, // DPAQX_SA_W_PH |
2708 |
536893100U, // DPAQX_SA_W_PH |
| 2709 |
536893100U, // DPAQX_SA_W_PH_MMR2 |
2709 |
536893100U, // DPAQX_SA_W_PH_MMR2 |
| 2710 |
536893183U, // DPAQX_S_W_PH |
2710 |
536893183U, // DPAQX_S_W_PH |
| 2711 |
536893183U, // DPAQX_S_W_PH_MMR2 |
2711 |
536893183U, // DPAQX_S_W_PH_MMR2 |
| 2712 |
536895948U, // DPAQ_SA_L_W |
2712 |
536895948U, // DPAQ_SA_L_W |
| 2713 |
536895948U, // DPAQ_SA_L_W_MM |
2713 |
536895948U, // DPAQ_SA_L_W_MM |
| 2714 |
536893142U, // DPAQ_S_W_PH |
2714 |
536893142U, // DPAQ_S_W_PH |
| 2715 |
536893142U, // DPAQ_S_W_PH_MM |
2715 |
536893142U, // DPAQ_S_W_PH_MM |
| 2716 |
536893449U, // DPAU_H_QBL |
2716 |
536893449U, // DPAU_H_QBL |
| 2717 |
536893449U, // DPAU_H_QBL_MM |
2717 |
536893449U, // DPAU_H_QBL_MM |
| 2718 |
536894035U, // DPAU_H_QBR |
2718 |
536894035U, // DPAU_H_QBR |
| 2719 |
536894035U, // DPAU_H_QBR_MM |
2719 |
536894035U, // DPAU_H_QBR_MM |
| 2720 |
536893221U, // DPAX_W_PH |
2720 |
536893221U, // DPAX_W_PH |
| 2721 |
536893221U, // DPAX_W_PH_MMR2 |
2721 |
536893221U, // DPAX_W_PH_MMR2 |
| 2722 |
536893090U, // DPA_W_PH |
2722 |
536893090U, // DPA_W_PH |
| 2723 |
536893090U, // DPA_W_PH_MMR2 |
2723 |
536893090U, // DPA_W_PH_MMR2 |
| 2724 |
22989U, // DPOP |
2724 |
22989U, // DPOP |
| 2725 |
536893115U, // DPSQX_SA_W_PH |
2725 |
536893115U, // DPSQX_SA_W_PH |
| 2726 |
536893115U, // DPSQX_SA_W_PH_MMR2 |
2726 |
536893115U, // DPSQX_SA_W_PH_MMR2 |
| 2727 |
536893197U, // DPSQX_S_W_PH |
2727 |
536893197U, // DPSQX_S_W_PH |
| 2728 |
536893197U, // DPSQX_S_W_PH_MMR2 |
2728 |
536893197U, // DPSQX_S_W_PH_MMR2 |
| 2729 |
536895961U, // DPSQ_SA_L_W |
2729 |
536895961U, // DPSQ_SA_L_W |
| 2730 |
536895961U, // DPSQ_SA_L_W_MM |
2730 |
536895961U, // DPSQ_SA_L_W_MM |
| 2731 |
536893170U, // DPSQ_S_W_PH |
2731 |
536893170U, // DPSQ_S_W_PH |
| 2732 |
536893170U, // DPSQ_S_W_PH_MM |
2732 |
536893170U, // DPSQ_S_W_PH_MM |
| 2733 |
570444976U, // DPSUB_S_D |
2733 |
570444976U, // DPSUB_S_D |
| 2734 |
570446537U, // DPSUB_S_H |
2734 |
570446537U, // DPSUB_S_H |
| 2735 |
570450790U, // DPSUB_S_W |
2735 |
570450790U, // DPSUB_S_W |
| 2736 |
570445443U, // DPSUB_U_D |
2736 |
570445443U, // DPSUB_U_D |
| 2737 |
570446825U, // DPSUB_U_H |
2737 |
570446825U, // DPSUB_U_H |
| 2738 |
570451258U, // DPSUB_U_W |
2738 |
570451258U, // DPSUB_U_W |
| 2739 |
536893461U, // DPSU_H_QBL |
2739 |
536893461U, // DPSU_H_QBL |
| 2740 |
536893461U, // DPSU_H_QBL_MM |
2740 |
536893461U, // DPSU_H_QBL_MM |
| 2741 |
536894047U, // DPSU_H_QBR |
2741 |
536894047U, // DPSU_H_QBR |
| 2742 |
536894047U, // DPSU_H_QBR_MM |
2742 |
536894047U, // DPSU_H_QBR_MM |
| 2743 |
536893232U, // DPSX_W_PH |
2743 |
536893232U, // DPSX_W_PH |
| 2744 |
536893232U, // DPSX_W_PH_MMR2 |
2744 |
536893232U, // DPSX_W_PH_MMR2 |
| 2745 |
536893211U, // DPS_W_PH |
2745 |
536893211U, // DPS_W_PH |
| 2746 |
536893211U, // DPS_W_PH_MMR2 |
2746 |
536893211U, // DPS_W_PH_MMR2 |
| 2747 |
536894220U, // DROTR |
2747 |
536894220U, // DROTR |
| 2748 |
536887573U, // DROTR32 |
2748 |
536887573U, // DROTR32 |
| 2749 |
536895463U, // DROTRV |
2749 |
536895463U, // DROTRV |
| 2750 |
21752U, // DSBH |
2750 |
21752U, // DSBH |
| 2751 |
26407U, // DSDIV |
2751 |
26407U, // DSDIV |
| 2752 |
20529U, // DSHD |
2752 |
20529U, // DSHD |
| 2753 |
536893647U, // DSLL |
2753 |
536893647U, // DSLL |
| 2754 |
536887543U, // DSLL32 |
2754 |
536887543U, // DSLL32 |
| 2755 |
2147506383U, // DSLL64_32 |
2755 |
2147506383U, // DSLL64_32 |
| 2756 |
536895425U, // DSLLV |
2756 |
536895425U, // DSLLV |
| 2757 |
536888013U, // DSRA |
2757 |
536888013U, // DSRA |
| 2758 |
536887525U, // DSRA32 |
2758 |
536887525U, // DSRA32 |
| 2759 |
536895404U, // DSRAV |
2759 |
536895404U, // DSRAV |
| 2760 |
536893675U, // DSRL |
2760 |
536893675U, // DSRL |
| 2761 |
536887551U, // DSRL32 |
2761 |
536887551U, // DSRL32 |
| 2762 |
536895432U, // DSRLV |
2762 |
536895432U, // DSRLV |
| 2763 |
536889257U, // DSUB |
2763 |
536889257U, // DSUB |
| 2764 |
536895114U, // DSUBu |
2764 |
536895114U, // DSUBu |
| 2765 |
26393U, // DUDIV |
2765 |
26393U, // DUDIV |
| 2766 |
547376U, // DVP |
2766 |
547376U, // DVP |
| 2767 |
544979U, // DVPE |
2767 |
544979U, // DVPE |
| 2768 |
547376U, // DVP_MMR6 |
2768 |
547376U, // DVP_MMR6 |
| 2769 |
26408U, // DivRxRy16 |
2769 |
26408U, // DivRxRy16 |
| 2770 |
26394U, // DivuRxRy16 |
2770 |
26394U, // DivuRxRy16 |
| 2771 |
10531U, // EHB |
2771 |
10531U, // EHB |
| 2772 |
10531U, // EHB_MM |
2772 |
10531U, // EHB_MM |
| 2773 |
10531U, // EHB_MMR6 |
2773 |
10531U, // EHB_MMR6 |
| 2774 |
546652U, // EI |
2774 |
546652U, // EI |
| 2775 |
546652U, // EI_MM |
2775 |
546652U, // EI_MM |
| 2776 |
546652U, // EI_MMR6 |
2776 |
546652U, // EI_MMR6 |
| 2777 |
548456U, // EMT |
2777 |
548456U, // EMT |
| 2778 |
10638U, // ERET |
2778 |
10638U, // ERET |
| 2779 |
10535U, // ERETNC |
2779 |
10535U, // ERETNC |
| 2780 |
10535U, // ERETNC_MMR6 |
2780 |
10535U, // ERETNC_MMR6 |
| 2781 |
10638U, // ERET_MM |
2781 |
10638U, // ERET_MM |
| 2782 |
10638U, // ERET_MMR6 |
2782 |
10638U, // ERET_MMR6 |
| 2783 |
547381U, // EVP |
2783 |
547381U, // EVP |
| 2784 |
544985U, // EVPE |
2784 |
544985U, // EVPE |
| 2785 |
547381U, // EVP_MMR6 |
2785 |
547381U, // EVP_MMR6 |
| 2786 |
536895104U, // EXT |
2786 |
536895104U, // EXT |
| 2787 |
536893994U, // EXTP |
2787 |
536893994U, // EXTP |
| 2788 |
536893873U, // EXTPDP |
2788 |
536893873U, // EXTPDP |
| 2789 |
536895447U, // EXTPDPV |
2789 |
536895447U, // EXTPDPV |
| 2790 |
536895447U, // EXTPDPV_MM |
2790 |
536895447U, // EXTPDPV_MM |
| 2791 |
536893873U, // EXTPDP_MM |
2791 |
536893873U, // EXTPDP_MM |
| 2792 |
536895456U, // EXTPV |
2792 |
536895456U, // EXTPV |
| 2793 |
536895456U, // EXTPV_MM |
2793 |
536895456U, // EXTPV_MM |
| 2794 |
536893994U, // EXTP_MM |
2794 |
536893994U, // EXTP_MM |
| 2795 |
536896681U, // EXTRV_RS_W |
2795 |
536896681U, // EXTRV_RS_W |
| 2796 |
536896681U, // EXTRV_RS_W_MM |
2796 |
536896681U, // EXTRV_RS_W_MM |
| 2797 |
536896235U, // EXTRV_R_W |
2797 |
536896235U, // EXTRV_R_W |
| 2798 |
536896235U, // EXTRV_R_W_MM |
2798 |
536896235U, // EXTRV_R_W_MM |
| 2799 |
536892302U, // EXTRV_S_H |
2799 |
536892302U, // EXTRV_S_H |
| 2800 |
536892302U, // EXTRV_S_H_MM |
2800 |
536892302U, // EXTRV_S_H_MM |
| 2801 |
536897118U, // EXTRV_W |
2801 |
536897118U, // EXTRV_W |
| 2802 |
536897118U, // EXTRV_W_MM |
2802 |
536897118U, // EXTRV_W_MM |
| 2803 |
536896670U, // EXTR_RS_W |
2803 |
536896670U, // EXTR_RS_W |
| 2804 |
536896670U, // EXTR_RS_W_MM |
2804 |
536896670U, // EXTR_RS_W_MM |
| 2805 |
536896214U, // EXTR_R_W |
2805 |
536896214U, // EXTR_R_W |
| 2806 |
536896214U, // EXTR_R_W_MM |
2806 |
536896214U, // EXTR_R_W_MM |
| 2807 |
536892233U, // EXTR_S_H |
2807 |
536892233U, // EXTR_S_H |
| 2808 |
536892233U, // EXTR_S_H_MM |
2808 |
536892233U, // EXTR_S_H_MM |
| 2809 |
536896313U, // EXTR_W |
2809 |
536896313U, // EXTR_W |
| 2810 |
536896313U, // EXTR_W_MM |
2810 |
536896313U, // EXTR_W_MM |
| 2811 |
536895019U, // EXTS |
2811 |
536895019U, // EXTS |
| 2812 |
536887590U, // EXTS32 |
2812 |
536887590U, // EXTS32 |
| 2813 |
536895104U, // EXT_MM |
2813 |
536895104U, // EXT_MM |
| 2814 |
536895104U, // EXT_MMR6 |
2814 |
536895104U, // EXT_MMR6 |
| 2815 |
19872U, // FABS_D32 |
2815 |
19872U, // FABS_D32 |
| 2816 |
19872U, // FABS_D32_MM |
2816 |
19872U, // FABS_D32_MM |
| 2817 |
19872U, // FABS_D64 |
2817 |
19872U, // FABS_D64 |
| 2818 |
19872U, // FABS_D64_MM |
2818 |
19872U, // FABS_D64_MM |
| 2819 |
23743U, // FABS_S |
2819 |
23743U, // FABS_S |
| 2820 |
23743U, // FABS_S_MM |
2820 |
23743U, // FABS_S_MM |
| 2821 |
536889681U, // FADD_D |
2821 |
536889681U, // FADD_D |
| 2822 |
536889682U, // FADD_D32 |
2822 |
536889682U, // FADD_D32 |
| 2823 |
536889682U, // FADD_D32_MM |
2823 |
536889682U, // FADD_D32_MM |
| 2824 |
536889682U, // FADD_D64 |
2824 |
536889682U, // FADD_D64 |
| 2825 |
536889682U, // FADD_D64_MM |
2825 |
536889682U, // FADD_D64_MM |
| 2826 |
536894935U, // FADD_PS64 |
2826 |
536894935U, // FADD_PS64 |
| 2827 |
536894286U, // FADD_S |
2827 |
536894286U, // FADD_S |
| 2828 |
536894286U, // FADD_S_MM |
2828 |
536894286U, // FADD_S_MM |
| 2829 |
570448718U, // FADD_S_MMR6 |
2829 |
570448718U, // FADD_S_MMR6 |
| 2830 |
536895583U, // FADD_W |
2830 |
536895583U, // FADD_W |
| 2831 |
536889915U, // FCAF_D |
2831 |
536889915U, // FCAF_D |
| 2832 |
536895702U, // FCAF_W |
2832 |
536895702U, // FCAF_W |
| 2833 |
536890354U, // FCEQ_D |
2833 |
536890354U, // FCEQ_D |
| 2834 |
536896141U, // FCEQ_W |
2834 |
536896141U, // FCEQ_W |
| 2835 |
19879U, // FCLASS_D |
2835 |
19879U, // FCLASS_D |
| 2836 |
25781U, // FCLASS_W |
2836 |
25781U, // FCLASS_W |
| 2837 |
536889759U, // FCLE_D |
2837 |
536889759U, // FCLE_D |
| 2838 |
536895625U, // FCLE_W |
2838 |
536895625U, // FCLE_W |
| 2839 |
536890845U, // FCLT_D |
2839 |
536890845U, // FCLT_D |
| 2840 |
536896720U, // FCLT_W |
2840 |
536896720U, // FCLT_W |
| 2841 |
5941291U, // FCMP_D32 |
2841 |
5941291U, // FCMP_D32 |
| 2842 |
5941291U, // FCMP_D32_MM |
2842 |
5941291U, // FCMP_D32_MM |
| 2843 |
5941291U, // FCMP_D64 |
2843 |
5941291U, // FCMP_D64 |
| 2844 |
6465579U, // FCMP_S32 |
2844 |
6465579U, // FCMP_S32 |
| 2845 |
6465579U, // FCMP_S32_MM |
2845 |
6465579U, // FCMP_S32_MM |
| 2846 |
536889855U, // FCNE_D |
2846 |
536889855U, // FCNE_D |
| 2847 |
536895659U, // FCNE_W |
2847 |
536895659U, // FCNE_W |
| 2848 |
536890464U, // FCOR_D |
2848 |
536890464U, // FCOR_D |
| 2849 |
536896270U, // FCOR_W |
2849 |
536896270U, // FCOR_W |
| 2850 |
536890410U, // FCUEQ_D |
2850 |
536890410U, // FCUEQ_D |
| 2851 |
536896157U, // FCUEQ_W |
2851 |
536896157U, // FCUEQ_W |
| 2852 |
536889825U, // FCULE_D |
2852 |
536889825U, // FCULE_D |
| 2853 |
536895641U, // FCULE_W |
2853 |
536895641U, // FCULE_W |
| 2854 |
536890901U, // FCULT_D |
2854 |
536890901U, // FCULT_D |
| 2855 |
536896736U, // FCULT_W |
2855 |
536896736U, // FCULT_W |
| 2856 |
536889871U, // FCUNE_D |
2856 |
536889871U, // FCUNE_D |
| 2857 |
536895675U, // FCUNE_W |
2857 |
536895675U, // FCUNE_W |
| 2858 |
536890284U, // FCUN_D |
2858 |
536890284U, // FCUN_D |
| 2859 |
536896047U, // FCUN_W |
2859 |
536896047U, // FCUN_W |
| 2860 |
536891277U, // FDIV_D |
2860 |
536891277U, // FDIV_D |
| 2861 |
536891278U, // FDIV_D32 |
2861 |
536891278U, // FDIV_D32 |
| 2862 |
536891278U, // FDIV_D32_MM |
2862 |
536891278U, // FDIV_D32_MM |
| 2863 |
536891278U, // FDIV_D64 |
2863 |
536891278U, // FDIV_D64 |
| 2864 |
536891278U, // FDIV_D64_MM |
2864 |
536891278U, // FDIV_D64_MM |
| 2865 |
536894785U, // FDIV_S |
2865 |
536894785U, // FDIV_S |
| 2866 |
536894785U, // FDIV_S_MM |
2866 |
536894785U, // FDIV_S_MM |
| 2867 |
570449217U, // FDIV_S_MMR6 |
2867 |
570449217U, // FDIV_S_MMR6 |
| 2868 |
536897102U, // FDIV_W |
2868 |
536897102U, // FDIV_W |
| 2869 |
536891960U, // FEXDO_H |
2869 |
536891960U, // FEXDO_H |
| 2870 |
536896063U, // FEXDO_W |
2870 |
536896063U, // FEXDO_W |
| 2871 |
536889568U, // FEXP2_D |
2871 |
536889568U, // FEXP2_D |
| 2872 |
536895486U, // FEXP2_W |
2872 |
536895486U, // FEXP2_W |
| 2873 |
19296U, // FEXUPL_D |
2873 |
19296U, // FEXUPL_D |
| 2874 |
25077U, // FEXUPL_W |
2874 |
25077U, // FEXUPL_W |
| 2875 |
19568U, // FEXUPR_D |
2875 |
19568U, // FEXUPR_D |
| 2876 |
25374U, // FEXUPR_W |
2876 |
25374U, // FEXUPR_W |
| 2877 |
19810U, // FFINT_S_D |
2877 |
19810U, // FFINT_S_D |
| 2878 |
25674U, // FFINT_S_W |
2878 |
25674U, // FFINT_S_W |
| 2879 |
20289U, // FFINT_U_D |
2879 |
20289U, // FFINT_U_D |
| 2880 |
26104U, // FFINT_U_W |
2880 |
26104U, // FFINT_U_W |
| 2881 |
19306U, // FFQL_D |
2881 |
19306U, // FFQL_D |
| 2882 |
25087U, // FFQL_W |
2882 |
25087U, // FFQL_W |
| 2883 |
19578U, // FFQR_D |
2883 |
19578U, // FFQR_D |
| 2884 |
25384U, // FFQR_W |
2884 |
25384U, // FFQR_W |
| 2885 |
17422U, // FILL_B |
2885 |
17422U, // FILL_B |
| 2886 |
19281U, // FILL_D |
2886 |
19281U, // FILL_D |
| 2887 |
21009U, // FILL_H |
2887 |
21009U, // FILL_H |
| 2888 |
25062U, // FILL_W |
2888 |
25062U, // FILL_W |
| 2889 |
18647U, // FLOG2_D |
2889 |
18647U, // FLOG2_D |
| 2890 |
24565U, // FLOG2_W |
2890 |
24565U, // FLOG2_W |
| 2891 |
19245U, // FLOOR_L_D64 |
2891 |
19245U, // FLOOR_L_D64 |
| 2892 |
19245U, // FLOOR_L_D_MMR6 |
2892 |
19245U, // FLOOR_L_D_MMR6 |
| 2893 |
23577U, // FLOOR_L_S |
2893 |
23577U, // FLOOR_L_S |
| 2894 |
23577U, // FLOOR_L_S_MMR6 |
2894 |
23577U, // FLOOR_L_S_MMR6 |
| 2895 |
20420U, // FLOOR_W_D32 |
2895 |
20420U, // FLOOR_W_D32 |
| 2896 |
20420U, // FLOOR_W_D64 |
2896 |
20420U, // FLOOR_W_D64 |
| 2897 |
20420U, // FLOOR_W_D_MMR6 |
2897 |
20420U, // FLOOR_W_D_MMR6 |
| 2898 |
20420U, // FLOOR_W_MM |
2898 |
20420U, // FLOOR_W_MM |
| 2899 |
23919U, // FLOOR_W_S |
2899 |
23919U, // FLOOR_W_S |
| 2900 |
23919U, // FLOOR_W_S_MM |
2900 |
23919U, // FLOOR_W_S_MM |
| 2901 |
23919U, // FLOOR_W_S_MMR6 |
2901 |
23919U, // FLOOR_W_S_MMR6 |
| 2902 |
570444121U, // FMADD_D |
2902 |
570444121U, // FMADD_D |
| 2903 |
570450023U, // FMADD_W |
2903 |
570450023U, // FMADD_W |
| 2904 |
536889606U, // FMAX_A_D |
2904 |
536889606U, // FMAX_A_D |
| 2905 |
536895524U, // FMAX_A_W |
2905 |
536895524U, // FMAX_A_W |
| 2906 |
536891352U, // FMAX_D |
2906 |
536891352U, // FMAX_D |
| 2907 |
536897127U, // FMAX_W |
2907 |
536897127U, // FMAX_W |
| 2908 |
536889586U, // FMIN_A_D |
2908 |
536889586U, // FMIN_A_D |
| 2909 |
536895504U, // FMIN_A_W |
2909 |
536895504U, // FMIN_A_W |
| 2910 |
536890258U, // FMIN_D |
2910 |
536890258U, // FMIN_D |
| 2911 |
536896039U, // FMIN_W |
2911 |
536896039U, // FMIN_W |
| 2912 |
20381U, // FMOV_D32 |
2912 |
20381U, // FMOV_D32 |
| 2913 |
20381U, // FMOV_D32_MM |
2913 |
20381U, // FMOV_D32_MM |
| 2914 |
20381U, // FMOV_D64 |
2914 |
20381U, // FMOV_D64 |
| 2915 |
20381U, // FMOV_D64_MM |
2915 |
20381U, // FMOV_D64_MM |
| 2916 |
20381U, // FMOV_D_MMR6 |
2916 |
20381U, // FMOV_D_MMR6 |
| 2917 |
23880U, // FMOV_S |
2917 |
23880U, // FMOV_S |
| 2918 |
23880U, // FMOV_S_MM |
2918 |
23880U, // FMOV_S_MM |
| 2919 |
23880U, // FMOV_S_MMR6 |
2919 |
23880U, // FMOV_S_MMR6 |
| 2920 |
570444079U, // FMSUB_D |
2920 |
570444079U, // FMSUB_D |
| 2921 |
570449981U, // FMSUB_W |
2921 |
570449981U, // FMSUB_W |
| 2922 |
536890242U, // FMUL_D |
2922 |
536890242U, // FMUL_D |
| 2923 |
536890243U, // FMUL_D32 |
2923 |
536890243U, // FMUL_D32 |
| 2924 |
536890243U, // FMUL_D32_MM |
2924 |
536890243U, // FMUL_D32_MM |
| 2925 |
536890243U, // FMUL_D64 |
2925 |
536890243U, // FMUL_D64 |
| 2926 |
536890243U, // FMUL_D64_MM |
2926 |
536890243U, // FMUL_D64_MM |
| 2927 |
536894951U, // FMUL_PS64 |
2927 |
536894951U, // FMUL_PS64 |
| 2928 |
536894525U, // FMUL_S |
2928 |
536894525U, // FMUL_S |
| 2929 |
536894525U, // FMUL_S_MM |
2929 |
536894525U, // FMUL_S_MM |
| 2930 |
570448957U, // FMUL_S_MMR6 |
2930 |
570448957U, // FMUL_S_MMR6 |
| 2931 |
536896023U, // FMUL_W |
2931 |
536896023U, // FMUL_W |
| 2932 |
19073U, // FNEG_D32 |
2932 |
19073U, // FNEG_D32 |
| 2933 |
19073U, // FNEG_D32_MM |
2933 |
19073U, // FNEG_D32_MM |
| 2934 |
19073U, // FNEG_D64 |
2934 |
19073U, // FNEG_D64 |
| 2935 |
19073U, // FNEG_D64_MM |
2935 |
19073U, // FNEG_D64_MM |
| 2936 |
23532U, // FNEG_S |
2936 |
23532U, // FNEG_S |
| 2937 |
23532U, // FNEG_S_MM |
2937 |
23532U, // FNEG_S_MM |
| 2938 |
23532U, // FNEG_S_MMR6 |
2938 |
23532U, // FNEG_S_MMR6 |
| 2939 |
2752567255U, // FORK |
2939 |
2752567255U, // FORK |
| 2940 |
19407U, // FRCP_D |
2940 |
19407U, // FRCP_D |
| 2941 |
25160U, // FRCP_W |
2941 |
25160U, // FRCP_W |
| 2942 |
20027U, // FRINT_D |
2942 |
20027U, // FRINT_D |
| 2943 |
25850U, // FRINT_W |
2943 |
25850U, // FRINT_W |
| 2944 |
20055U, // FRSQRT_D |
2944 |
20055U, // FRSQRT_D |
| 2945 |
25878U, // FRSQRT_W |
2945 |
25878U, // FRSQRT_W |
| 2946 |
536889934U, // FSAF_D |
2946 |
536889934U, // FSAF_D |
| 2947 |
536895710U, // FSAF_W |
2947 |
536895710U, // FSAF_W |
| 2948 |
536890382U, // FSEQ_D |
2948 |
536890382U, // FSEQ_D |
| 2949 |
536896149U, // FSEQ_W |
2949 |
536896149U, // FSEQ_W |
| 2950 |
536889797U, // FSLE_D |
2950 |
536889797U, // FSLE_D |
| 2951 |
536895633U, // FSLE_W |
2951 |
536895633U, // FSLE_W |
| 2952 |
536890873U, // FSLT_D |
2952 |
536890873U, // FSLT_D |
| 2953 |
536896728U, // FSLT_W |
2953 |
536896728U, // FSLT_W |
| 2954 |
536889863U, // FSNE_D |
2954 |
536889863U, // FSNE_D |
| 2955 |
536895667U, // FSNE_W |
2955 |
536895667U, // FSNE_W |
| 2956 |
536890472U, // FSOR_D |
2956 |
536890472U, // FSOR_D |
| 2957 |
536896278U, // FSOR_W |
2957 |
536896278U, // FSOR_W |
| 2958 |
20046U, // FSQRT_D |
2958 |
20046U, // FSQRT_D |
| 2959 |
20047U, // FSQRT_D32 |
2959 |
20047U, // FSQRT_D32 |
| 2960 |
20047U, // FSQRT_D32_MM |
2960 |
20047U, // FSQRT_D32_MM |
| 2961 |
20047U, // FSQRT_D64 |
2961 |
20047U, // FSQRT_D64 |
| 2962 |
20047U, // FSQRT_D64_MM |
2962 |
20047U, // FSQRT_D64_MM |
| 2963 |
23857U, // FSQRT_S |
2963 |
23857U, // FSQRT_S |
| 2964 |
23857U, // FSQRT_S_MM |
2964 |
23857U, // FSQRT_S_MM |
| 2965 |
25869U, // FSQRT_W |
2965 |
25869U, // FSQRT_W |
| 2966 |
536889639U, // FSUB_D |
2966 |
536889639U, // FSUB_D |
| 2967 |
536889640U, // FSUB_D32 |
2967 |
536889640U, // FSUB_D32 |
| 2968 |
536889640U, // FSUB_D32_MM |
2968 |
536889640U, // FSUB_D32_MM |
| 2969 |
536889640U, // FSUB_D64 |
2969 |
536889640U, // FSUB_D64 |
| 2970 |
536889640U, // FSUB_D64_MM |
2970 |
536889640U, // FSUB_D64_MM |
| 2971 |
536894927U, // FSUB_PS64 |
2971 |
536894927U, // FSUB_PS64 |
| 2972 |
536894268U, // FSUB_S |
2972 |
536894268U, // FSUB_S |
| 2973 |
536894268U, // FSUB_S_MM |
2973 |
536894268U, // FSUB_S_MM |
| 2974 |
570448700U, // FSUB_S_MMR6 |
2974 |
570448700U, // FSUB_S_MMR6 |
| 2975 |
536895541U, // FSUB_W |
2975 |
536895541U, // FSUB_W |
| 2976 |
536890431U, // FSUEQ_D |
2976 |
536890431U, // FSUEQ_D |
| 2977 |
536896166U, // FSUEQ_W |
2977 |
536896166U, // FSUEQ_W |
| 2978 |
536889846U, // FSULE_D |
2978 |
536889846U, // FSULE_D |
| 2979 |
536895650U, // FSULE_W |
2979 |
536895650U, // FSULE_W |
| 2980 |
536890922U, // FSULT_D |
2980 |
536890922U, // FSULT_D |
| 2981 |
536896745U, // FSULT_W |
2981 |
536896745U, // FSULT_W |
| 2982 |
536889880U, // FSUNE_D |
2982 |
536889880U, // FSUNE_D |
| 2983 |
536895684U, // FSUNE_W |
2983 |
536895684U, // FSUNE_W |
| 2984 |
536890303U, // FSUN_D |
2984 |
536890303U, // FSUN_D |
| 2985 |
536896055U, // FSUN_W |
2985 |
536896055U, // FSUN_W |
| 2986 |
19821U, // FTINT_S_D |
2986 |
19821U, // FTINT_S_D |
| 2987 |
25685U, // FTINT_S_W |
2987 |
25685U, // FTINT_S_W |
| 2988 |
20300U, // FTINT_U_D |
2988 |
20300U, // FTINT_U_D |
| 2989 |
26115U, // FTINT_U_W |
2989 |
26115U, // FTINT_U_W |
| 2990 |
536892037U, // FTQ_H |
2990 |
536892037U, // FTQ_H |
| 2991 |
536896175U, // FTQ_W |
2991 |
536896175U, // FTQ_W |
| 2992 |
19643U, // FTRUNC_S_D |
2992 |
19643U, // FTRUNC_S_D |
| 2993 |
25457U, // FTRUNC_S_W |
2993 |
25457U, // FTRUNC_S_W |
| 2994 |
20110U, // FTRUNC_U_D |
2994 |
20110U, // FTRUNC_U_D |
| 2995 |
25925U, // FTRUNC_U_W |
2995 |
25925U, // FTRUNC_U_W |
| 2996 |
546758U, // GINVI |
2996 |
546758U, // GINVI |
| 2997 |
546758U, // GINVI_MMR6 |
2997 |
546758U, // GINVI_MMR6 |
| 2998 |
218127986U, // GINVT |
2998 |
218127986U, // GINVT |
| 2999 |
218127986U, // GINVT_MMR6 |
2999 |
218127986U, // GINVT_MMR6 |
| 3000 |
536890567U, // HADD_S_D |
3000 |
536890567U, // HADD_S_D |
| 3001 |
536892116U, // HADD_S_H |
3001 |
536892116U, // HADD_S_H |
| 3002 |
536896381U, // HADD_S_W |
3002 |
536896381U, // HADD_S_W |
| 3003 |
536891034U, // HADD_U_D |
3003 |
536891034U, // HADD_U_D |
| 3004 |
536892404U, // HADD_U_H |
3004 |
536892404U, // HADD_U_H |
| 3005 |
536896849U, // HADD_U_W |
3005 |
536896849U, // HADD_U_W |
| 3006 |
536890534U, // HSUB_S_D |
3006 |
536890534U, // HSUB_S_D |
| 3007 |
536892095U, // HSUB_S_H |
3007 |
536892095U, // HSUB_S_H |
| 3008 |
536896348U, // HSUB_S_W |
3008 |
536896348U, // HSUB_S_W |
| 3009 |
536891001U, // HSUB_U_D |
3009 |
536891001U, // HSUB_U_D |
| 3010 |
536892383U, // HSUB_U_H |
3010 |
536892383U, // HSUB_U_H |
| 3011 |
536896816U, // HSUB_U_W |
3011 |
536896816U, // HSUB_U_W |
| 3012 |
645291U, // HYPCALL |
3012 |
645291U, // HYPCALL |
| 3013 |
645291U, // HYPCALL_MM |
3013 |
645291U, // HYPCALL_MM |
| 3014 |
536888837U, // ILVEV_B |
3014 |
536888837U, // ILVEV_B |
| 3015 |
536891268U, // ILVEV_D |
3015 |
536891268U, // ILVEV_D |
| 3016 |
536892626U, // ILVEV_H |
3016 |
536892626U, // ILVEV_H |
| 3017 |
536897093U, // ILVEV_W |
3017 |
536897093U, // ILVEV_W |
| 3018 |
536888365U, // ILVL_B |
3018 |
536888365U, // ILVL_B |
| 3019 |
536890250U, // ILVL_D |
3019 |
536890250U, // ILVL_D |
| 3020 |
536891952U, // ILVL_H |
3020 |
536891952U, // ILVL_H |
| 3021 |
536896031U, // ILVL_W |
3021 |
536896031U, // ILVL_W |
| 3022 |
536888117U, // ILVOD_B |
3022 |
536888117U, // ILVOD_B |
| 3023 |
536889723U, // ILVOD_D |
3023 |
536889723U, // ILVOD_D |
| 3024 |
536891754U, // ILVOD_H |
3024 |
536891754U, // ILVOD_H |
| 3025 |
536895616U, // ILVOD_W |
3025 |
536895616U, // ILVOD_W |
| 3026 |
536888413U, // ILVR_B |
3026 |
536888413U, // ILVR_B |
| 3027 |
536890507U, // ILVR_D |
3027 |
536890507U, // ILVR_D |
| 3028 |
536892077U, // ILVR_H |
3028 |
536892077U, // ILVR_H |
| 3029 |
536896321U, // ILVR_W |
3029 |
536896321U, // ILVR_W |
| 3030 |
536894916U, // INS |
3030 |
536894916U, // INS |
| 3031 |
241714476U, // INSERT_B |
3031 |
241714476U, // INSERT_B |
| 3032 |
258494020U, // INSERT_D |
3032 |
258494020U, // INSERT_D |
| 3033 |
275272645U, // INSERT_H |
3033 |
275272645U, // INSERT_H |
| 3034 |
292054275U, // INSERT_W |
3034 |
292054275U, // INSERT_W |
| 3035 |
33578991U, // INSV |
3035 |
33578991U, // INSV |
| 3036 |
308822846U, // INSVE_B |
3036 |
308822846U, // INSVE_B |
| 3037 |
325601825U, // INSVE_D |
3037 |
325601825U, // INSVE_D |
| 3038 |
342380915U, // INSVE_H |
3038 |
342380915U, // INSVE_H |
| 3039 |
359162061U, // INSVE_W |
3039 |
359162061U, // INSVE_W |
| 3040 |
33578991U, // INSV_MM |
3040 |
33578991U, // INSV_MM |
| 3041 |
536894916U, // INS_MM |
3041 |
536894916U, // INS_MM |
| 3042 |
536894916U, // INS_MMR6 |
3042 |
536894916U, // INS_MMR6 |
| 3043 |
186317U, // J |
3043 |
186317U, // J |
| 3044 |
186356U, // JAL |
3044 |
186356U, // JAL |
| 3045 |
23264U, // JALR |
3045 |
23264U, // JALR |
| 3046 |
547552U, // JALR16_MM |
3046 |
547552U, // JALR16_MM |
| 3047 |
23264U, // JALR64 |
3047 |
23264U, // JALR64 |
| 3048 |
547552U, // JALRC16_MMR6 |
3048 |
547552U, // JALRC16_MMR6 |
| 3049 |
17977U, // JALRC_HB_MMR6 |
3049 |
17977U, // JALRC_HB_MMR6 |
| 3050 |
18516U, // JALRC_MMR6 |
3050 |
18516U, // JALRC_MMR6 |
| 3051 |
541239U, // JALRS16_MM |
3051 |
541239U, // JALRS16_MM |
| 3052 |
24100U, // JALRS_MM |
3052 |
24100U, // JALRS_MM |
| 3053 |
17994U, // JALR_HB |
3053 |
17994U, // JALR_HB |
| 3054 |
17994U, // JALR_HB64 |
3054 |
17994U, // JALR_HB64 |
| 3055 |
23264U, // JALR_MM |
3055 |
23264U, // JALR_MM |
| 3056 |
187819U, // JALS_MM |
3056 |
187819U, // JALS_MM |
| 3057 |
190126U, // JALX |
3057 |
190126U, // JALX |
| 3058 |
190126U, // JALX_MM |
3058 |
190126U, // JALX_MM |
| 3059 |
186356U, // JAL_MM |
3059 |
186356U, // JAL_MM |
| 3060 |
18395U, // JIALC |
3060 |
18395U, // JIALC |
| 3061 |
18395U, // JIALC64 |
3061 |
18395U, // JIALC64 |
| 3062 |
18395U, // JIALC_MMR6 |
3062 |
18395U, // JIALC_MMR6 |
| 3063 |
18384U, // JIC |
3063 |
18384U, // JIC |
| 3064 |
18384U, // JIC64 |
3064 |
18384U, // JIC64 |
| 3065 |
18384U, // JIC_MMR6 |
3065 |
18384U, // JIC_MMR6 |
| 3066 |
547548U, // JR |
3066 |
547548U, // JR |
| 3067 |
541226U, // JR16_MM |
3067 |
541226U, // JR16_MM |
| 3068 |
547548U, // JR64 |
3068 |
547548U, // JR64 |
| 3069 |
547353U, // JRADDIUSP |
3069 |
547353U, // JRADDIUSP |
| 3070 |
542799U, // JRC16_MM |
3070 |
542799U, // JRC16_MM |
| 3071 |
541104U, // JRC16_MMR6 |
3071 |
541104U, // JRC16_MMR6 |
| 3072 |
547341U, // JRCADDIUSP_MMR6 |
3072 |
547341U, // JRCADDIUSP_MMR6 |
| 3073 |
542275U, // JR_HB |
3073 |
542275U, // JR_HB |
| 3074 |
542275U, // JR_HB64 |
3074 |
542275U, // JR_HB64 |
| 3075 |
542275U, // JR_HB64_R6 |
3075 |
542275U, // JR_HB64_R6 |
| 3076 |
542275U, // JR_HB_R6 |
3076 |
542275U, // JR_HB_R6 |
| 3077 |
547548U, // JR_MM |
3077 |
547548U, // JR_MM |
| 3078 |
186317U, // J_MM |
3078 |
186317U, // J_MM |
| 3079 |
7542772U, // Jal16 |
3079 |
7542772U, // Jal16 |
| 3080 |
8067060U, // JalB16 |
3080 |
8067060U, // JalB16 |
| 3081 |
10524U, // JrRa16 |
3081 |
10524U, // JrRa16 |
| 3082 |
10516U, // JrcRa16 |
3082 |
10516U, // JrcRa16 |
| 3083 |
542799U, // JrcRx16 |
3083 |
542799U, // JrcRx16 |
| 3084 |
542804U, // JumpLinkReg16 |
3084 |
542804U, // JumpLinkReg16 |
| 3085 |
50349651U, // LB |
3085 |
50349651U, // LB |
| 3086 |
50349651U, // LB64 |
3086 |
50349651U, // LB64 |
| 3087 |
50352227U, // LBE |
3087 |
50352227U, // LBE |
| 3088 |
50352227U, // LBE_MM |
3088 |
50352227U, // LBE_MM |
| 3089 |
50348615U, // LBU16_MM |
3089 |
50348615U, // LBU16_MM |
| 3090 |
3254806196U, // LBUX |
3090 |
3254806196U, // LBUX |
| 3091 |
3254806196U, // LBUX_MM |
3091 |
3254806196U, // LBUX_MM |
| 3092 |
50355845U, // LBU_MMR6 |
3092 |
50355845U, // LBU_MMR6 |
| 3093 |
50349651U, // LB_MM |
3093 |
50349651U, // LB_MM |
| 3094 |
50349651U, // LB_MMR6 |
3094 |
50349651U, // LB_MMR6 |
| 3095 |
50355845U, // LBu |
3095 |
50355845U, // LBu |
| 3096 |
50355845U, // LBu64 |
3096 |
50355845U, // LBu64 |
| 3097 |
50352363U, // LBuE |
3097 |
50352363U, // LBuE |
| 3098 |
50352363U, // LBuE_MM |
3098 |
50352363U, // LBuE_MM |
| 3099 |
50355845U, // LBu_MM |
3099 |
50355845U, // LBu_MM |
| 3100 |
50352186U, // LD |
3100 |
50352186U, // LD |
| 3101 |
50348118U, // LDC1 |
3101 |
50348118U, // LDC1 |
| 3102 |
50348118U, // LDC164 |
3102 |
50348118U, // LDC164 |
| 3103 |
50348118U, // LDC1_D64_MMR6 |
3103 |
50348118U, // LDC1_D64_MMR6 |
| 3104 |
50348118U, // LDC1_MM_D32 |
3104 |
50348118U, // LDC1_MM_D32 |
| 3105 |
50348118U, // LDC1_MM_D64 |
3105 |
50348118U, // LDC1_MM_D64 |
| 3106 |
50348334U, // LDC2 |
3106 |
50348334U, // LDC2 |
| 3107 |
50348334U, // LDC2_MMR6 |
3107 |
50348334U, // LDC2_MMR6 |
| 3108 |
50348334U, // LDC2_R6 |
3108 |
50348334U, // LDC2_R6 |
| 3109 |
50348419U, // LDC3 |
3109 |
50348419U, // LDC3 |
| 3110 |
17248U, // LDI_B |
3110 |
17248U, // LDI_B |
| 3111 |
19089U, // LDI_D |
3111 |
19089U, // LDI_D |
| 3112 |
20885U, // LDI_H |
3112 |
20885U, // LDI_H |
| 3113 |
24912U, // LDI_W |
3113 |
24912U, // LDI_W |
| 3114 |
50354256U, // LDL |
3114 |
50354256U, // LDL |
| 3115 |
18462U, // LDPC |
3115 |
18462U, // LDPC |
| 3116 |
50354842U, // LDR |
3116 |
50354842U, // LDR |
| 3117 |
3254796438U, // LDXC1 |
3117 |
3254796438U, // LDXC1 |
| 3118 |
3254796438U, // LDXC164 |
3118 |
3254796438U, // LDXC164 |
| 3119 |
50348838U, // LD_B |
3119 |
50348838U, // LD_B |
| 3120 |
50350444U, // LD_D |
3120 |
50350444U, // LD_D |
| 3121 |
50352475U, // LD_H |
3121 |
50352475U, // LD_H |
| 3122 |
50356337U, // LD_W |
3122 |
50356337U, // LD_W |
| 3123 |
134242016U, // LEA_ADDiu |
3123 |
134242016U, // LEA_ADDiu |
| 3124 |
134242015U, // LEA_ADDiu64 |
3124 |
134242015U, // LEA_ADDiu64 |
| 3125 |
134242016U, // LEA_ADDiu_MM |
3125 |
134242016U, // LEA_ADDiu_MM |
| 3126 |
50353427U, // LH |
3126 |
50353427U, // LH |
| 3127 |
50353427U, // LH64 |
3127 |
50353427U, // LH64 |
| 3128 |
50352279U, // LHE |
3128 |
50352279U, // LHE |
| 3129 |
50352279U, // LHE_MM |
3129 |
50352279U, // LHE_MM |
| 3130 |
50348638U, // LHU16_MM |
3130 |
50348638U, // LHU16_MM |
| 3131 |
3254806185U, // LHX |
3131 |
3254806185U, // LHX |
| 3132 |
3254806185U, // LHX_MM |
3132 |
3254806185U, // LHX_MM |
| 3133 |
50353427U, // LH_MM |
3133 |
50353427U, // LH_MM |
| 3134 |
50355923U, // LHu |
3134 |
50355923U, // LHu |
| 3135 |
50355923U, // LHu64 |
3135 |
50355923U, // LHu64 |
| 3136 |
50352369U, // LHuE |
3136 |
50352369U, // LHuE |
| 3137 |
50352369U, // LHuE_MM |
3137 |
50352369U, // LHuE_MM |
| 3138 |
50355923U, // LHu_MM |
3138 |
50355923U, // LHu_MM |
| 3139 |
16878U, // LI16_MM |
3139 |
16878U, // LI16_MM |
| 3140 |
16878U, // LI16_MMR6 |
3140 |
16878U, // LI16_MMR6 |
| 3141 |
50354352U, // LL |
3141 |
50354352U, // LL |
| 3142 |
50354352U, // LL64 |
3142 |
50354352U, // LL64 |
| 3143 |
50354352U, // LL64_R6 |
3143 |
50354352U, // LL64_R6 |
| 3144 |
50352190U, // LLD |
3144 |
50352190U, // LLD |
| 3145 |
50352190U, // LLD_R6 |
3145 |
50352190U, // LLD_R6 |
| 3146 |
50352302U, // LLE |
3146 |
50352302U, // LLE |
| 3147 |
50352302U, // LLE_MM |
3147 |
50352302U, // LLE_MM |
| 3148 |
50354352U, // LL_MM |
3148 |
50354352U, // LL_MM |
| 3149 |
50354352U, // LL_MMR6 |
3149 |
50354352U, // LL_MMR6 |
| 3150 |
50354352U, // LL_R6 |
3150 |
50354352U, // LL_R6 |
| 3151 |
536888020U, // LSA |
3151 |
536888020U, // LSA |
| 3152 |
3828450004U, // LSA_MMR6 |
3152 |
3828450004U, // LSA_MMR6 |
| 3153 |
536888020U, // LSA_R6 |
3153 |
536888020U, // LSA_R6 |
| 3154 |
201349057U, // LUI_MMR6 |
3154 |
201349057U, // LUI_MMR6 |
| 3155 |
3254796452U, // LUXC1 |
3155 |
3254796452U, // LUXC1 |
| 3156 |
3254796452U, // LUXC164 |
3156 |
3254796452U, // LUXC164 |
| 3157 |
3254796452U, // LUXC1_MM |
3157 |
3254796452U, // LUXC1_MM |
| 3158 |
201349057U, // LUi |
3158 |
201349057U, // LUi |
| 3159 |
201349057U, // LUi64 |
3159 |
201349057U, // LUi64 |
| 3160 |
201349057U, // LUi_MM |
3160 |
201349057U, // LUi_MM |
| 3161 |
50357902U, // LW |
3161 |
50357902U, // LW |
| 3162 |
50348645U, // LW16_MM |
3162 |
50348645U, // LW16_MM |
| 3163 |
50357902U, // LW64 |
3163 |
50357902U, // LW64 |
| 3164 |
50348170U, // LWC1 |
3164 |
50348170U, // LWC1 |
| 3165 |
50348170U, // LWC1_MM |
3165 |
50348170U, // LWC1_MM |
| 3166 |
50348386U, // LWC2 |
3166 |
50348386U, // LWC2 |
| 3167 |
50348386U, // LWC2_MMR6 |
3167 |
50348386U, // LWC2_MMR6 |
| 3168 |
50348386U, // LWC2_R6 |
3168 |
50348386U, // LWC2_R6 |
| 3169 |
50348431U, // LWC3 |
3169 |
50348431U, // LWC3 |
| 3170 |
50357902U, // LWDSP |
3170 |
50357902U, // LWDSP |
| 3171 |
50357902U, // LWDSP_MM |
3171 |
50357902U, // LWDSP_MM |
| 3172 |
50352381U, // LWE |
3172 |
50352381U, // LWE |
| 3173 |
50352381U, // LWE_MM |
3173 |
50352381U, // LWE_MM |
| 3174 |
50357902U, // LWGP_MM |
3174 |
50357902U, // LWGP_MM |
| 3175 |
50354470U, // LWL |
3175 |
50354470U, // LWL |
| 3176 |
50354470U, // LWL64 |
3176 |
50354470U, // LWL64 |
| 3177 |
50352312U, // LWLE |
3177 |
50352312U, // LWLE |
| 3178 |
50352312U, // LWLE_MM |
3178 |
50352312U, // LWLE_MM |
| 3179 |
50354470U, // LWL_MM |
3179 |
50354470U, // LWL_MM |
| 3180 |
66059U, // LWM16_MM |
3180 |
66059U, // LWM16_MM |
| 3181 |
66059U, // LWM16_MMR6 |
3181 |
66059U, // LWM16_MMR6 |
| 3182 |
65799U, // LWM32_MM |
3182 |
65799U, // LWM32_MM |
| 3183 |
18499U, // LWPC |
3183 |
18499U, // LWPC |
| 3184 |
18499U, // LWPC_MMR6 |
3184 |
18499U, // LWPC_MMR6 |
| 3185 |
369121850U, // LWP_MM |
3185 |
369121850U, // LWP_MM |
| 3186 |
50354976U, // LWR |
3186 |
50354976U, // LWR |
| 3187 |
50354976U, // LWR64 |
3187 |
50354976U, // LWR64 |
| 3188 |
50352351U, // LWRE |
3188 |
50352351U, // LWRE |
| 3189 |
50352351U, // LWRE_MM |
3189 |
50352351U, // LWRE_MM |
| 3190 |
50354976U, // LWR_MM |
3190 |
50354976U, // LWR_MM |
| 3191 |
50357902U, // LWSP_MM |
3191 |
50357902U, // LWSP_MM |
| 3192 |
18492U, // LWUPC |
3192 |
18492U, // LWUPC |
| 3193 |
50356070U, // LWU_MM |
3193 |
50356070U, // LWU_MM |
| 3194 |
3254806202U, // LWX |
3194 |
3254806202U, // LWX |
| 3195 |
3254796466U, // LWXC1 |
3195 |
3254796466U, // LWXC1 |
| 3196 |
3254796466U, // LWXC1_MM |
3196 |
3254796466U, // LWXC1_MM |
| 3197 |
3254804017U, // LWXS_MM |
3197 |
3254804017U, // LWXS_MM |
| 3198 |
3254806202U, // LWX_MM |
3198 |
3254806202U, // LWX_MM |
| 3199 |
50357902U, // LW_MM |
3199 |
50357902U, // LW_MM |
| 3200 |
50357902U, // LW_MMR6 |
3200 |
50357902U, // LW_MMR6 |
| 3201 |
50356070U, // LWu |
3201 |
50356070U, // LWu |
| 3202 |
50349651U, // LbRxRyOffMemX16 |
3202 |
50349651U, // LbRxRyOffMemX16 |
| 3203 |
50355845U, // LbuRxRyOffMemX16 |
3203 |
50355845U, // LbuRxRyOffMemX16 |
| 3204 |
50353427U, // LhRxRyOffMemX16 |
3204 |
50353427U, // LhRxRyOffMemX16 |
| 3205 |
50355923U, // LhuRxRyOffMemX16 |
3205 |
50355923U, // LhuRxRyOffMemX16 |
| 3206 |
1610635144U, // LiRxImm16 |
3206 |
1610635144U, // LiRxImm16 |
| 3207 |
22398U, // LiRxImmAlignX16 |
3207 |
22398U, // LiRxImmAlignX16 |
| 3208 |
22408U, // LiRxImmX16 |
3208 |
22408U, // LiRxImmX16 |
| 3209 |
26254U, // LwRxPcTcp16 |
3209 |
26254U, // LwRxPcTcp16 |
| 3210 |
26254U, // LwRxPcTcpX16 |
3210 |
26254U, // LwRxPcTcpX16 |
| 3211 |
50357902U, // LwRxRyOffMemX16 |
3211 |
50357902U, // LwRxRyOffMemX16 |
| 3212 |
50357902U, // LwRxSpImmX16 |
3212 |
50357902U, // LwRxSpImmX16 |
| 3213 |
20523U, // MADD |
3213 |
20523U, // MADD |
| 3214 |
570444383U, // MADDF_D |
3214 |
570444383U, // MADDF_D |
| 3215 |
570444383U, // MADDF_D_MMR6 |
3215 |
570444383U, // MADDF_D_MMR6 |
| 3216 |
570448851U, // MADDF_S |
3216 |
570448851U, // MADDF_S |
| 3217 |
570448851U, // MADDF_S_MMR6 |
3217 |
570448851U, // MADDF_S_MMR6 |
| 3218 |
570446441U, // MADDR_Q_H |
3218 |
570446441U, // MADDR_Q_H |
| 3219 |
570450552U, // MADDR_Q_W |
3219 |
570450552U, // MADDR_Q_W |
| 3220 |
24230U, // MADDU |
3220 |
24230U, // MADDU |
| 3221 |
536895142U, // MADDU_DSP |
3221 |
536895142U, // MADDU_DSP |
| 3222 |
536895142U, // MADDU_DSP_MM |
3222 |
536895142U, // MADDU_DSP_MM |
| 3223 |
24230U, // MADDU_MM |
3223 |
24230U, // MADDU_MM |
| 3224 |
570443251U, // MADDV_B |
3224 |
570443251U, // MADDV_B |
| 3225 |
570445682U, // MADDV_D |
3225 |
570445682U, // MADDV_D |
| 3226 |
570447040U, // MADDV_H |
3226 |
570447040U, // MADDV_H |
| 3227 |
570451507U, // MADDV_W |
3227 |
570451507U, // MADDV_W |
| 3228 |
536889690U, // MADD_D32 |
3228 |
536889690U, // MADD_D32 |
| 3229 |
536889690U, // MADD_D32_MM |
3229 |
536889690U, // MADD_D32_MM |
| 3230 |
536889690U, // MADD_D64 |
3230 |
536889690U, // MADD_D64 |
| 3231 |
536891435U, // MADD_DSP |
3231 |
536891435U, // MADD_DSP |
| 3232 |
536891435U, // MADD_DSP_MM |
3232 |
536891435U, // MADD_DSP_MM |
| 3233 |
20523U, // MADD_MM |
3233 |
20523U, // MADD_MM |
| 3234 |
570446411U, // MADD_Q_H |
3234 |
570446411U, // MADD_Q_H |
| 3235 |
570450522U, // MADD_Q_W |
3235 |
570450522U, // MADD_Q_W |
| 3236 |
536894285U, // MADD_S |
3236 |
536894285U, // MADD_S |
| 3237 |
536894285U, // MADD_S_MM |
3237 |
536894285U, // MADD_S_MM |
| 3238 |
536893555U, // MAQ_SA_W_PHL |
3238 |
536893555U, // MAQ_SA_W_PHL |
| 3239 |
536893555U, // MAQ_SA_W_PHL_MM |
3239 |
536893555U, // MAQ_SA_W_PHL_MM |
| 3240 |
536894116U, // MAQ_SA_W_PHR |
3240 |
536894116U, // MAQ_SA_W_PHR |
| 3241 |
536894116U, // MAQ_SA_W_PHR_MM |
3241 |
536894116U, // MAQ_SA_W_PHR_MM |
| 3242 |
536893583U, // MAQ_S_W_PHL |
3242 |
536893583U, // MAQ_S_W_PHL |
| 3243 |
536893583U, // MAQ_S_W_PHL_MM |
3243 |
536893583U, // MAQ_S_W_PHL_MM |
| 3244 |
536894144U, // MAQ_S_W_PHR |
3244 |
536894144U, // MAQ_S_W_PHR |
| 3245 |
536894144U, // MAQ_S_W_PHR_MM |
3245 |
536894144U, // MAQ_S_W_PHR_MM |
| 3246 |
536889631U, // MAXA_D |
3246 |
536889631U, // MAXA_D |
| 3247 |
536889631U, // MAXA_D_MMR6 |
3247 |
536889631U, // MAXA_D_MMR6 |
| 3248 |
536894258U, // MAXA_S |
3248 |
536894258U, // MAXA_S |
| 3249 |
536894258U, // MAXA_S_MMR6 |
3249 |
536894258U, // MAXA_S_MMR6 |
| 3250 |
536888488U, // MAXI_S_B |
3250 |
536888488U, // MAXI_S_B |
| 3251 |
536890645U, // MAXI_S_D |
3251 |
536890645U, // MAXI_S_D |
| 3252 |
536892194U, // MAXI_S_H |
3252 |
536892194U, // MAXI_S_H |
| 3253 |
536896459U, // MAXI_S_W |
3253 |
536896459U, // MAXI_S_W |
| 3254 |
536888703U, // MAXI_U_B |
3254 |
536888703U, // MAXI_U_B |
| 3255 |
536891112U, // MAXI_U_D |
3255 |
536891112U, // MAXI_U_D |
| 3256 |
536892482U, // MAXI_U_H |
3256 |
536892482U, // MAXI_U_H |
| 3257 |
536896927U, // MAXI_U_W |
3257 |
536896927U, // MAXI_U_W |
| 3258 |
536888069U, // MAX_A_B |
3258 |
536888069U, // MAX_A_B |
| 3259 |
536889607U, // MAX_A_D |
3259 |
536889607U, // MAX_A_D |
| 3260 |
536891706U, // MAX_A_H |
3260 |
536891706U, // MAX_A_H |
| 3261 |
536895525U, // MAX_A_W |
3261 |
536895525U, // MAX_A_W |
| 3262 |
536891353U, // MAX_D |
3262 |
536891353U, // MAX_D |
| 3263 |
536891353U, // MAX_D_MMR6 |
3263 |
536891353U, // MAX_D_MMR6 |
| 3264 |
536894851U, // MAX_S |
3264 |
536894851U, // MAX_S |
| 3265 |
536888576U, // MAX_S_B |
3265 |
536888576U, // MAX_S_B |
| 3266 |
536890765U, // MAX_S_D |
3266 |
536890765U, // MAX_S_D |
| 3267 |
536892313U, // MAX_S_H |
3267 |
536892313U, // MAX_S_H |
| 3268 |
536894851U, // MAX_S_MMR6 |
3268 |
536894851U, // MAX_S_MMR6 |
| 3269 |
536896640U, // MAX_S_W |
3269 |
536896640U, // MAX_S_W |
| 3270 |
536888791U, // MAX_U_B |
3270 |
536888791U, // MAX_U_B |
| 3271 |
536891232U, // MAX_U_D |
3271 |
536891232U, // MAX_U_D |
| 3272 |
536892580U, // MAX_U_H |
3272 |
536892580U, // MAX_U_H |
| 3273 |
536897047U, // MAX_U_W |
3273 |
536897047U, // MAX_U_W |
| 3274 |
536887298U, // MFC0 |
3274 |
536887298U, // MFC0 |
| 3275 |
536887298U, // MFC0_MMR6 |
3275 |
536887298U, // MFC0_MMR6 |
| 3276 |
16489U, // MFC1 |
3276 |
16489U, // MFC1 |
| 3277 |
16489U, // MFC1_D64 |
3277 |
16489U, // MFC1_D64 |
| 3278 |
16489U, // MFC1_MM |
3278 |
16489U, // MFC1_MM |
| 3279 |
16489U, // MFC1_MMR6 |
3279 |
16489U, // MFC1_MMR6 |
| 3280 |
536887617U, // MFC2 |
3280 |
536887617U, // MFC2 |
| 3281 |
16705U, // MFC2_MMR6 |
3281 |
16705U, // MFC2_MMR6 |
| 3282 |
536887305U, // MFGC0 |
3282 |
536887305U, // MFGC0 |
| 3283 |
536887305U, // MFGC0_MM |
3283 |
536887305U, // MFGC0_MM |
| 3284 |
536887336U, // MFHC0_MMR6 |
3284 |
536887336U, // MFHC0_MMR6 |
| 3285 |
16495U, // MFHC1_D32 |
3285 |
16495U, // MFHC1_D32 |
| 3286 |
16495U, // MFHC1_D32_MM |
3286 |
16495U, // MFHC1_D32_MM |
| 3287 |
16495U, // MFHC1_D64 |
3287 |
16495U, // MFHC1_D64 |
| 3288 |
16495U, // MFHC1_D64_MM |
3288 |
16495U, // MFHC1_D64_MM |
| 3289 |
16711U, // MFHC2_MMR6 |
3289 |
16711U, // MFHC2_MMR6 |
| 3290 |
536887312U, // MFHGC0 |
3290 |
536887312U, // MFHGC0 |
| 3291 |
536887312U, // MFHGC0_MM |
3291 |
536887312U, // MFHGC0_MM |
| 3292 |
546674U, // MFHI |
3292 |
546674U, // MFHI |
| 3293 |
541158U, // MFHI16_MM |
3293 |
541158U, // MFHI16_MM |
| 3294 |
546674U, // MFHI64 |
3294 |
546674U, // MFHI64 |
| 3295 |
22386U, // MFHI_DSP |
3295 |
22386U, // MFHI_DSP |
| 3296 |
22386U, // MFHI_DSP_MM |
3296 |
22386U, // MFHI_DSP_MM |
| 3297 |
546674U, // MFHI_MM |
3297 |
546674U, // MFHI_MM |
| 3298 |
547206U, // MFLO |
3298 |
547206U, // MFLO |
| 3299 |
541209U, // MFLO16_MM |
3299 |
541209U, // MFLO16_MM |
| 3300 |
547206U, // MFLO64 |
3300 |
547206U, // MFLO64 |
| 3301 |
22918U, // MFLO_DSP |
3301 |
22918U, // MFLO_DSP |
| 3302 |
22918U, // MFLO_DSP_MM |
3302 |
22918U, // MFLO_DSP_MM |
| 3303 |
547206U, // MFLO_MM |
3303 |
547206U, // MFLO_MM |
| 3304 |
536894214U, // MFTR |
3304 |
536894214U, // MFTR |
| 3305 |
536889616U, // MINA_D |
3305 |
536889616U, // MINA_D |
| 3306 |
536889616U, // MINA_D_MMR6 |
3306 |
536889616U, // MINA_D_MMR6 |
| 3307 |
536894250U, // MINA_S |
3307 |
536894250U, // MINA_S |
| 3308 |
536894250U, // MINA_S_MMR6 |
3308 |
536894250U, // MINA_S_MMR6 |
| 3309 |
536888468U, // MINI_S_B |
3309 |
536888468U, // MINI_S_B |
| 3310 |
536890625U, // MINI_S_D |
3310 |
536890625U, // MINI_S_D |
| 3311 |
536892174U, // MINI_S_H |
3311 |
536892174U, // MINI_S_H |
| 3312 |
536896439U, // MINI_S_W |
3312 |
536896439U, // MINI_S_W |
| 3313 |
536888683U, // MINI_U_B |
3313 |
536888683U, // MINI_U_B |
| 3314 |
536891092U, // MINI_U_D |
3314 |
536891092U, // MINI_U_D |
| 3315 |
536892462U, // MINI_U_H |
3315 |
536892462U, // MINI_U_H |
| 3316 |
536896907U, // MINI_U_W |
3316 |
536896907U, // MINI_U_W |
| 3317 |
536888050U, // MIN_A_B |
3317 |
536888050U, // MIN_A_B |
| 3318 |
536889587U, // MIN_A_D |
3318 |
536889587U, // MIN_A_D |
| 3319 |
536891687U, // MIN_A_H |
3319 |
536891687U, // MIN_A_H |
| 3320 |
536895505U, // MIN_A_W |
3320 |
536895505U, // MIN_A_W |
| 3321 |
536890259U, // MIN_D |
3321 |
536890259U, // MIN_D |
| 3322 |
536890259U, // MIN_D_MMR6 |
3322 |
536890259U, // MIN_D_MMR6 |
| 3323 |
536894532U, // MIN_S |
3323 |
536894532U, // MIN_S |
| 3324 |
536888498U, // MIN_S_B |
3324 |
536888498U, // MIN_S_B |
| 3325 |
536890655U, // MIN_S_D |
3325 |
536890655U, // MIN_S_D |
| 3326 |
536892204U, // MIN_S_H |
3326 |
536892204U, // MIN_S_H |
| 3327 |
536894532U, // MIN_S_MMR6 |
3327 |
536894532U, // MIN_S_MMR6 |
| 3328 |
536896479U, // MIN_S_W |
3328 |
536896479U, // MIN_S_W |
| 3329 |
536888713U, // MIN_U_B |
3329 |
536888713U, // MIN_U_B |
| 3330 |
536891122U, // MIN_U_D |
3330 |
536891122U, // MIN_U_D |
| 3331 |
536892492U, // MIN_U_H |
3331 |
536892492U, // MIN_U_H |
| 3332 |
536896937U, // MIN_U_W |
3332 |
536896937U, // MIN_U_W |
| 3333 |
536891482U, // MOD |
3333 |
536891482U, // MOD |
| 3334 |
536889255U, // MODSUB |
3334 |
536889255U, // MODSUB |
| 3335 |
536889255U, // MODSUB_MM |
3335 |
536889255U, // MODSUB_MM |
| 3336 |
536895150U, // MODU |
3336 |
536895150U, // MODU |
| 3337 |
536895150U, // MODU_MMR6 |
3337 |
536895150U, // MODU_MMR6 |
| 3338 |
536891482U, // MOD_MMR6 |
3338 |
536891482U, // MOD_MMR6 |
| 3339 |
536888431U, // MOD_S_B |
3339 |
536888431U, // MOD_S_B |
| 3340 |
536890588U, // MOD_S_D |
3340 |
536890588U, // MOD_S_D |
| 3341 |
536892137U, // MOD_S_H |
3341 |
536892137U, // MOD_S_H |
| 3342 |
536896402U, // MOD_S_W |
3342 |
536896402U, // MOD_S_W |
| 3343 |
536888646U, // MOD_U_B |
3343 |
536888646U, // MOD_U_B |
| 3344 |
536891055U, // MOD_U_D |
3344 |
536891055U, // MOD_U_D |
| 3345 |
536892425U, // MOD_U_H |
3345 |
536892425U, // MOD_U_H |
| 3346 |
536896870U, // MOD_U_W |
3346 |
536896870U, // MOD_U_W |
| 3347 |
20727U, // MOVE16_MM |
3347 |
20727U, // MOVE16_MM |
| 3348 |
16848U, // MOVE16_MMR6 |
3348 |
16848U, // MOVE16_MMR6 |
| 3349 |
536893881U, // MOVEP_MM |
3349 |
536893881U, // MOVEP_MM |
| 3350 |
536893881U, // MOVEP_MMR6 |
3350 |
536893881U, // MOVEP_MMR6 |
| 3351 |
24434U, // MOVE_V |
3351 |
24434U, // MOVE_V |
| 3352 |
536889976U, // MOVF_D32 |
3352 |
536889976U, // MOVF_D32 |
| 3353 |
536889976U, // MOVF_D32_MM |
3353 |
536889976U, // MOVF_D32_MM |
| 3354 |
536889976U, // MOVF_D64 |
3354 |
536889976U, // MOVF_D64 |
| 3355 |
536891667U, // MOVF_I |
3355 |
536891667U, // MOVF_I |
| 3356 |
536891667U, // MOVF_I64 |
3356 |
536891667U, // MOVF_I64 |
| 3357 |
536891667U, // MOVF_I_MM |
3357 |
536891667U, // MOVF_I_MM |
| 3358 |
536894436U, // MOVF_S |
3358 |
536894436U, // MOVF_S |
| 3359 |
536894436U, // MOVF_S_MM |
3359 |
536894436U, // MOVF_S_MM |
| 3360 |
536890311U, // MOVN_I64_D64 |
3360 |
536890311U, // MOVN_I64_D64 |
| 3361 |
536893818U, // MOVN_I64_I |
3361 |
536893818U, // MOVN_I64_I |
| 3362 |
536893818U, // MOVN_I64_I64 |
3362 |
536893818U, // MOVN_I64_I64 |
| 3363 |
536894568U, // MOVN_I64_S |
3363 |
536894568U, // MOVN_I64_S |
| 3364 |
536890311U, // MOVN_I_D32 |
3364 |
536890311U, // MOVN_I_D32 |
| 3365 |
536890311U, // MOVN_I_D32_MM |
3365 |
536890311U, // MOVN_I_D32_MM |
| 3366 |
536890311U, // MOVN_I_D64 |
3366 |
536890311U, // MOVN_I_D64 |
| 3367 |
536893818U, // MOVN_I_I |
3367 |
536893818U, // MOVN_I_I |
| 3368 |
536893818U, // MOVN_I_I64 |
3368 |
536893818U, // MOVN_I_I64 |
| 3369 |
536893818U, // MOVN_I_MM |
3369 |
536893818U, // MOVN_I_MM |
| 3370 |
536894568U, // MOVN_I_S |
3370 |
536894568U, // MOVN_I_S |
| 3371 |
536894568U, // MOVN_I_S_MM |
3371 |
536894568U, // MOVN_I_S_MM |
| 3372 |
536890983U, // MOVT_D32 |
3372 |
536890983U, // MOVT_D32 |
| 3373 |
536890983U, // MOVT_D32_MM |
3373 |
536890983U, // MOVT_D32_MM |
| 3374 |
536890983U, // MOVT_D64 |
3374 |
536890983U, // MOVT_D64 |
| 3375 |
536895097U, // MOVT_I |
3375 |
536895097U, // MOVT_I |
| 3376 |
536895097U, // MOVT_I64 |
3376 |
536895097U, // MOVT_I64 |
| 3377 |
536895097U, // MOVT_I_MM |
3377 |
536895097U, // MOVT_I_MM |
| 3378 |
536894777U, // MOVT_S |
3378 |
536894777U, // MOVT_S |
| 3379 |
536894777U, // MOVT_S_MM |
3379 |
536894777U, // MOVT_S_MM |
| 3380 |
536891393U, // MOVZ_I64_D64 |
3380 |
536891393U, // MOVZ_I64_D64 |
| 3381 |
536897287U, // MOVZ_I64_I |
3381 |
536897287U, // MOVZ_I64_I |
| 3382 |
536897287U, // MOVZ_I64_I64 |
3382 |
536897287U, // MOVZ_I64_I64 |
| 3383 |
536894878U, // MOVZ_I64_S |
3383 |
536894878U, // MOVZ_I64_S |
| 3384 |
536891393U, // MOVZ_I_D32 |
3384 |
536891393U, // MOVZ_I_D32 |
| 3385 |
536891393U, // MOVZ_I_D32_MM |
3385 |
536891393U, // MOVZ_I_D32_MM |
| 3386 |
536891393U, // MOVZ_I_D64 |
3386 |
536891393U, // MOVZ_I_D64 |
| 3387 |
536897287U, // MOVZ_I_I |
3387 |
536897287U, // MOVZ_I_I |
| 3388 |
536897287U, // MOVZ_I_I64 |
3388 |
536897287U, // MOVZ_I_I64 |
| 3389 |
536897287U, // MOVZ_I_MM |
3389 |
536897287U, // MOVZ_I_MM |
| 3390 |
536894878U, // MOVZ_I_S |
3390 |
536894878U, // MOVZ_I_S |
| 3391 |
536894878U, // MOVZ_I_S_MM |
3391 |
536894878U, // MOVZ_I_S_MM |
| 3392 |
18351U, // MSUB |
3392 |
18351U, // MSUB |
| 3393 |
570444374U, // MSUBF_D |
3393 |
570444374U, // MSUBF_D |
| 3394 |
570444374U, // MSUBF_D_MMR6 |
3394 |
570444374U, // MSUBF_D_MMR6 |
| 3395 |
570448842U, // MSUBF_S |
3395 |
570448842U, // MSUBF_S |
| 3396 |
570448842U, // MSUBF_S_MMR6 |
3396 |
570448842U, // MSUBF_S_MMR6 |
| 3397 |
570446430U, // MSUBR_Q_H |
3397 |
570446430U, // MSUBR_Q_H |
| 3398 |
570450541U, // MSUBR_Q_W |
3398 |
570450541U, // MSUBR_Q_W |
| 3399 |
24209U, // MSUBU |
3399 |
24209U, // MSUBU |
| 3400 |
536895121U, // MSUBU_DSP |
3400 |
536895121U, // MSUBU_DSP |
| 3401 |
536895121U, // MSUBU_DSP_MM |
3401 |
536895121U, // MSUBU_DSP_MM |
| 3402 |
24209U, // MSUBU_MM |
3402 |
24209U, // MSUBU_MM |
| 3403 |
570443242U, // MSUBV_B |
3403 |
570443242U, // MSUBV_B |
| 3404 |
570445673U, // MSUBV_D |
3404 |
570445673U, // MSUBV_D |
| 3405 |
570447031U, // MSUBV_H |
3405 |
570447031U, // MSUBV_H |
| 3406 |
570451498U, // MSUBV_W |
3406 |
570451498U, // MSUBV_W |
| 3407 |
536889648U, // MSUB_D32 |
3407 |
536889648U, // MSUB_D32 |
| 3408 |
536889648U, // MSUB_D32_MM |
3408 |
536889648U, // MSUB_D32_MM |
| 3409 |
536889648U, // MSUB_D64 |
3409 |
536889648U, // MSUB_D64 |
| 3410 |
536889263U, // MSUB_DSP |
3410 |
536889263U, // MSUB_DSP |
| 3411 |
536889263U, // MSUB_DSP_MM |
3411 |
536889263U, // MSUB_DSP_MM |
| 3412 |
18351U, // MSUB_MM |
3412 |
18351U, // MSUB_MM |
| 3413 |
570446401U, // MSUB_Q_H |
3413 |
570446401U, // MSUB_Q_H |
| 3414 |
570450512U, // MSUB_Q_W |
3414 |
570450512U, // MSUB_Q_W |
| 3415 |
536894267U, // MSUB_S |
3415 |
536894267U, // MSUB_S |
| 3416 |
536894267U, // MSUB_S_MM |
3416 |
536894267U, // MSUB_S_MM |
| 3417 |
2752561207U, // MTC0 |
3417 |
2752561207U, // MTC0 |
| 3418 |
2752561207U, // MTC0_MMR6 |
3418 |
2752561207U, // MTC0_MMR6 |
| 3419 |
17875076U, // MTC1 |
3419 |
17875076U, // MTC1 |
| 3420 |
17875076U, // MTC1_D64 |
3420 |
17875076U, // MTC1_D64 |
| 3421 |
17875076U, // MTC1_D64_MM |
3421 |
17875076U, // MTC1_D64_MM |
| 3422 |
17875076U, // MTC1_MM |
3422 |
17875076U, // MTC1_MM |
| 3423 |
17875076U, // MTC1_MMR6 |
3423 |
17875076U, // MTC1_MMR6 |
| 3424 |
2752561500U, // MTC2 |
3424 |
2752561500U, // MTC2 |
| 3425 |
17875292U, // MTC2_MMR6 |
3425 |
17875292U, // MTC2_MMR6 |
| 3426 |
2752561185U, // MTGC0 |
3426 |
2752561185U, // MTGC0 |
| 3427 |
2752561185U, // MTGC0_MM |
3427 |
2752561185U, // MTGC0_MM |
| 3428 |
2752561199U, // MTHC0_MMR6 |
3428 |
2752561199U, // MTHC0_MMR6 |
| 3429 |
17924214U, // MTHC1_D32 |
3429 |
17924214U, // MTHC1_D32 |
| 3430 |
17924214U, // MTHC1_D32_MM |
3430 |
17924214U, // MTHC1_D32_MM |
| 3431 |
17924214U, // MTHC1_D64 |
3431 |
17924214U, // MTHC1_D64 |
| 3432 |
17924214U, // MTHC1_D64_MM |
3432 |
17924214U, // MTHC1_D64_MM |
| 3433 |
17875278U, // MTHC2_MMR6 |
3433 |
17875278U, // MTHC2_MMR6 |
| 3434 |
2752561176U, // MTHGC0 |
3434 |
2752561176U, // MTHGC0 |
| 3435 |
2752561176U, // MTHGC0_MM |
3435 |
2752561176U, // MTHGC0_MM |
| 3436 |
546680U, // MTHI |
3436 |
546680U, // MTHI |
| 3437 |
546680U, // MTHI64 |
3437 |
546680U, // MTHI64 |
| 3438 |
17880952U, // MTHI_DSP |
3438 |
17880952U, // MTHI_DSP |
| 3439 |
17880952U, // MTHI_DSP_MM |
3439 |
17880952U, // MTHI_DSP_MM |
| 3440 |
546680U, // MTHI_MM |
3440 |
546680U, // MTHI_MM |
| 3441 |
17881536U, // MTHLIP |
3441 |
17881536U, // MTHLIP |
| 3442 |
17881536U, // MTHLIP_MM |
3442 |
17881536U, // MTHLIP_MM |
| 3443 |
547219U, // MTLO |
3443 |
547219U, // MTLO |
| 3444 |
547219U, // MTLO64 |
3444 |
547219U, // MTLO64 |
| 3445 |
17881491U, // MTLO_DSP |
3445 |
17881491U, // MTLO_DSP |
| 3446 |
17881491U, // MTLO_DSP_MM |
3446 |
17881491U, // MTLO_DSP_MM |
| 3447 |
547219U, // MTLO_MM |
3447 |
547219U, // MTLO_MM |
| 3448 |
540739U, // MTM0 |
3448 |
540739U, // MTM0 |
| 3449 |
540864U, // MTM1 |
3449 |
540864U, // MTM1 |
| 3450 |
541038U, // MTM2 |
3450 |
541038U, // MTM2 |
| 3451 |
540745U, // MTP0 |
3451 |
540745U, // MTP0 |
| 3452 |
540870U, // MTP1 |
3452 |
540870U, // MTP1 |
| 3453 |
541044U, // MTP2 |
3453 |
541044U, // MTP2 |
| 3454 |
68213523U, // MTTR |
3454 |
68213523U, // MTTR |
| 3455 |
536893249U, // MUH |
3455 |
536893249U, // MUH |
| 3456 |
536895193U, // MUHU |
3456 |
536895193U, // MUHU |
| 3457 |
536895193U, // MUHU_MMR6 |
3457 |
536895193U, // MUHU_MMR6 |
| 3458 |
536893249U, // MUH_MMR6 |
3458 |
536893249U, // MUH_MMR6 |
| 3459 |
536893715U, // MUL |
3459 |
536893715U, // MUL |
| 3460 |
536893596U, // MULEQ_S_W_PHL |
3460 |
536893596U, // MULEQ_S_W_PHL |
| 3461 |
536893596U, // MULEQ_S_W_PHL_MM |
3461 |
536893596U, // MULEQ_S_W_PHL_MM |
| 3462 |
536894157U, // MULEQ_S_W_PHR |
3462 |
536894157U, // MULEQ_S_W_PHR |
| 3463 |
536894157U, // MULEQ_S_W_PHR_MM |
3463 |
536894157U, // MULEQ_S_W_PHR_MM |
| 3464 |
536893473U, // MULEU_S_PH_QBL |
3464 |
536893473U, // MULEU_S_PH_QBL |
| 3465 |
536893473U, // MULEU_S_PH_QBL_MM |
3465 |
536893473U, // MULEU_S_PH_QBL_MM |
| 3466 |
536894059U, // MULEU_S_PH_QBR |
3466 |
536894059U, // MULEU_S_PH_QBR |
| 3467 |
536894059U, // MULEU_S_PH_QBR_MM |
3467 |
536894059U, // MULEU_S_PH_QBR_MM |
| 3468 |
536893009U, // MULQ_RS_PH |
3468 |
536893009U, // MULQ_RS_PH |
| 3469 |
536893009U, // MULQ_RS_PH_MM |
3469 |
536893009U, // MULQ_RS_PH_MM |
| 3470 |
536896659U, // MULQ_RS_W |
3470 |
536896659U, // MULQ_RS_W |
| 3471 |
536896659U, // MULQ_RS_W_MMR2 |
3471 |
536896659U, // MULQ_RS_W_MMR2 |
| 3472 |
536892953U, // MULQ_S_PH |
3472 |
536892953U, // MULQ_S_PH |
| 3473 |
536892953U, // MULQ_S_PH_MMR2 |
3473 |
536892953U, // MULQ_S_PH_MMR2 |
| 3474 |
536896518U, // MULQ_S_W |
3474 |
536896518U, // MULQ_S_W |
| 3475 |
536896518U, // MULQ_S_W_MMR2 |
3475 |
536896518U, // MULQ_S_W_MMR2 |
| 3476 |
536894976U, // MULR_PS64 |
3476 |
536894976U, // MULR_PS64 |
| 3477 |
536892020U, // MULR_Q_H |
3477 |
536892020U, // MULR_Q_H |
| 3478 |
536896131U, // MULR_Q_W |
3478 |
536896131U, // MULR_Q_W |
| 3479 |
536893155U, // MULSAQ_S_W_PH |
3479 |
536893155U, // MULSAQ_S_W_PH |
| 3480 |
536893155U, // MULSAQ_S_W_PH_MM |
3480 |
536893155U, // MULSAQ_S_W_PH_MM |
| 3481 |
536893130U, // MULSA_W_PH |
3481 |
536893130U, // MULSA_W_PH |
| 3482 |
536893130U, // MULSA_W_PH_MMR2 |
3482 |
536893130U, // MULSA_W_PH_MMR2 |
| 3483 |
24157U, // MULT |
3483 |
24157U, // MULT |
| 3484 |
536895313U, // MULTU_DSP |
3484 |
536895313U, // MULTU_DSP |
| 3485 |
536895313U, // MULTU_DSP_MM |
3485 |
536895313U, // MULTU_DSP_MM |
| 3486 |
536895069U, // MULT_DSP |
3486 |
536895069U, // MULT_DSP |
| 3487 |
536895069U, // MULT_DSP_MM |
3487 |
536895069U, // MULT_DSP_MM |
| 3488 |
24157U, // MULT_MM |
3488 |
24157U, // MULT_MM |
| 3489 |
24401U, // MULTu |
3489 |
24401U, // MULTu |
| 3490 |
24401U, // MULTu_MM |
3490 |
24401U, // MULTu_MM |
| 3491 |
536895230U, // MULU |
3491 |
536895230U, // MULU |
| 3492 |
536895230U, // MULU_MMR6 |
3492 |
536895230U, // MULU_MMR6 |
| 3493 |
536888846U, // MULV_B |
3493 |
536888846U, // MULV_B |
| 3494 |
536891285U, // MULV_D |
3494 |
536891285U, // MULV_D |
| 3495 |
536892635U, // MULV_H |
3495 |
536892635U, // MULV_H |
| 3496 |
536897110U, // MULV_W |
3496 |
536897110U, // MULV_W |
| 3497 |
536893715U, // MUL_MM |
3497 |
536893715U, // MUL_MM |
| 3498 |
536893715U, // MUL_MMR6 |
3498 |
536893715U, // MUL_MMR6 |
| 3499 |
536892826U, // MUL_PH |
3499 |
536892826U, // MUL_PH |
| 3500 |
536892826U, // MUL_PH_MMR2 |
3500 |
536892826U, // MUL_PH_MMR2 |
| 3501 |
536891989U, // MUL_Q_H |
3501 |
536891989U, // MUL_Q_H |
| 3502 |
536896100U, // MUL_Q_W |
3502 |
536896100U, // MUL_Q_W |
| 3503 |
536893715U, // MUL_R6 |
3503 |
536893715U, // MUL_R6 |
| 3504 |
536892921U, // MUL_S_PH |
3504 |
536892921U, // MUL_S_PH |
| 3505 |
536892921U, // MUL_S_PH_MMR2 |
3505 |
536892921U, // MUL_S_PH_MMR2 |
| 3506 |
546674U, // Mfhi16 |
3506 |
546674U, // Mfhi16 |
| 3507 |
547206U, // Mflo16 |
3507 |
547206U, // Mflo16 |
| 3508 |
20727U, // Move32R16 |
3508 |
20727U, // Move32R16 |
| 3509 |
20727U, // MoveR3216 |
3509 |
20727U, // MoveR3216 |
| 3510 |
17173U, // NLOC_B |
3510 |
17173U, // NLOC_B |
| 3511 |
18753U, // NLOC_D |
3511 |
18753U, // NLOC_D |
| 3512 |
20810U, // NLOC_H |
3512 |
20810U, // NLOC_H |
| 3513 |
24646U, // NLOC_W |
3513 |
24646U, // NLOC_W |
| 3514 |
17181U, // NLZC_B |
3514 |
17181U, // NLZC_B |
| 3515 |
18761U, // NLZC_D |
3515 |
18761U, // NLZC_D |
| 3516 |
20818U, // NLZC_H |
3516 |
20818U, // NLZC_H |
| 3517 |
24654U, // NLZC_W |
3517 |
24654U, // NLZC_W |
| 3518 |
536889698U, // NMADD_D32 |
3518 |
536889698U, // NMADD_D32 |
| 3519 |
536889698U, // NMADD_D32_MM |
3519 |
536889698U, // NMADD_D32_MM |
| 3520 |
536889698U, // NMADD_D64 |
3520 |
536889698U, // NMADD_D64 |
| 3521 |
536894284U, // NMADD_S |
3521 |
536894284U, // NMADD_S |
| 3522 |
536894284U, // NMADD_S_MM |
3522 |
536894284U, // NMADD_S_MM |
| 3523 |
536889656U, // NMSUB_D32 |
3523 |
536889656U, // NMSUB_D32 |
| 3524 |
536889656U, // NMSUB_D32_MM |
3524 |
536889656U, // NMSUB_D32_MM |
| 3525 |
536889656U, // NMSUB_D64 |
3525 |
536889656U, // NMSUB_D64 |
| 3526 |
536894266U, // NMSUB_S |
3526 |
536894266U, // NMSUB_S |
| 3527 |
536894266U, // NMSUB_S_MM |
3527 |
536894266U, // NMSUB_S_MM |
| 3528 |
536894182U, // NOR |
3528 |
536894182U, // NOR |
| 3529 |
536894182U, // NOR64 |
3529 |
536894182U, // NOR64 |
| 3530 |
536888254U, // NORI_B |
3530 |
536888254U, // NORI_B |
| 3531 |
536894182U, // NOR_MM |
3531 |
536894182U, // NOR_MM |
| 3532 |
536894182U, // NOR_MMR6 |
3532 |
536894182U, // NOR_MMR6 |
| 3533 |
536895362U, // NOR_V |
3533 |
536895362U, // NOR_V |
| 3534 |
16960U, // NOT16_MM |
3534 |
16960U, // NOT16_MM |
| 3535 |
16960U, // NOT16_MMR6 |
3535 |
16960U, // NOT16_MMR6 |
| 3536 |
20761U, // NegRxRy16 |
3536 |
20761U, // NegRxRy16 |
| 3537 |
24173U, // NotRxRy16 |
3537 |
24173U, // NotRxRy16 |
| 3538 |
536894183U, // OR |
3538 |
536894183U, // OR |
| 3539 |
20021809U, // OR16_MM |
3539 |
20021809U, // OR16_MM |
| 3540 |
20021809U, // OR16_MMR6 |
3540 |
20021809U, // OR16_MMR6 |
| 3541 |
536894183U, // OR64 |
3541 |
536894183U, // OR64 |
| 3542 |
536888255U, // ORI_B |
3542 |
536888255U, // ORI_B |
| 3543 |
536893348U, // ORI_MMR6 |
3543 |
536893348U, // ORI_MMR6 |
| 3544 |
536894183U, // OR_MM |
3544 |
536894183U, // OR_MM |
| 3545 |
536894183U, // OR_MMR6 |
3545 |
536894183U, // OR_MMR6 |
| 3546 |
536895363U, // OR_V |
3546 |
536895363U, // OR_V |
| 3547 |
536893348U, // ORi |
3547 |
536893348U, // ORi |
| 3548 |
536893348U, // ORi64 |
3548 |
536893348U, // ORi64 |
| 3549 |
536893348U, // ORi_MM |
3549 |
536893348U, // ORi_MM |
| 3550 |
33577703U, // OrRxRxRy16 |
3550 |
33577703U, // OrRxRxRy16 |
| 3551 |
536892815U, // PACKRL_PH |
3551 |
536892815U, // PACKRL_PH |
| 3552 |
536892815U, // PACKRL_PH_MM |
3552 |
536892815U, // PACKRL_PH_MM |
| 3553 |
10542U, // PAUSE |
3553 |
10542U, // PAUSE |
| 3554 |
10542U, // PAUSE_MM |
3554 |
10542U, // PAUSE_MM |
| 3555 |
10542U, // PAUSE_MMR6 |
3555 |
10542U, // PAUSE_MMR6 |
| 3556 |
536888828U, // PCKEV_B |
3556 |
536888828U, // PCKEV_B |
| 3557 |
536891259U, // PCKEV_D |
3557 |
536891259U, // PCKEV_D |
| 3558 |
536892617U, // PCKEV_H |
3558 |
536892617U, // PCKEV_H |
| 3559 |
536897084U, // PCKEV_W |
3559 |
536897084U, // PCKEV_W |
| 3560 |
536888108U, // PCKOD_B |
3560 |
536888108U, // PCKOD_B |
| 3561 |
536889714U, // PCKOD_D |
3561 |
536889714U, // PCKOD_D |
| 3562 |
536891745U, // PCKOD_H |
3562 |
536891745U, // PCKOD_H |
| 3563 |
536895607U, // PCKOD_W |
3563 |
536895607U, // PCKOD_W |
| 3564 |
17700U, // PCNT_B |
3564 |
17700U, // PCNT_B |
| 3565 |
20019U, // PCNT_D |
3565 |
20019U, // PCNT_D |
| 3566 |
21437U, // PCNT_H |
3566 |
21437U, // PCNT_H |
| 3567 |
25842U, // PCNT_W |
3567 |
25842U, // PCNT_W |
| 3568 |
536892779U, // PICK_PH |
3568 |
536892779U, // PICK_PH |
| 3569 |
536892779U, // PICK_PH_MM |
3569 |
536892779U, // PICK_PH_MM |
| 3570 |
536888987U, // PICK_QB |
3570 |
536888987U, // PICK_QB |
| 3571 |
536888987U, // PICK_QB_MM |
3571 |
536888987U, // PICK_QB_MM |
| 3572 |
536894943U, // PLL_PS64 |
3572 |
536894943U, // PLL_PS64 |
| 3573 |
536894985U, // PLU_PS64 |
3573 |
536894985U, // PLU_PS64 |
| 3574 |
22990U, // POP |
3574 |
22990U, // POP |
| 3575 |
22592U, // PRECEQU_PH_QBL |
3575 |
22592U, // PRECEQU_PH_QBL |
| 3576 |
17046U, // PRECEQU_PH_QBLA |
3576 |
17046U, // PRECEQU_PH_QBLA |
| 3577 |
17046U, // PRECEQU_PH_QBLA_MM |
3577 |
17046U, // PRECEQU_PH_QBLA_MM |
| 3578 |
22592U, // PRECEQU_PH_QBL_MM |
3578 |
22592U, // PRECEQU_PH_QBL_MM |
| 3579 |
23178U, // PRECEQU_PH_QBR |
3579 |
23178U, // PRECEQU_PH_QBR |
| 3580 |
17084U, // PRECEQU_PH_QBRA |
3580 |
17084U, // PRECEQU_PH_QBRA |
| 3581 |
17084U, // PRECEQU_PH_QBRA_MM |
3581 |
17084U, // PRECEQU_PH_QBRA_MM |
| 3582 |
23178U, // PRECEQU_PH_QBR_MM |
3582 |
23178U, // PRECEQU_PH_QBR_MM |
| 3583 |
22657U, // PRECEQ_W_PHL |
3583 |
22657U, // PRECEQ_W_PHL |
| 3584 |
22657U, // PRECEQ_W_PHL_MM |
3584 |
22657U, // PRECEQ_W_PHL_MM |
| 3585 |
23218U, // PRECEQ_W_PHR |
3585 |
23218U, // PRECEQ_W_PHR |
| 3586 |
23218U, // PRECEQ_W_PHR_MM |
3586 |
23218U, // PRECEQ_W_PHR_MM |
| 3587 |
22577U, // PRECEU_PH_QBL |
3587 |
22577U, // PRECEU_PH_QBL |
| 3588 |
17030U, // PRECEU_PH_QBLA |
3588 |
17030U, // PRECEU_PH_QBLA |
| 3589 |
17030U, // PRECEU_PH_QBLA_MM |
3589 |
17030U, // PRECEU_PH_QBLA_MM |
| 3590 |
22577U, // PRECEU_PH_QBL_MM |
3590 |
22577U, // PRECEU_PH_QBL_MM |
| 3591 |
23163U, // PRECEU_PH_QBR |
3591 |
23163U, // PRECEU_PH_QBR |
| 3592 |
17068U, // PRECEU_PH_QBRA |
3592 |
17068U, // PRECEU_PH_QBRA |
| 3593 |
17068U, // PRECEU_PH_QBRA_MM |
3593 |
17068U, // PRECEU_PH_QBRA_MM |
| 3594 |
23163U, // PRECEU_PH_QBR_MM |
3594 |
23163U, // PRECEU_PH_QBR_MM |
| 3595 |
536892731U, // PRECRQU_S_QB_PH |
3595 |
536892731U, // PRECRQU_S_QB_PH |
| 3596 |
536892731U, // PRECRQU_S_QB_PH_MM |
3596 |
536892731U, // PRECRQU_S_QB_PH_MM |
| 3597 |
536895750U, // PRECRQ_PH_W |
3597 |
536895750U, // PRECRQ_PH_W |
| 3598 |
536895750U, // PRECRQ_PH_W_MM |
3598 |
536895750U, // PRECRQ_PH_W_MM |
| 3599 |
536892704U, // PRECRQ_QB_PH |
3599 |
536892704U, // PRECRQ_QB_PH |
| 3600 |
536892704U, // PRECRQ_QB_PH_MM |
3600 |
536892704U, // PRECRQ_QB_PH_MM |
| 3601 |
536895781U, // PRECRQ_RS_PH_W |
3601 |
536895781U, // PRECRQ_RS_PH_W |
| 3602 |
536895781U, // PRECRQ_RS_PH_W_MM |
3602 |
536895781U, // PRECRQ_RS_PH_W_MM |
| 3603 |
536892718U, // PRECR_QB_PH |
3603 |
536892718U, // PRECR_QB_PH |
| 3604 |
536892718U, // PRECR_QB_PH_MMR2 |
3604 |
536892718U, // PRECR_QB_PH_MMR2 |
| 3605 |
536895734U, // PRECR_SRA_PH_W |
3605 |
536895734U, // PRECR_SRA_PH_W |
| 3606 |
536895734U, // PRECR_SRA_PH_W_MMR2 |
3606 |
536895734U, // PRECR_SRA_PH_W_MMR2 |
| 3607 |
536895763U, // PRECR_SRA_R_PH_W |
3607 |
536895763U, // PRECR_SRA_R_PH_W |
| 3608 |
536895763U, // PRECR_SRA_R_PH_W_MMR2 |
3608 |
536895763U, // PRECR_SRA_R_PH_W_MMR2 |
| 3609 |
5394701U, // PREF |
3609 |
5394701U, // PREF |
| 3610 |
5394554U, // PREFE |
3610 |
5394554U, // PREFE |
| 3611 |
5394554U, // PREFE_MM |
3611 |
5394554U, // PREFE_MM |
| 3612 |
389179042U, // PREFX_MM |
3612 |
389179042U, // PREFX_MM |
| 3613 |
5394701U, // PREF_MM |
3613 |
5394701U, // PREF_MM |
| 3614 |
5394701U, // PREF_MMR6 |
3614 |
5394701U, // PREF_MMR6 |
| 3615 |
5394701U, // PREF_R6 |
3615 |
5394701U, // PREF_R6 |
| 3616 |
536891464U, // PREPEND |
3616 |
536891464U, // PREPEND |
| 3617 |
536891464U, // PREPEND_MMR2 |
3617 |
536891464U, // PREPEND_MMR2 |
| 3618 |
536894959U, // PUL_PS64 |
3618 |
536894959U, // PUL_PS64 |
| 3619 |
536894993U, // PUU_PS64 |
3619 |
536894993U, // PUU_PS64 |
| 3620 |
18327U, // RADDU_W_QB |
3620 |
18327U, // RADDU_W_QB |
| 3621 |
18327U, // RADDU_W_QB_MM |
3621 |
18327U, // RADDU_W_QB_MM |
| 3622 |
184572415U, // RDDSP |
3622 |
184572415U, // RDDSP |
| 3623 |
402676223U, // RDDSP_MM |
3623 |
402676223U, // RDDSP_MM |
| 3624 |
536894233U, // RDHWR |
3624 |
536894233U, // RDHWR |
| 3625 |
536894233U, // RDHWR64 |
3625 |
536894233U, // RDHWR64 |
| 3626 |
536894233U, // RDHWR_MM |
3626 |
536894233U, // RDHWR_MM |
| 3627 |
536894233U, // RDHWR_MMR6 |
3627 |
536894233U, // RDHWR_MMR6 |
| 3628 |
23286U, // RDPGPR_MMR6 |
3628 |
23286U, // RDPGPR_MMR6 |
| 3629 |
19415U, // RECIP_D32 |
3629 |
19415U, // RECIP_D32 |
| 3630 |
19415U, // RECIP_D32_MM |
3630 |
19415U, // RECIP_D32_MM |
| 3631 |
19415U, // RECIP_D64 |
3631 |
19415U, // RECIP_D64 |
| 3632 |
19415U, // RECIP_D64_MM |
3632 |
19415U, // RECIP_D64_MM |
| 3633 |
23664U, // RECIP_S |
3633 |
23664U, // RECIP_S |
| 3634 |
23664U, // RECIP_S_MM |
3634 |
23664U, // RECIP_S_MM |
| 3635 |
22158U, // REPLV_PH |
3635 |
22158U, // REPLV_PH |
| 3636 |
22158U, // REPLV_PH_MM |
3636 |
22158U, // REPLV_PH_MM |
| 3637 |
18307U, // REPLV_QB |
3637 |
18307U, // REPLV_QB |
| 3638 |
18307U, // REPLV_QB_MM |
3638 |
18307U, // REPLV_QB_MM |
| 3639 |
21885U, // REPL_PH |
3639 |
21885U, // REPL_PH |
| 3640 |
21885U, // REPL_PH_MM |
3640 |
21885U, // REPL_PH_MM |
| 3641 |
419448493U, // REPL_QB |
3641 |
419448493U, // REPL_QB |
| 3642 |
419448493U, // REPL_QB_MM |
3642 |
419448493U, // REPL_QB_MM |
| 3643 |
20028U, // RINT_D |
3643 |
20028U, // RINT_D |
| 3644 |
20028U, // RINT_D_MMR6 |
3644 |
20028U, // RINT_D_MMR6 |
| 3645 |
23848U, // RINT_S |
3645 |
23848U, // RINT_S |
| 3646 |
23848U, // RINT_S_MMR6 |
3646 |
23848U, // RINT_S_MMR6 |
| 3647 |
536894221U, // ROTR |
3647 |
536894221U, // ROTR |
| 3648 |
536895464U, // ROTRV |
3648 |
536895464U, // ROTRV |
| 3649 |
536895464U, // ROTRV_MM |
3649 |
536895464U, // ROTRV_MM |
| 3650 |
536894221U, // ROTR_MM |
3650 |
536894221U, // ROTR_MM |
| 3651 |
19224U, // ROUND_L_D64 |
3651 |
19224U, // ROUND_L_D64 |
| 3652 |
19224U, // ROUND_L_D_MMR6 |
3652 |
19224U, // ROUND_L_D_MMR6 |
| 3653 |
23556U, // ROUND_L_S |
3653 |
23556U, // ROUND_L_S |
| 3654 |
23556U, // ROUND_L_S_MMR6 |
3654 |
23556U, // ROUND_L_S_MMR6 |
| 3655 |
20399U, // ROUND_W_D32 |
3655 |
20399U, // ROUND_W_D32 |
| 3656 |
20399U, // ROUND_W_D64 |
3656 |
20399U, // ROUND_W_D64 |
| 3657 |
20399U, // ROUND_W_D_MMR6 |
3657 |
20399U, // ROUND_W_D_MMR6 |
| 3658 |
20399U, // ROUND_W_MM |
3658 |
20399U, // ROUND_W_MM |
| 3659 |
23898U, // ROUND_W_S |
3659 |
23898U, // ROUND_W_S |
| 3660 |
23898U, // ROUND_W_S_MM |
3660 |
23898U, // ROUND_W_S_MM |
| 3661 |
23898U, // ROUND_W_S_MMR6 |
3661 |
23898U, // ROUND_W_S_MMR6 |
| 3662 |
20056U, // RSQRT_D32 |
3662 |
20056U, // RSQRT_D32 |
| 3663 |
20056U, // RSQRT_D32_MM |
3663 |
20056U, // RSQRT_D32_MM |
| 3664 |
20056U, // RSQRT_D64 |
3664 |
20056U, // RSQRT_D64 |
| 3665 |
20056U, // RSQRT_D64_MM |
3665 |
20056U, // RSQRT_D64_MM |
| 3666 |
23856U, // RSQRT_S |
3666 |
23856U, // RSQRT_S |
| 3667 |
23856U, // RSQRT_S_MM |
3667 |
23856U, // RSQRT_S_MM |
| 3668 |
0U, // Restore16 |
3668 |
0U, // Restore16 |
| 3669 |
0U, // RestoreX16 |
3669 |
0U, // RestoreX16 |
| 3670 |
8405633U, // SAA |
3670 |
8405633U, // SAA |
| 3671 |
8409105U, // SAAD |
3671 |
8409105U, // SAAD |
| 3672 |
536888537U, // SAT_S_B |
3672 |
536888537U, // SAT_S_B |
| 3673 |
536890704U, // SAT_S_D |
3673 |
536890704U, // SAT_S_D |
| 3674 |
536892263U, // SAT_S_H |
3674 |
536892263U, // SAT_S_H |
| 3675 |
536896568U, // SAT_S_W |
3675 |
536896568U, // SAT_S_W |
| 3676 |
536888764U, // SAT_U_B |
3676 |
536888764U, // SAT_U_B |
| 3677 |
536891183U, // SAT_U_D |
3677 |
536891183U, // SAT_U_D |
| 3678 |
536892553U, // SAT_U_H |
3678 |
536892553U, // SAT_U_H |
| 3679 |
536896998U, // SAT_U_W |
3679 |
536896998U, // SAT_U_W |
| 3680 |
50349987U, // SB |
3680 |
50349987U, // SB |
| 3681 |
50348452U, // SB16_MM |
3681 |
50348452U, // SB16_MM |
| 3682 |
50348452U, // SB16_MMR6 |
3682 |
50348452U, // SB16_MMR6 |
| 3683 |
50349987U, // SB64 |
3683 |
50349987U, // SB64 |
| 3684 |
50352232U, // SBE |
3684 |
50352232U, // SBE |
| 3685 |
50352232U, // SBE_MM |
3685 |
50352232U, // SBE_MM |
| 3686 |
50349987U, // SB_MM |
3686 |
50349987U, // SB_MM |
| 3687 |
50349987U, // SB_MMR6 |
3687 |
50349987U, // SB_MMR6 |
| 3688 |
8964190U, // SC |
3688 |
8964190U, // SC |
| 3689 |
8964190U, // SC64 |
3689 |
8964190U, // SC64 |
| 3690 |
8964190U, // SC64_R6 |
3690 |
8964190U, // SC64_R6 |
| 3691 |
8966176U, // SCD |
3691 |
8966176U, // SCD |
| 3692 |
8966176U, // SCD_R6 |
3692 |
8966176U, // SCD_R6 |
| 3693 |
8966253U, // SCE |
3693 |
8966253U, // SCE |
| 3694 |
8966253U, // SCE_MM |
3694 |
8966253U, // SCE_MM |
| 3695 |
8964190U, // SC_MM |
3695 |
8964190U, // SC_MM |
| 3696 |
8964190U, // SC_MMR6 |
3696 |
8964190U, // SC_MMR6 |
| 3697 |
8964190U, // SC_R6 |
3697 |
8964190U, // SC_R6 |
| 3698 |
50352223U, // SD |
3698 |
50352223U, // SD |
| 3699 |
219562U, // SDBBP |
3699 |
219562U, // SDBBP |
| 3700 |
131617U, // SDBBP16_MM |
3700 |
131617U, // SDBBP16_MM |
| 3701 |
131617U, // SDBBP16_MMR6 |
3701 |
131617U, // SDBBP16_MMR6 |
| 3702 |
645546U, // SDBBP_MM |
3702 |
645546U, // SDBBP_MM |
| 3703 |
219562U, // SDBBP_MMR6 |
3703 |
219562U, // SDBBP_MMR6 |
| 3704 |
219562U, // SDBBP_R6 |
3704 |
219562U, // SDBBP_R6 |
| 3705 |
50348124U, // SDC1 |
3705 |
50348124U, // SDC1 |
| 3706 |
50348124U, // SDC164 |
3706 |
50348124U, // SDC164 |
| 3707 |
50348124U, // SDC1_D64_MMR6 |
3707 |
50348124U, // SDC1_D64_MMR6 |
| 3708 |
50348124U, // SDC1_MM_D32 |
3708 |
50348124U, // SDC1_MM_D32 |
| 3709 |
50348124U, // SDC1_MM_D64 |
3709 |
50348124U, // SDC1_MM_D64 |
| 3710 |
50348340U, // SDC2 |
3710 |
50348340U, // SDC2 |
| 3711 |
50348340U, // SDC2_MMR6 |
3711 |
50348340U, // SDC2_MMR6 |
| 3712 |
50348340U, // SDC2_R6 |
3712 |
50348340U, // SDC2_R6 |
| 3713 |
50348425U, // SDC3 |
3713 |
50348425U, // SDC3 |
| 3714 |
26408U, // SDIV |
3714 |
26408U, // SDIV |
| 3715 |
26408U, // SDIV_MM |
3715 |
26408U, // SDIV_MM |
| 3716 |
50354261U, // SDL |
3716 |
50354261U, // SDL |
| 3717 |
50354847U, // SDR |
3717 |
50354847U, // SDR |
| 3718 |
3254796445U, // SDXC1 |
3718 |
3254796445U, // SDXC1 |
| 3719 |
3254796445U, // SDXC164 |
3719 |
3254796445U, // SDXC164 |
| 3720 |
17972U, // SEB |
3720 |
17972U, // SEB |
| 3721 |
17972U, // SEB64 |
3721 |
17972U, // SEB64 |
| 3722 |
17972U, // SEB_MM |
3722 |
17972U, // SEB_MM |
| 3723 |
21773U, // SEH |
3723 |
21773U, // SEH |
| 3724 |
21773U, // SEH64 |
3724 |
21773U, // SEH64 |
| 3725 |
21773U, // SEH_MM |
3725 |
21773U, // SEH_MM |
| 3726 |
536897260U, // SELEQZ |
3726 |
536897260U, // SELEQZ |
| 3727 |
536897260U, // SELEQZ64 |
3727 |
536897260U, // SELEQZ64 |
| 3728 |
536891383U, // SELEQZ_D |
3728 |
536891383U, // SELEQZ_D |
| 3729 |
536891383U, // SELEQZ_D_MMR6 |
3729 |
536891383U, // SELEQZ_D_MMR6 |
| 3730 |
536897260U, // SELEQZ_MMR6 |
3730 |
536897260U, // SELEQZ_MMR6 |
| 3731 |
536894868U, // SELEQZ_S |
3731 |
536894868U, // SELEQZ_S |
| 3732 |
536894868U, // SELEQZ_S_MMR6 |
3732 |
536894868U, // SELEQZ_S_MMR6 |
| 3733 |
536897233U, // SELNEZ |
3733 |
536897233U, // SELNEZ |
| 3734 |
536897233U, // SELNEZ64 |
3734 |
536897233U, // SELNEZ64 |
| 3735 |
536891366U, // SELNEZ_D |
3735 |
536891366U, // SELNEZ_D |
| 3736 |
536891366U, // SELNEZ_D_MMR6 |
3736 |
536891366U, // SELNEZ_D_MMR6 |
| 3737 |
536897233U, // SELNEZ_MMR6 |
3737 |
536897233U, // SELNEZ_MMR6 |
| 3738 |
536894858U, // SELNEZ_S |
3738 |
536894858U, // SELNEZ_S |
| 3739 |
536894858U, // SELNEZ_S_MMR6 |
3739 |
536894858U, // SELNEZ_S_MMR6 |
| 3740 |
570444609U, // SEL_D |
3740 |
570444609U, // SEL_D |
| 3741 |
570444609U, // SEL_D_MMR6 |
3741 |
570444609U, // SEL_D_MMR6 |
| 3742 |
570448941U, // SEL_S |
3742 |
570448941U, // SEL_S |
| 3743 |
570448941U, // SEL_S_MMR6 |
3743 |
570448941U, // SEL_S_MMR6 |
| 3744 |
536894025U, // SEQ |
3744 |
536894025U, // SEQ |
| 3745 |
536893335U, // SEQi |
3745 |
536893335U, // SEQi |
| 3746 |
50353980U, // SH |
3746 |
50353980U, // SH |
| 3747 |
50348504U, // SH16_MM |
3747 |
50348504U, // SH16_MM |
| 3748 |
50348504U, // SH16_MMR6 |
3748 |
50348504U, // SH16_MMR6 |
| 3749 |
50353980U, // SH64 |
3749 |
50353980U, // SH64 |
| 3750 |
50352284U, // SHE |
3750 |
50352284U, // SHE |
| 3751 |
50352284U, // SHE_MM |
3751 |
50352284U, // SHE_MM |
| 3752 |
536888136U, // SHF_B |
3752 |
536888136U, // SHF_B |
| 3753 |
536891773U, // SHF_H |
3753 |
536891773U, // SHF_H |
| 3754 |
536895719U, // SHF_W |
3754 |
536895719U, // SHF_W |
| 3755 |
22924U, // SHILO |
3755 |
22924U, // SHILO |
| 3756 |
24527U, // SHILOV |
3756 |
24527U, // SHILOV |
| 3757 |
24527U, // SHILOV_MM |
3757 |
24527U, // SHILOV_MM |
| 3758 |
22924U, // SHILO_MM |
3758 |
22924U, // SHILO_MM |
| 3759 |
536893060U, // SHLLV_PH |
3759 |
536893060U, // SHLLV_PH |
| 3760 |
536893060U, // SHLLV_PH_MM |
3760 |
536893060U, // SHLLV_PH_MM |
| 3761 |
536889209U, // SHLLV_QB |
3761 |
536889209U, // SHLLV_QB |
| 3762 |
536889209U, // SHLLV_QB_MM |
3762 |
536889209U, // SHLLV_QB_MM |
| 3763 |
536892997U, // SHLLV_S_PH |
3763 |
536892997U, // SHLLV_S_PH |
| 3764 |
536892997U, // SHLLV_S_PH_MM |
3764 |
536892997U, // SHLLV_S_PH_MM |
| 3765 |
536896629U, // SHLLV_S_W |
3765 |
536896629U, // SHLLV_S_W |
| 3766 |
536896629U, // SHLLV_S_W_MM |
3766 |
536896629U, // SHLLV_S_W_MM |
| 3767 |
536892788U, // SHLL_PH |
3767 |
536892788U, // SHLL_PH |
| 3768 |
536892788U, // SHLL_PH_MM |
3768 |
536892788U, // SHLL_PH_MM |
| 3769 |
536888996U, // SHLL_QB |
3769 |
536888996U, // SHLL_QB |
| 3770 |
536888996U, // SHLL_QB_MM |
3770 |
536888996U, // SHLL_QB_MM |
| 3771 |
536892910U, // SHLL_S_PH |
3771 |
536892910U, // SHLL_S_PH |
| 3772 |
536892910U, // SHLL_S_PH_MM |
3772 |
536892910U, // SHLL_S_PH_MM |
| 3773 |
536896469U, // SHLL_S_W |
3773 |
536896469U, // SHLL_S_W |
| 3774 |
536896469U, // SHLL_S_W_MM |
3774 |
536896469U, // SHLL_S_W_MM |
| 3775 |
536893050U, // SHRAV_PH |
3775 |
536893050U, // SHRAV_PH |
| 3776 |
536893050U, // SHRAV_PH_MM |
3776 |
536893050U, // SHRAV_PH_MM |
| 3777 |
536889199U, // SHRAV_QB |
3777 |
536889199U, // SHRAV_QB |
| 3778 |
536889199U, // SHRAV_QB_MMR2 |
3778 |
536889199U, // SHRAV_QB_MMR2 |
| 3779 |
536892898U, // SHRAV_R_PH |
3779 |
536892898U, // SHRAV_R_PH |
| 3780 |
536892898U, // SHRAV_R_PH_MM |
3780 |
536892898U, // SHRAV_R_PH_MM |
| 3781 |
536889097U, // SHRAV_R_QB |
3781 |
536889097U, // SHRAV_R_QB |
| 3782 |
536889097U, // SHRAV_R_QB_MMR2 |
3782 |
536889097U, // SHRAV_R_QB_MMR2 |
| 3783 |
536896224U, // SHRAV_R_W |
3783 |
536896224U, // SHRAV_R_W |
| 3784 |
536896224U, // SHRAV_R_W_MM |
3784 |
536896224U, // SHRAV_R_W_MM |
| 3785 |
536892695U, // SHRA_PH |
3785 |
536892695U, // SHRA_PH |
| 3786 |
536892695U, // SHRA_PH_MM |
3786 |
536892695U, // SHRA_PH_MM |
| 3787 |
536888919U, // SHRA_QB |
3787 |
536888919U, // SHRA_QB |
| 3788 |
536888919U, // SHRA_QB_MMR2 |
3788 |
536888919U, // SHRA_QB_MMR2 |
| 3789 |
536892863U, // SHRA_R_PH |
3789 |
536892863U, // SHRA_R_PH |
| 3790 |
536892863U, // SHRA_R_PH_MM |
3790 |
536892863U, // SHRA_R_PH_MM |
| 3791 |
536889062U, // SHRA_R_QB |
3791 |
536889062U, // SHRA_R_QB |
| 3792 |
536889062U, // SHRA_R_QB_MMR2 |
3792 |
536889062U, // SHRA_R_QB_MMR2 |
| 3793 |
536896182U, // SHRA_R_W |
3793 |
536896182U, // SHRA_R_W |
| 3794 |
536896182U, // SHRA_R_W_MM |
3794 |
536896182U, // SHRA_R_W_MM |
| 3795 |
536893080U, // SHRLV_PH |
3795 |
536893080U, // SHRLV_PH |
| 3796 |
536893080U, // SHRLV_PH_MMR2 |
3796 |
536893080U, // SHRLV_PH_MMR2 |
| 3797 |
536889229U, // SHRLV_QB |
3797 |
536889229U, // SHRLV_QB |
| 3798 |
536889229U, // SHRLV_QB_MM |
3798 |
536889229U, // SHRLV_QB_MM |
| 3799 |
536892806U, // SHRL_PH |
3799 |
536892806U, // SHRL_PH |
| 3800 |
536892806U, // SHRL_PH_MMR2 |
3800 |
536892806U, // SHRL_PH_MMR2 |
| 3801 |
536889014U, // SHRL_QB |
3801 |
536889014U, // SHRL_QB |
| 3802 |
536889014U, // SHRL_QB_MM |
3802 |
536889014U, // SHRL_QB_MM |
| 3803 |
50353980U, // SH_MM |
3803 |
50353980U, // SH_MM |
| 3804 |
50353980U, // SH_MMR6 |
3804 |
50353980U, // SH_MMR6 |
| 3805 |
233633U, // SIGRIE |
3805 |
233633U, // SIGRIE |
| 3806 |
233633U, // SIGRIE_MMR6 |
3806 |
233633U, // SIGRIE_MMR6 |
| 3807 |
1107313503U, // SLDI_B |
3807 |
1107313503U, // SLDI_B |
| 3808 |
1107315344U, // SLDI_D |
3808 |
1107315344U, // SLDI_D |
| 3809 |
1107317140U, // SLDI_H |
3809 |
1107317140U, // SLDI_H |
| 3810 |
1107321167U, // SLDI_W |
3810 |
1107321167U, // SLDI_W |
| 3811 |
1107313445U, // SLD_B |
3811 |
1107313445U, // SLD_B |
| 3812 |
1107315051U, // SLD_D |
3812 |
1107315051U, // SLD_D |
| 3813 |
1107317082U, // SLD_H |
3813 |
1107317082U, // SLD_H |
| 3814 |
1107320944U, // SLD_W |
3814 |
1107320944U, // SLD_W |
| 3815 |
536893648U, // SLL |
3815 |
536893648U, // SLL |
| 3816 |
536887805U, // SLL16_MM |
3816 |
536887805U, // SLL16_MM |
| 3817 |
536887805U, // SLL16_MMR6 |
3817 |
536887805U, // SLL16_MMR6 |
| 3818 |
536893648U, // SLL64_32 |
3818 |
536893648U, // SLL64_32 |
| 3819 |
536893648U, // SLL64_64 |
3819 |
536893648U, // SLL64_64 |
| 3820 |
536888193U, // SLLI_B |
3820 |
536888193U, // SLLI_B |
| 3821 |
536890017U, // SLLI_D |
3821 |
536890017U, // SLLI_D |
| 3822 |
536891813U, // SLLI_H |
3822 |
536891813U, // SLLI_H |
| 3823 |
536895840U, // SLLI_W |
3823 |
536895840U, // SLLI_W |
| 3824 |
536895426U, // SLLV |
3824 |
536895426U, // SLLV |
| 3825 |
536895426U, // SLLV_MM |
3825 |
536895426U, // SLLV_MM |
| 3826 |
536888342U, // SLL_B |
3826 |
536888342U, // SLL_B |
| 3827 |
536890201U, // SLL_D |
3827 |
536890201U, // SLL_D |
| 3828 |
536891929U, // SLL_H |
3828 |
536891929U, // SLL_H |
| 3829 |
536893648U, // SLL_MM |
3829 |
536893648U, // SLL_MM |
| 3830 |
536893648U, // SLL_MMR6 |
3830 |
536893648U, // SLL_MMR6 |
| 3831 |
536895982U, // SLL_W |
3831 |
536895982U, // SLL_W |
| 3832 |
536895058U, // SLT |
3832 |
536895058U, // SLT |
| 3833 |
536895058U, // SLT64 |
3833 |
536895058U, // SLT64 |
| 3834 |
536895058U, // SLT_MM |
3834 |
536895058U, // SLT_MM |
| 3835 |
536893359U, // SLTi |
3835 |
536893359U, // SLTi |
| 3836 |
536893359U, // SLTi64 |
3836 |
536893359U, // SLTi64 |
| 3837 |
536893359U, // SLTi_MM |
3837 |
536893359U, // SLTi_MM |
| 3838 |
536895214U, // SLTiu |
3838 |
536895214U, // SLTiu |
| 3839 |
536895214U, // SLTiu64 |
3839 |
536895214U, // SLTiu64 |
| 3840 |
536895214U, // SLTiu_MM |
3840 |
536895214U, // SLTiu_MM |
| 3841 |
536895300U, // SLTu |
3841 |
536895300U, // SLTu |
| 3842 |
536895300U, // SLTu64 |
3842 |
536895300U, // SLTu64 |
| 3843 |
536895300U, // SLTu_MM |
3843 |
536895300U, // SLTu_MM |
| 3844 |
536891593U, // SNE |
3844 |
536891593U, // SNE |
| 3845 |
536893280U, // SNEi |
3845 |
536893280U, // SNEi |
| 3846 |
1073759192U, // SPLATI_B |
3846 |
1073759192U, // SPLATI_B |
| 3847 |
1073761000U, // SPLATI_D |
3847 |
1073761000U, // SPLATI_D |
| 3848 |
1073762796U, // SPLATI_H |
3848 |
1073762796U, // SPLATI_H |
| 3849 |
1073766823U, // SPLATI_W |
3849 |
1073766823U, // SPLATI_W |
| 3850 |
1073759507U, // SPLAT_B |
3850 |
1073759507U, // SPLAT_B |
| 3851 |
1073761713U, // SPLAT_D |
3851 |
1073761713U, // SPLAT_D |
| 3852 |
1073763244U, // SPLAT_H |
3852 |
1073763244U, // SPLAT_H |
| 3853 |
1073767615U, // SPLAT_W |
3853 |
1073767615U, // SPLAT_W |
| 3854 |
536888014U, // SRA |
3854 |
536888014U, // SRA |
| 3855 |
536888151U, // SRAI_B |
3855 |
536888151U, // SRAI_B |
| 3856 |
536889992U, // SRAI_D |
3856 |
536889992U, // SRAI_D |
| 3857 |
536891788U, // SRAI_H |
3857 |
536891788U, // SRAI_H |
| 3858 |
536895815U, // SRAI_W |
3858 |
536895815U, // SRAI_W |
| 3859 |
536888227U, // SRARI_B |
3859 |
536888227U, // SRARI_B |
| 3860 |
536890051U, // SRARI_D |
3860 |
536890051U, // SRARI_D |
| 3861 |
536891847U, // SRARI_H |
3861 |
536891847U, // SRARI_H |
| 3862 |
536895874U, // SRARI_W |
3862 |
536895874U, // SRARI_W |
| 3863 |
536888380U, // SRAR_B |
3863 |
536888380U, // SRAR_B |
| 3864 |
536890440U, // SRAR_D |
3864 |
536890440U, // SRAR_D |
| 3865 |
536892044U, // SRAR_H |
3865 |
536892044U, // SRAR_H |
| 3866 |
536896246U, // SRAR_W |
3866 |
536896246U, // SRAR_W |
| 3867 |
536895405U, // SRAV |
3867 |
536895405U, // SRAV |
| 3868 |
536895405U, // SRAV_MM |
3868 |
536895405U, // SRAV_MM |
| 3869 |
536888078U, // SRA_B |
3869 |
536888078U, // SRA_B |
| 3870 |
536889624U, // SRA_D |
3870 |
536889624U, // SRA_D |
| 3871 |
536891715U, // SRA_H |
3871 |
536891715U, // SRA_H |
| 3872 |
536888014U, // SRA_MM |
3872 |
536888014U, // SRA_MM |
| 3873 |
536895534U, // SRA_W |
3873 |
536895534U, // SRA_W |
| 3874 |
536893676U, // SRL |
3874 |
536893676U, // SRL |
| 3875 |
536887812U, // SRL16_MM |
3875 |
536887812U, // SRL16_MM |
| 3876 |
536887812U, // SRL16_MMR6 |
3876 |
536887812U, // SRL16_MMR6 |
| 3877 |
536888201U, // SRLI_B |
3877 |
536888201U, // SRLI_B |
| 3878 |
536890025U, // SRLI_D |
3878 |
536890025U, // SRLI_D |
| 3879 |
536891821U, // SRLI_H |
3879 |
536891821U, // SRLI_H |
| 3880 |
536895848U, // SRLI_W |
3880 |
536895848U, // SRLI_W |
| 3881 |
536888245U, // SRLRI_B |
3881 |
536888245U, // SRLRI_B |
| 3882 |
536890069U, // SRLRI_D |
3882 |
536890069U, // SRLRI_D |
| 3883 |
536891865U, // SRLRI_H |
3883 |
536891865U, // SRLRI_H |
| 3884 |
536895892U, // SRLRI_W |
3884 |
536895892U, // SRLRI_W |
| 3885 |
536888396U, // SRLR_B |
3885 |
536888396U, // SRLR_B |
| 3886 |
536890456U, // SRLR_D |
3886 |
536890456U, // SRLR_D |
| 3887 |
536892060U, // SRLR_H |
3887 |
536892060U, // SRLR_H |
| 3888 |
536896262U, // SRLR_W |
3888 |
536896262U, // SRLR_W |
| 3889 |
536895433U, // SRLV |
3889 |
536895433U, // SRLV |
| 3890 |
536895433U, // SRLV_MM |
3890 |
536895433U, // SRLV_MM |
| 3891 |
536888349U, // SRL_B |
3891 |
536888349U, // SRL_B |
| 3892 |
536890226U, // SRL_D |
3892 |
536890226U, // SRL_D |
| 3893 |
536891936U, // SRL_H |
3893 |
536891936U, // SRL_H |
| 3894 |
536893676U, // SRL_MM |
3894 |
536893676U, // SRL_MM |
| 3895 |
536896007U, // SRL_W |
3895 |
536896007U, // SRL_W |
| 3896 |
10607U, // SSNOP |
3896 |
10607U, // SSNOP |
| 3897 |
10607U, // SSNOP_MM |
3897 |
10607U, // SSNOP_MM |
| 3898 |
10607U, // SSNOP_MMR6 |
3898 |
10607U, // SSNOP_MMR6 |
| 3899 |
50349366U, // ST_B |
3899 |
50349366U, // ST_B |
| 3900 |
50351713U, // ST_D |
3900 |
50351713U, // ST_D |
| 3901 |
50353103U, // ST_H |
3901 |
50353103U, // ST_H |
| 3902 |
50357536U, // ST_W |
3902 |
50357536U, // ST_W |
| 3903 |
536889258U, // SUB |
3903 |
536889258U, // SUB |
| 3904 |
536892759U, // SUBQH_PH |
3904 |
536892759U, // SUBQH_PH |
| 3905 |
536892759U, // SUBQH_PH_MMR2 |
3905 |
536892759U, // SUBQH_PH_MMR2 |
| 3906 |
536892874U, // SUBQH_R_PH |
3906 |
536892874U, // SUBQH_R_PH |
| 3907 |
536892874U, // SUBQH_R_PH_MMR2 |
3907 |
536892874U, // SUBQH_R_PH_MMR2 |
| 3908 |
536896192U, // SUBQH_R_W |
3908 |
536896192U, // SUBQH_R_W |
| 3909 |
536896192U, // SUBQH_R_W_MMR2 |
3909 |
536896192U, // SUBQH_R_W_MMR2 |
| 3910 |
536895797U, // SUBQH_W |
3910 |
536895797U, // SUBQH_W |
| 3911 |
536895797U, // SUBQH_W_MMR2 |
3911 |
536895797U, // SUBQH_W_MMR2 |
| 3912 |
536892834U, // SUBQ_PH |
3912 |
536892834U, // SUBQ_PH |
| 3913 |
536892834U, // SUBQ_PH_MM |
3913 |
536892834U, // SUBQ_PH_MM |
| 3914 |
536892931U, // SUBQ_S_PH |
3914 |
536892931U, // SUBQ_S_PH |
| 3915 |
536892931U, // SUBQ_S_PH_MM |
3915 |
536892931U, // SUBQ_S_PH_MM |
| 3916 |
536896498U, // SUBQ_S_W |
3916 |
536896498U, // SUBQ_S_W |
| 3917 |
536896498U, // SUBQ_S_W_MM |
3917 |
536896498U, // SUBQ_S_W_MM |
| 3918 |
536888752U, // SUBSUS_U_B |
3918 |
536888752U, // SUBSUS_U_B |
| 3919 |
536891171U, // SUBSUS_U_D |
3919 |
536891171U, // SUBSUS_U_D |
| 3920 |
536892541U, // SUBSUS_U_H |
3920 |
536892541U, // SUBSUS_U_H |
| 3921 |
536896986U, // SUBSUS_U_W |
3921 |
536896986U, // SUBSUS_U_W |
| 3922 |
536888555U, // SUBSUU_S_B |
3922 |
536888555U, // SUBSUU_S_B |
| 3923 |
536890744U, // SUBSUU_S_D |
3923 |
536890744U, // SUBSUU_S_D |
| 3924 |
536892281U, // SUBSUU_S_H |
3924 |
536892281U, // SUBSUU_S_H |
| 3925 |
536896608U, // SUBSUU_S_W |
3925 |
536896608U, // SUBSUU_S_W |
| 3926 |
536888517U, // SUBS_S_B |
3926 |
536888517U, // SUBS_S_B |
| 3927 |
536890684U, // SUBS_S_D |
3927 |
536890684U, // SUBS_S_D |
| 3928 |
536892243U, // SUBS_S_H |
3928 |
536892243U, // SUBS_S_H |
| 3929 |
536896548U, // SUBS_S_W |
3929 |
536896548U, // SUBS_S_W |
| 3930 |
536888732U, // SUBS_U_B |
3930 |
536888732U, // SUBS_U_B |
| 3931 |
536891151U, // SUBS_U_D |
3931 |
536891151U, // SUBS_U_D |
| 3932 |
536892521U, // SUBS_U_H |
3932 |
536892521U, // SUBS_U_H |
| 3933 |
536896966U, // SUBS_U_W |
3933 |
536896966U, // SUBS_U_W |
| 3934 |
536887886U, // SUBU16_MM |
3934 |
536887886U, // SUBU16_MM |
| 3935 |
536887886U, // SUBU16_MMR6 |
3935 |
536887886U, // SUBU16_MMR6 |
| 3936 |
536888967U, // SUBUH_QB |
3936 |
536888967U, // SUBUH_QB |
| 3937 |
536888967U, // SUBUH_QB_MMR2 |
3937 |
536888967U, // SUBUH_QB_MMR2 |
| 3938 |
536889073U, // SUBUH_R_QB |
3938 |
536889073U, // SUBUH_R_QB |
| 3939 |
536889073U, // SUBUH_R_QB_MMR2 |
3939 |
536889073U, // SUBUH_R_QB_MMR2 |
| 3940 |
536895115U, // SUBU_MMR6 |
3940 |
536895115U, // SUBU_MMR6 |
| 3941 |
536893032U, // SUBU_PH |
3941 |
536893032U, // SUBU_PH |
| 3942 |
536893032U, // SUBU_PH_MMR2 |
3942 |
536893032U, // SUBU_PH_MMR2 |
| 3943 |
536889181U, // SUBU_QB |
3943 |
536889181U, // SUBU_QB |
| 3944 |
536889181U, // SUBU_QB_MM |
3944 |
536889181U, // SUBU_QB_MM |
| 3945 |
536892975U, // SUBU_S_PH |
3945 |
536892975U, // SUBU_S_PH |
| 3946 |
536892975U, // SUBU_S_PH_MMR2 |
3946 |
536892975U, // SUBU_S_PH_MMR2 |
| 3947 |
536889120U, // SUBU_S_QB |
3947 |
536889120U, // SUBU_S_QB |
| 3948 |
536889120U, // SUBU_S_QB_MM |
3948 |
536889120U, // SUBU_S_QB_MM |
| 3949 |
536888299U, // SUBVI_B |
3949 |
536888299U, // SUBVI_B |
| 3950 |
536890107U, // SUBVI_D |
3950 |
536890107U, // SUBVI_D |
| 3951 |
536891903U, // SUBVI_H |
3951 |
536891903U, // SUBVI_H |
| 3952 |
536895930U, // SUBVI_W |
3952 |
536895930U, // SUBVI_W |
| 3953 |
536888811U, // SUBV_B |
3953 |
536888811U, // SUBV_B |
| 3954 |
536891242U, // SUBV_D |
3954 |
536891242U, // SUBV_D |
| 3955 |
536892600U, // SUBV_H |
3955 |
536892600U, // SUBV_H |
| 3956 |
536897067U, // SUBV_W |
3956 |
536897067U, // SUBV_W |
| 3957 |
536889258U, // SUB_MM |
3957 |
536889258U, // SUB_MM |
| 3958 |
536889258U, // SUB_MMR6 |
3958 |
536889258U, // SUB_MMR6 |
| 3959 |
536895115U, // SUBu |
3959 |
536895115U, // SUBu |
| 3960 |
536895115U, // SUBu_MM |
3960 |
536895115U, // SUBu_MM |
| 3961 |
3254796459U, // SUXC1 |
3961 |
3254796459U, // SUXC1 |
| 3962 |
3254796459U, // SUXC164 |
3962 |
3254796459U, // SUXC164 |
| 3963 |
3254796459U, // SUXC1_MM |
3963 |
3254796459U, // SUXC1_MM |
| 3964 |
50357918U, // SW |
3964 |
50357918U, // SW |
| 3965 |
50348651U, // SW16_MM |
3965 |
50348651U, // SW16_MM |
| 3966 |
50348651U, // SW16_MMR6 |
3966 |
50348651U, // SW16_MMR6 |
| 3967 |
50357918U, // SW64 |
3967 |
50357918U, // SW64 |
| 3968 |
50348176U, // SWC1 |
3968 |
50348176U, // SWC1 |
| 3969 |
50348176U, // SWC1_MM |
3969 |
50348176U, // SWC1_MM |
| 3970 |
50348392U, // SWC2 |
3970 |
50348392U, // SWC2 |
| 3971 |
50348392U, // SWC2_MMR6 |
3971 |
50348392U, // SWC2_MMR6 |
| 3972 |
50348392U, // SWC2_R6 |
3972 |
50348392U, // SWC2_R6 |
| 3973 |
50348437U, // SWC3 |
3973 |
50348437U, // SWC3 |
| 3974 |
50357918U, // SWDSP |
3974 |
50357918U, // SWDSP |
| 3975 |
50357918U, // SWDSP_MM |
3975 |
50357918U, // SWDSP_MM |
| 3976 |
50352386U, // SWE |
3976 |
50352386U, // SWE |
| 3977 |
50352386U, // SWE_MM |
3977 |
50352386U, // SWE_MM |
| 3978 |
50354475U, // SWL |
3978 |
50354475U, // SWL |
| 3979 |
50354475U, // SWL64 |
3979 |
50354475U, // SWL64 |
| 3980 |
50352318U, // SWLE |
3980 |
50352318U, // SWLE |
| 3981 |
50352318U, // SWLE_MM |
3981 |
50352318U, // SWLE_MM |
| 3982 |
50354475U, // SWL_MM |
3982 |
50354475U, // SWL_MM |
| 3983 |
66066U, // SWM16_MM |
3983 |
66066U, // SWM16_MM |
| 3984 |
66066U, // SWM16_MMR6 |
3984 |
66066U, // SWM16_MMR6 |
| 3985 |
65806U, // SWM32_MM |
3985 |
65806U, // SWM32_MM |
| 3986 |
369121855U, // SWP_MM |
3986 |
369121855U, // SWP_MM |
| 3987 |
50354981U, // SWR |
3987 |
50354981U, // SWR |
| 3988 |
50354981U, // SWR64 |
3988 |
50354981U, // SWR64 |
| 3989 |
50352357U, // SWRE |
3989 |
50352357U, // SWRE |
| 3990 |
50352357U, // SWRE_MM |
3990 |
50352357U, // SWRE_MM |
| 3991 |
50354981U, // SWR_MM |
3991 |
50354981U, // SWR_MM |
| 3992 |
50354724U, // SWSP_MM |
3992 |
50354724U, // SWSP_MM |
| 3993 |
50357918U, // SWSP_MMR6 |
3993 |
50357918U, // SWSP_MMR6 |
| 3994 |
3254796473U, // SWXC1 |
3994 |
3254796473U, // SWXC1 |
| 3995 |
3254796473U, // SWXC1_MM |
3995 |
3254796473U, // SWXC1_MM |
| 3996 |
50357918U, // SW_MM |
3996 |
50357918U, // SW_MM |
| 3997 |
50357918U, // SW_MMR6 |
3997 |
50357918U, // SW_MMR6 |
| 3998 |
255866U, // SYNC |
3998 |
255866U, // SYNC |
| 3999 |
268102U, // SYNCI |
3999 |
268102U, // SYNCI |
| 4000 |
268102U, // SYNCI_MM |
4000 |
268102U, // SYNCI_MM |
| 4001 |
268102U, // SYNCI_MMR6 |
4001 |
268102U, // SYNCI_MMR6 |
| 4002 |
255866U, // SYNC_MM |
4002 |
255866U, // SYNC_MM |
| 4003 |
247832U, // SYNC_MMR6 |
4003 |
247832U, // SYNC_MMR6 |
| 4004 |
219316U, // SYSCALL |
4004 |
219316U, // SYSCALL |
| 4005 |
645300U, // SYSCALL_MM |
4005 |
645300U, // SYSCALL_MM |
| 4006 |
0U, // Save16 |
4006 |
0U, // Save16 |
| 4007 |
0U, // SaveX16 |
4007 |
0U, // SaveX16 |
| 4008 |
50349987U, // SbRxRyOffMemX16 |
4008 |
50349987U, // SbRxRyOffMemX16 |
| 4009 |
550669U, // SebRx16 |
4009 |
550669U, // SebRx16 |
| 4010 |
550675U, // SehRx16 |
4010 |
550675U, // SehRx16 |
| 4011 |
50353980U, // ShRxRyOffMemX16 |
4011 |
50353980U, // ShRxRyOffMemX16 |
| 4012 |
536893648U, // SllX16 |
4012 |
536893648U, // SllX16 |
| 4013 |
33578946U, // SllvRxRy16 |
4013 |
33578946U, // SllvRxRy16 |
| 4014 |
24146U, // SltRxRy16 |
4014 |
24146U, // SltRxRy16 |
| 4015 |
1610635183U, // SltiRxImm16 |
4015 |
1610635183U, // SltiRxImm16 |
| 4016 |
22447U, // SltiRxImmX16 |
4016 |
22447U, // SltiRxImmX16 |
| 4017 |
1610637038U, // SltiuRxImm16 |
4017 |
1610637038U, // SltiuRxImm16 |
| 4018 |
24302U, // SltiuRxImmX16 |
4018 |
24302U, // SltiuRxImmX16 |
| 4019 |
24388U, // SltuRxRy16 |
4019 |
24388U, // SltuRxRy16 |
| 4020 |
536888014U, // SraX16 |
4020 |
536888014U, // SraX16 |
| 4021 |
33578925U, // SravRxRy16 |
4021 |
33578925U, // SravRxRy16 |
| 4022 |
536893676U, // SrlX16 |
4022 |
536893676U, // SrlX16 |
| 4023 |
33578953U, // SrlvRxRy16 |
4023 |
33578953U, // SrlvRxRy16 |
| 4024 |
536895115U, // SubuRxRyRz16 |
4024 |
536895115U, // SubuRxRyRz16 |
| 4025 |
50357918U, // SwRxRyOffMemX16 |
4025 |
50357918U, // SwRxRyOffMemX16 |
| 4026 |
50357918U, // SwRxSpImmX16 |
4026 |
50357918U, // SwRxSpImmX16 |
| 4027 |
536894030U, // TEQ |
4027 |
536894030U, // TEQ |
| 4028 |
22429U, // TEQI |
4028 |
22429U, // TEQI |
| 4029 |
22429U, // TEQI_MM |
4029 |
22429U, // TEQI_MM |
| 4030 |
536894030U, // TEQ_MM |
4030 |
536894030U, // TEQ_MM |
| 4031 |
536891531U, // TGE |
4031 |
536891531U, // TGE |
| 4032 |
22362U, // TGEI |
4032 |
22362U, // TGEI |
| 4033 |
24295U, // TGEIU |
4033 |
24295U, // TGEIU |
| 4034 |
24295U, // TGEIU_MM |
4034 |
24295U, // TGEIU_MM |
| 4035 |
22362U, // TGEI_MM |
4035 |
22362U, // TGEI_MM |
| 4036 |
536895168U, // TGEU |
4036 |
536895168U, // TGEU |
| 4037 |
536895168U, // TGEU_MM |
4037 |
536895168U, // TGEU_MM |
| 4038 |
536891531U, // TGE_MM |
4038 |
536891531U, // TGE_MM |
| 4039 |
10655U, // TLBGINV |
4039 |
10655U, // TLBGINV |
| 4040 |
10556U, // TLBGINVF |
4040 |
10556U, // TLBGINVF |
| 4041 |
10556U, // TLBGINVF_MM |
4041 |
10556U, // TLBGINVF_MM |
| 4042 |
10655U, // TLBGINV_MM |
4042 |
10655U, // TLBGINV_MM |
| 4043 |
10601U, // TLBGP |
4043 |
10601U, // TLBGP |
| 4044 |
10601U, // TLBGP_MM |
4044 |
10601U, // TLBGP_MM |
| 4045 |
10618U, // TLBGR |
4045 |
10618U, // TLBGR |
| 4046 |
10618U, // TLBGR_MM |
4046 |
10618U, // TLBGR_MM |
| 4047 |
10571U, // TLBGWI |
4047 |
10571U, // TLBGWI |
| 4048 |
10571U, // TLBGWI_MM |
4048 |
10571U, // TLBGWI_MM |
| 4049 |
10630U, // TLBGWR |
4049 |
10630U, // TLBGWR |
| 4050 |
10630U, // TLBGWR_MM |
4050 |
10630U, // TLBGWR_MM |
| 4051 |
10648U, // TLBINV |
4051 |
10648U, // TLBINV |
| 4052 |
10548U, // TLBINVF |
4052 |
10548U, // TLBINVF |
| 4053 |
10548U, // TLBINVF_MMR6 |
4053 |
10548U, // TLBINVF_MMR6 |
| 4054 |
10648U, // TLBINV_MMR6 |
4054 |
10648U, // TLBINV_MMR6 |
| 4055 |
10596U, // TLBP |
4055 |
10596U, // TLBP |
| 4056 |
10596U, // TLBP_MM |
4056 |
10596U, // TLBP_MM |
| 4057 |
10613U, // TLBR |
4057 |
10613U, // TLBR |
| 4058 |
10613U, // TLBR_MM |
4058 |
10613U, // TLBR_MM |
| 4059 |
10565U, // TLBWI |
4059 |
10565U, // TLBWI |
| 4060 |
10565U, // TLBWI_MM |
4060 |
10565U, // TLBWI_MM |
| 4061 |
10624U, // TLBWR |
4061 |
10624U, // TLBWR |
| 4062 |
10624U, // TLBWR_MM |
4062 |
10624U, // TLBWR_MM |
| 4063 |
536895063U, // TLT |
4063 |
536895063U, // TLT |
| 4064 |
22453U, // TLTI |
4064 |
22453U, // TLTI |
| 4065 |
24309U, // TLTIU_MM |
4065 |
24309U, // TLTIU_MM |
| 4066 |
22453U, // TLTI_MM |
4066 |
22453U, // TLTI_MM |
| 4067 |
536895306U, // TLTU |
4067 |
536895306U, // TLTU |
| 4068 |
536895306U, // TLTU_MM |
4068 |
536895306U, // TLTU_MM |
| 4069 |
536895063U, // TLT_MM |
4069 |
536895063U, // TLT_MM |
| 4070 |
536891598U, // TNE |
4070 |
536891598U, // TNE |
| 4071 |
22374U, // TNEI |
4071 |
22374U, // TNEI |
| 4072 |
22374U, // TNEI_MM |
4072 |
22374U, // TNEI_MM |
| 4073 |
536891598U, // TNE_MM |
4073 |
536891598U, // TNE_MM |
| 4074 |
19213U, // TRUNC_L_D64 |
4074 |
19213U, // TRUNC_L_D64 |
| 4075 |
19213U, // TRUNC_L_D_MMR6 |
4075 |
19213U, // TRUNC_L_D_MMR6 |
| 4076 |
23545U, // TRUNC_L_S |
4076 |
23545U, // TRUNC_L_S |
| 4077 |
23545U, // TRUNC_L_S_MMR6 |
4077 |
23545U, // TRUNC_L_S_MMR6 |
| 4078 |
20388U, // TRUNC_W_D32 |
4078 |
20388U, // TRUNC_W_D32 |
| 4079 |
20388U, // TRUNC_W_D64 |
4079 |
20388U, // TRUNC_W_D64 |
| 4080 |
20388U, // TRUNC_W_D_MMR6 |
4080 |
20388U, // TRUNC_W_D_MMR6 |
| 4081 |
20388U, // TRUNC_W_MM |
4081 |
20388U, // TRUNC_W_MM |
| 4082 |
23887U, // TRUNC_W_S |
4082 |
23887U, // TRUNC_W_S |
| 4083 |
23887U, // TRUNC_W_S_MM |
4083 |
23887U, // TRUNC_W_S_MM |
| 4084 |
23887U, // TRUNC_W_S_MMR6 |
4084 |
23887U, // TRUNC_W_S_MMR6 |
| 4085 |
24309U, // TTLTIU |
4085 |
24309U, // TTLTIU |
| 4086 |
26394U, // UDIV |
4086 |
26394U, // UDIV |
| 4087 |
26394U, // UDIV_MM |
4087 |
26394U, // UDIV_MM |
| 4088 |
536895228U, // V3MULU |
4088 |
536895228U, // V3MULU |
| 4089 |
536887357U, // VMM0 |
4089 |
536887357U, // VMM0 |
| 4090 |
536895243U, // VMULU |
4090 |
536895243U, // VMULU |
| 4091 |
570442567U, // VSHF_B |
4091 |
570442567U, // VSHF_B |
| 4092 |
570444392U, // VSHF_D |
4092 |
570444392U, // VSHF_D |
| 4093 |
570446204U, // VSHF_H |
4093 |
570446204U, // VSHF_H |
| 4094 |
570450150U, // VSHF_W |
4094 |
570450150U, // VSHF_W |
| 4095 |
10643U, // WAIT |
4095 |
10643U, // WAIT |
| 4096 |
646727U, // WAIT_MM |
4096 |
646727U, // WAIT_MM |
| 4097 |
646727U, // WAIT_MMR6 |
4097 |
646727U, // WAIT_MMR6 |
| 4098 |
184572422U, // WRDSP |
4098 |
184572422U, // WRDSP |
| 4099 |
402676230U, // WRDSP_MM |
4099 |
402676230U, // WRDSP_MM |
| 4100 |
23294U, // WRPGPR_MMR6 |
4100 |
23294U, // WRPGPR_MMR6 |
| 4101 |
21758U, // WSBH |
4101 |
21758U, // WSBH |
| 4102 |
21758U, // WSBH_MM |
4102 |
21758U, // WSBH_MM |
| 4103 |
21758U, // WSBH_MMR6 |
4103 |
21758U, // WSBH_MMR6 |
| 4104 |
536894193U, // XOR |
4104 |
536894193U, // XOR |
| 4105 |
20021808U, // XOR16_MM |
4105 |
20021808U, // XOR16_MM |
| 4106 |
20021808U, // XOR16_MMR6 |
4106 |
20021808U, // XOR16_MMR6 |
| 4107 |
536894193U, // XOR64 |
4107 |
536894193U, // XOR64 |
| 4108 |
536888262U, // XORI_B |
4108 |
536888262U, // XORI_B |
| 4109 |
536893347U, // XORI_MMR6 |
4109 |
536893347U, // XORI_MMR6 |
| 4110 |
536894193U, // XOR_MM |
4110 |
536894193U, // XOR_MM |
| 4111 |
536894193U, // XOR_MMR6 |
4111 |
536894193U, // XOR_MMR6 |
| 4112 |
536895369U, // XOR_V |
4112 |
536895369U, // XOR_V |
| 4113 |
536893347U, // XORi |
4113 |
536893347U, // XORi |
| 4114 |
536893347U, // XORi64 |
4114 |
536893347U, // XORi64 |
| 4115 |
536893347U, // XORi_MM |
4115 |
536893347U, // XORi_MM |
| 4116 |
33577713U, // XorRxRxRy16 |
4116 |
33577713U, // XorRxRxRy16 |
| 4117 |
20535U, // YIELD |
4117 |
20535U, // YIELD |
| 4118 |
}; |
4118 |
}; |
| 4119 |
|
4119 |
|
| 4120 |
static const uint16_t OpInfo1[] = { |
4120 |
static const uint16_t OpInfo1[] = { |
| 4121 |
0U, // PHI |
4121 |
0U, // PHI |
| 4122 |
0U, // INLINEASM |
4122 |
0U, // INLINEASM |
| 4123 |
0U, // INLINEASM_BR |
4123 |
0U, // INLINEASM_BR |
| 4124 |
0U, // CFI_INSTRUCTION |
4124 |
0U, // CFI_INSTRUCTION |
| 4125 |
0U, // EH_LABEL |
4125 |
0U, // EH_LABEL |
| 4126 |
0U, // GC_LABEL |
4126 |
0U, // GC_LABEL |
| 4127 |
0U, // ANNOTATION_LABEL |
4127 |
0U, // ANNOTATION_LABEL |
| 4128 |
0U, // KILL |
4128 |
0U, // KILL |
| 4129 |
0U, // EXTRACT_SUBREG |
4129 |
0U, // EXTRACT_SUBREG |
| 4130 |
0U, // INSERT_SUBREG |
4130 |
0U, // INSERT_SUBREG |
| 4131 |
0U, // IMPLICIT_DEF |
4131 |
0U, // IMPLICIT_DEF |
| 4132 |
0U, // SUBREG_TO_REG |
4132 |
0U, // SUBREG_TO_REG |
| 4133 |
0U, // COPY_TO_REGCLASS |
4133 |
0U, // COPY_TO_REGCLASS |
| 4134 |
0U, // DBG_VALUE |
4134 |
0U, // DBG_VALUE |
| 4135 |
0U, // DBG_VALUE_LIST |
4135 |
0U, // DBG_VALUE_LIST |
| 4136 |
0U, // DBG_INSTR_REF |
4136 |
0U, // DBG_INSTR_REF |
| 4137 |
0U, // DBG_PHI |
4137 |
0U, // DBG_PHI |
| 4138 |
0U, // DBG_LABEL |
4138 |
0U, // DBG_LABEL |
| 4139 |
0U, // REG_SEQUENCE |
4139 |
0U, // REG_SEQUENCE |
| 4140 |
0U, // COPY |
4140 |
0U, // COPY |
| 4141 |
0U, // BUNDLE |
4141 |
0U, // BUNDLE |
| 4142 |
0U, // LIFETIME_START |
4142 |
0U, // LIFETIME_START |
| 4143 |
0U, // LIFETIME_END |
4143 |
0U, // LIFETIME_END |
| 4144 |
0U, // PSEUDO_PROBE |
4144 |
0U, // PSEUDO_PROBE |
| 4145 |
0U, // ARITH_FENCE |
4145 |
0U, // ARITH_FENCE |
| 4146 |
0U, // STACKMAP |
4146 |
0U, // STACKMAP |
| 4147 |
0U, // FENTRY_CALL |
4147 |
0U, // FENTRY_CALL |
| 4148 |
0U, // PATCHPOINT |
4148 |
0U, // PATCHPOINT |
| 4149 |
0U, // LOAD_STACK_GUARD |
4149 |
0U, // LOAD_STACK_GUARD |
| 4150 |
0U, // PREALLOCATED_SETUP |
4150 |
0U, // PREALLOCATED_SETUP |
| 4151 |
0U, // PREALLOCATED_ARG |
4151 |
0U, // PREALLOCATED_ARG |
| 4152 |
0U, // STATEPOINT |
4152 |
0U, // STATEPOINT |
| 4153 |
0U, // LOCAL_ESCAPE |
4153 |
0U, // LOCAL_ESCAPE |
| 4154 |
0U, // FAULTING_OP |
4154 |
0U, // FAULTING_OP |
| 4155 |
0U, // PATCHABLE_OP |
4155 |
0U, // PATCHABLE_OP |
| 4156 |
0U, // PATCHABLE_FUNCTION_ENTER |
4156 |
0U, // PATCHABLE_FUNCTION_ENTER |
| 4157 |
0U, // PATCHABLE_RET |
4157 |
0U, // PATCHABLE_RET |
| 4158 |
0U, // PATCHABLE_FUNCTION_EXIT |
4158 |
0U, // PATCHABLE_FUNCTION_EXIT |
| 4159 |
0U, // PATCHABLE_TAIL_CALL |
4159 |
0U, // PATCHABLE_TAIL_CALL |
| 4160 |
0U, // PATCHABLE_EVENT_CALL |
4160 |
0U, // PATCHABLE_EVENT_CALL |
| 4161 |
0U, // PATCHABLE_TYPED_EVENT_CALL |
4161 |
0U, // PATCHABLE_TYPED_EVENT_CALL |
| 4162 |
0U, // ICALL_BRANCH_FUNNEL |
4162 |
0U, // ICALL_BRANCH_FUNNEL |
| 4163 |
0U, // MEMBARRIER |
4163 |
0U, // MEMBARRIER |
| 4164 |
0U, // G_ASSERT_SEXT |
4164 |
0U, // G_ASSERT_SEXT |
| 4165 |
0U, // G_ASSERT_ZEXT |
4165 |
0U, // G_ASSERT_ZEXT |
| 4166 |
0U, // G_ASSERT_ALIGN |
4166 |
0U, // G_ASSERT_ALIGN |
| 4167 |
0U, // G_ADD |
4167 |
0U, // G_ADD |
| 4168 |
0U, // G_SUB |
4168 |
0U, // G_SUB |
| 4169 |
0U, // G_MUL |
4169 |
0U, // G_MUL |
| 4170 |
0U, // G_SDIV |
4170 |
0U, // G_SDIV |
| 4171 |
0U, // G_UDIV |
4171 |
0U, // G_UDIV |
| 4172 |
0U, // G_SREM |
4172 |
0U, // G_SREM |
| 4173 |
0U, // G_UREM |
4173 |
0U, // G_UREM |
| 4174 |
0U, // G_SDIVREM |
4174 |
0U, // G_SDIVREM |
| 4175 |
0U, // G_UDIVREM |
4175 |
0U, // G_UDIVREM |
| 4176 |
0U, // G_AND |
4176 |
0U, // G_AND |
| 4177 |
0U, // G_OR |
4177 |
0U, // G_OR |
| 4178 |
0U, // G_XOR |
4178 |
0U, // G_XOR |
| 4179 |
0U, // G_IMPLICIT_DEF |
4179 |
0U, // G_IMPLICIT_DEF |
| 4180 |
0U, // G_PHI |
4180 |
0U, // G_PHI |
| 4181 |
0U, // G_FRAME_INDEX |
4181 |
0U, // G_FRAME_INDEX |
| 4182 |
0U, // G_GLOBAL_VALUE |
4182 |
0U, // G_GLOBAL_VALUE |
| 4183 |
0U, // G_CONSTANT_POOL |
4183 |
0U, // G_CONSTANT_POOL |
| 4184 |
0U, // G_EXTRACT |
4184 |
0U, // G_EXTRACT |
| 4185 |
0U, // G_UNMERGE_VALUES |
4185 |
0U, // G_UNMERGE_VALUES |
| 4186 |
0U, // G_INSERT |
4186 |
0U, // G_INSERT |
| 4187 |
0U, // G_MERGE_VALUES |
4187 |
0U, // G_MERGE_VALUES |
| 4188 |
0U, // G_BUILD_VECTOR |
4188 |
0U, // G_BUILD_VECTOR |
| 4189 |
0U, // G_BUILD_VECTOR_TRUNC |
4189 |
0U, // G_BUILD_VECTOR_TRUNC |
| 4190 |
0U, // G_CONCAT_VECTORS |
4190 |
0U, // G_CONCAT_VECTORS |
| 4191 |
0U, // G_PTRTOINT |
4191 |
0U, // G_PTRTOINT |
| 4192 |
0U, // G_INTTOPTR |
4192 |
0U, // G_INTTOPTR |
| 4193 |
0U, // G_BITCAST |
4193 |
0U, // G_BITCAST |
| 4194 |
0U, // G_FREEZE |
4194 |
0U, // G_FREEZE |
| 4195 |
0U, // G_CONSTANT_FOLD_BARRIER |
4195 |
0U, // G_CONSTANT_FOLD_BARRIER |
| 4196 |
0U, // G_INTRINSIC_FPTRUNC_ROUND |
4196 |
0U, // G_INTRINSIC_FPTRUNC_ROUND |
| 4197 |
0U, // G_INTRINSIC_TRUNC |
4197 |
0U, // G_INTRINSIC_TRUNC |
| 4198 |
0U, // G_INTRINSIC_ROUND |
4198 |
0U, // G_INTRINSIC_ROUND |
| 4199 |
0U, // G_INTRINSIC_LRINT |
4199 |
0U, // G_INTRINSIC_LRINT |
| 4200 |
0U, // G_INTRINSIC_ROUNDEVEN |
4200 |
0U, // G_INTRINSIC_ROUNDEVEN |
| 4201 |
0U, // G_READCYCLECOUNTER |
4201 |
0U, // G_READCYCLECOUNTER |
| 4202 |
0U, // G_LOAD |
4202 |
0U, // G_LOAD |
| 4203 |
0U, // G_SEXTLOAD |
4203 |
0U, // G_SEXTLOAD |
| 4204 |
0U, // G_ZEXTLOAD |
4204 |
0U, // G_ZEXTLOAD |
| 4205 |
0U, // G_INDEXED_LOAD |
4205 |
0U, // G_INDEXED_LOAD |
| 4206 |
0U, // G_INDEXED_SEXTLOAD |
4206 |
0U, // G_INDEXED_SEXTLOAD |
| 4207 |
0U, // G_INDEXED_ZEXTLOAD |
4207 |
0U, // G_INDEXED_ZEXTLOAD |
| 4208 |
0U, // G_STORE |
4208 |
0U, // G_STORE |
| 4209 |
0U, // G_INDEXED_STORE |
4209 |
0U, // G_INDEXED_STORE |
| 4210 |
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
4210 |
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 4211 |
0U, // G_ATOMIC_CMPXCHG |
4211 |
0U, // G_ATOMIC_CMPXCHG |
| 4212 |
0U, // G_ATOMICRMW_XCHG |
4212 |
0U, // G_ATOMICRMW_XCHG |
| 4213 |
0U, // G_ATOMICRMW_ADD |
4213 |
0U, // G_ATOMICRMW_ADD |
| 4214 |
0U, // G_ATOMICRMW_SUB |
4214 |
0U, // G_ATOMICRMW_SUB |
| 4215 |
0U, // G_ATOMICRMW_AND |
4215 |
0U, // G_ATOMICRMW_AND |
| 4216 |
0U, // G_ATOMICRMW_NAND |
4216 |
0U, // G_ATOMICRMW_NAND |
| 4217 |
0U, // G_ATOMICRMW_OR |
4217 |
0U, // G_ATOMICRMW_OR |
| 4218 |
0U, // G_ATOMICRMW_XOR |
4218 |
0U, // G_ATOMICRMW_XOR |
| 4219 |
0U, // G_ATOMICRMW_MAX |
4219 |
0U, // G_ATOMICRMW_MAX |
| 4220 |
0U, // G_ATOMICRMW_MIN |
4220 |
0U, // G_ATOMICRMW_MIN |
| 4221 |
0U, // G_ATOMICRMW_UMAX |
4221 |
0U, // G_ATOMICRMW_UMAX |
| 4222 |
0U, // G_ATOMICRMW_UMIN |
4222 |
0U, // G_ATOMICRMW_UMIN |
| 4223 |
0U, // G_ATOMICRMW_FADD |
4223 |
0U, // G_ATOMICRMW_FADD |
| 4224 |
0U, // G_ATOMICRMW_FSUB |
4224 |
0U, // G_ATOMICRMW_FSUB |
| 4225 |
0U, // G_ATOMICRMW_FMAX |
4225 |
0U, // G_ATOMICRMW_FMAX |
| 4226 |
0U, // G_ATOMICRMW_FMIN |
4226 |
0U, // G_ATOMICRMW_FMIN |
| 4227 |
0U, // G_ATOMICRMW_UINC_WRAP |
4227 |
0U, // G_ATOMICRMW_UINC_WRAP |
| 4228 |
0U, // G_ATOMICRMW_UDEC_WRAP |
4228 |
0U, // G_ATOMICRMW_UDEC_WRAP |
| 4229 |
0U, // G_FENCE |
4229 |
0U, // G_FENCE |
| 4230 |
0U, // G_BRCOND |
4230 |
0U, // G_BRCOND |
| 4231 |
0U, // G_BRINDIRECT |
4231 |
0U, // G_BRINDIRECT |
| 4232 |
0U, // G_INVOKE_REGION_START |
4232 |
0U, // G_INVOKE_REGION_START |
| 4233 |
0U, // G_INTRINSIC |
4233 |
0U, // G_INTRINSIC |
| 4234 |
0U, // G_INTRINSIC_W_SIDE_EFFECTS |
4234 |
0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 4235 |
0U, // G_ANYEXT |
4235 |
0U, // G_ANYEXT |
| 4236 |
0U, // G_TRUNC |
4236 |
0U, // G_TRUNC |
| 4237 |
0U, // G_CONSTANT |
4237 |
0U, // G_CONSTANT |
| 4238 |
0U, // G_FCONSTANT |
4238 |
0U, // G_FCONSTANT |
| 4239 |
0U, // G_VASTART |
4239 |
0U, // G_VASTART |
| 4240 |
0U, // G_VAARG |
4240 |
0U, // G_VAARG |
| 4241 |
0U, // G_SEXT |
4241 |
0U, // G_SEXT |
| 4242 |
0U, // G_SEXT_INREG |
4242 |
0U, // G_SEXT_INREG |
| 4243 |
0U, // G_ZEXT |
4243 |
0U, // G_ZEXT |
| 4244 |
0U, // G_SHL |
4244 |
0U, // G_SHL |
| 4245 |
0U, // G_LSHR |
4245 |
0U, // G_LSHR |
| 4246 |
0U, // G_ASHR |
4246 |
0U, // G_ASHR |
| 4247 |
0U, // G_FSHL |
4247 |
0U, // G_FSHL |
| 4248 |
0U, // G_FSHR |
4248 |
0U, // G_FSHR |
| 4249 |
0U, // G_ROTR |
4249 |
0U, // G_ROTR |
| 4250 |
0U, // G_ROTL |
4250 |
0U, // G_ROTL |
| 4251 |
0U, // G_ICMP |
4251 |
0U, // G_ICMP |
| 4252 |
0U, // G_FCMP |
4252 |
0U, // G_FCMP |
| 4253 |
0U, // G_SELECT |
4253 |
0U, // G_SELECT |
| 4254 |
0U, // G_UADDO |
4254 |
0U, // G_UADDO |
| 4255 |
0U, // G_UADDE |
4255 |
0U, // G_UADDE |
| 4256 |
0U, // G_USUBO |
4256 |
0U, // G_USUBO |
| 4257 |
0U, // G_USUBE |
4257 |
0U, // G_USUBE |
| 4258 |
0U, // G_SADDO |
4258 |
0U, // G_SADDO |
| 4259 |
0U, // G_SADDE |
4259 |
0U, // G_SADDE |
| 4260 |
0U, // G_SSUBO |
4260 |
0U, // G_SSUBO |
| 4261 |
0U, // G_SSUBE |
4261 |
0U, // G_SSUBE |
| 4262 |
0U, // G_UMULO |
4262 |
0U, // G_UMULO |
| 4263 |
0U, // G_SMULO |
4263 |
0U, // G_SMULO |
| 4264 |
0U, // G_UMULH |
4264 |
0U, // G_UMULH |
| 4265 |
0U, // G_SMULH |
4265 |
0U, // G_SMULH |
| 4266 |
0U, // G_UADDSAT |
4266 |
0U, // G_UADDSAT |
| 4267 |
0U, // G_SADDSAT |
4267 |
0U, // G_SADDSAT |
| 4268 |
0U, // G_USUBSAT |
4268 |
0U, // G_USUBSAT |
| 4269 |
0U, // G_SSUBSAT |
4269 |
0U, // G_SSUBSAT |
| 4270 |
0U, // G_USHLSAT |
4270 |
0U, // G_USHLSAT |
| 4271 |
0U, // G_SSHLSAT |
4271 |
0U, // G_SSHLSAT |
| 4272 |
0U, // G_SMULFIX |
4272 |
0U, // G_SMULFIX |
| 4273 |
0U, // G_UMULFIX |
4273 |
0U, // G_UMULFIX |
| 4274 |
0U, // G_SMULFIXSAT |
4274 |
0U, // G_SMULFIXSAT |
| 4275 |
0U, // G_UMULFIXSAT |
4275 |
0U, // G_UMULFIXSAT |
| 4276 |
0U, // G_SDIVFIX |
4276 |
0U, // G_SDIVFIX |
| 4277 |
0U, // G_UDIVFIX |
4277 |
0U, // G_UDIVFIX |
| 4278 |
0U, // G_SDIVFIXSAT |
4278 |
0U, // G_SDIVFIXSAT |
| 4279 |
0U, // G_UDIVFIXSAT |
4279 |
0U, // G_UDIVFIXSAT |
| 4280 |
0U, // G_FADD |
4280 |
0U, // G_FADD |
| 4281 |
0U, // G_FSUB |
4281 |
0U, // G_FSUB |
| 4282 |
0U, // G_FMUL |
4282 |
0U, // G_FMUL |
| 4283 |
0U, // G_FMA |
4283 |
0U, // G_FMA |
| 4284 |
0U, // G_FMAD |
4284 |
0U, // G_FMAD |
| 4285 |
0U, // G_FDIV |
4285 |
0U, // G_FDIV |
| 4286 |
0U, // G_FREM |
4286 |
0U, // G_FREM |
| 4287 |
0U, // G_FPOW |
4287 |
0U, // G_FPOW |
| 4288 |
0U, // G_FPOWI |
4288 |
0U, // G_FPOWI |
| 4289 |
0U, // G_FEXP |
4289 |
0U, // G_FEXP |
| 4290 |
0U, // G_FEXP2 |
4290 |
0U, // G_FEXP2 |
| 4291 |
0U, // G_FLOG |
4291 |
0U, // G_FLOG |
| 4292 |
0U, // G_FLOG2 |
4292 |
0U, // G_FLOG2 |
| 4293 |
0U, // G_FLOG10 |
4293 |
0U, // G_FLOG10 |
| 4294 |
0U, // G_FLDEXP |
4294 |
0U, // G_FLDEXP |
| 4295 |
0U, // G_FFREXP |
4295 |
0U, // G_FFREXP |
| 4296 |
0U, // G_FNEG |
4296 |
0U, // G_FNEG |
| 4297 |
0U, // G_FPEXT |
4297 |
0U, // G_FPEXT |
| 4298 |
0U, // G_FPTRUNC |
4298 |
0U, // G_FPTRUNC |
| 4299 |
0U, // G_FPTOSI |
4299 |
0U, // G_FPTOSI |
| 4300 |
0U, // G_FPTOUI |
4300 |
0U, // G_FPTOUI |
| 4301 |
0U, // G_SITOFP |
4301 |
0U, // G_SITOFP |
| 4302 |
0U, // G_UITOFP |
4302 |
0U, // G_UITOFP |
| 4303 |
0U, // G_FABS |
4303 |
0U, // G_FABS |
| 4304 |
0U, // G_FCOPYSIGN |
4304 |
0U, // G_FCOPYSIGN |
| 4305 |
0U, // G_IS_FPCLASS |
4305 |
0U, // G_IS_FPCLASS |
| 4306 |
0U, // G_FCANONICALIZE |
4306 |
0U, // G_FCANONICALIZE |
| 4307 |
0U, // G_FMINNUM |
4307 |
0U, // G_FMINNUM |
| 4308 |
0U, // G_FMAXNUM |
4308 |
0U, // G_FMAXNUM |
| 4309 |
0U, // G_FMINNUM_IEEE |
4309 |
0U, // G_FMINNUM_IEEE |
| 4310 |
0U, // G_FMAXNUM_IEEE |
4310 |
0U, // G_FMAXNUM_IEEE |
| 4311 |
0U, // G_FMINIMUM |
4311 |
0U, // G_FMINIMUM |
| 4312 |
0U, // G_FMAXIMUM |
4312 |
0U, // G_FMAXIMUM |
| 4313 |
0U, // G_PTR_ADD |
4313 |
0U, // G_PTR_ADD |
| 4314 |
0U, // G_PTRMASK |
4314 |
0U, // G_PTRMASK |
| 4315 |
0U, // G_SMIN |
4315 |
0U, // G_SMIN |
| 4316 |
0U, // G_SMAX |
4316 |
0U, // G_SMAX |
| 4317 |
0U, // G_UMIN |
4317 |
0U, // G_UMIN |
| 4318 |
0U, // G_UMAX |
4318 |
0U, // G_UMAX |
| 4319 |
0U, // G_ABS |
4319 |
0U, // G_ABS |
| 4320 |
0U, // G_LROUND |
4320 |
0U, // G_LROUND |
| 4321 |
0U, // G_LLROUND |
4321 |
0U, // G_LLROUND |
| 4322 |
0U, // G_BR |
4322 |
0U, // G_BR |
| 4323 |
0U, // G_BRJT |
4323 |
0U, // G_BRJT |
| 4324 |
0U, // G_INSERT_VECTOR_ELT |
4324 |
0U, // G_INSERT_VECTOR_ELT |
| 4325 |
0U, // G_EXTRACT_VECTOR_ELT |
4325 |
0U, // G_EXTRACT_VECTOR_ELT |
| 4326 |
0U, // G_SHUFFLE_VECTOR |
4326 |
0U, // G_SHUFFLE_VECTOR |
| 4327 |
0U, // G_CTTZ |
4327 |
0U, // G_CTTZ |
| 4328 |
0U, // G_CTTZ_ZERO_UNDEF |
4328 |
0U, // G_CTTZ_ZERO_UNDEF |
| 4329 |
0U, // G_CTLZ |
4329 |
0U, // G_CTLZ |
| 4330 |
0U, // G_CTLZ_ZERO_UNDEF |
4330 |
0U, // G_CTLZ_ZERO_UNDEF |
| 4331 |
0U, // G_CTPOP |
4331 |
0U, // G_CTPOP |
| 4332 |
0U, // G_BSWAP |
4332 |
0U, // G_BSWAP |
| 4333 |
0U, // G_BITREVERSE |
4333 |
0U, // G_BITREVERSE |
| 4334 |
0U, // G_FCEIL |
4334 |
0U, // G_FCEIL |
| 4335 |
0U, // G_FCOS |
4335 |
0U, // G_FCOS |
| 4336 |
0U, // G_FSIN |
4336 |
0U, // G_FSIN |
| 4337 |
0U, // G_FSQRT |
4337 |
0U, // G_FSQRT |
| 4338 |
0U, // G_FFLOOR |
4338 |
0U, // G_FFLOOR |
| 4339 |
0U, // G_FRINT |
4339 |
0U, // G_FRINT |
| 4340 |
0U, // G_FNEARBYINT |
4340 |
0U, // G_FNEARBYINT |
| 4341 |
0U, // G_ADDRSPACE_CAST |
4341 |
0U, // G_ADDRSPACE_CAST |
| 4342 |
0U, // G_BLOCK_ADDR |
4342 |
0U, // G_BLOCK_ADDR |
| 4343 |
0U, // G_JUMP_TABLE |
4343 |
0U, // G_JUMP_TABLE |
| 4344 |
0U, // G_DYN_STACKALLOC |
4344 |
0U, // G_DYN_STACKALLOC |
| 4345 |
0U, // G_STRICT_FADD |
4345 |
0U, // G_STRICT_FADD |
| 4346 |
0U, // G_STRICT_FSUB |
4346 |
0U, // G_STRICT_FSUB |
| 4347 |
0U, // G_STRICT_FMUL |
4347 |
0U, // G_STRICT_FMUL |
| 4348 |
0U, // G_STRICT_FDIV |
4348 |
0U, // G_STRICT_FDIV |
| 4349 |
0U, // G_STRICT_FREM |
4349 |
0U, // G_STRICT_FREM |
| 4350 |
0U, // G_STRICT_FMA |
4350 |
0U, // G_STRICT_FMA |
| 4351 |
0U, // G_STRICT_FSQRT |
4351 |
0U, // G_STRICT_FSQRT |
| 4352 |
0U, // G_STRICT_FLDEXP |
4352 |
0U, // G_STRICT_FLDEXP |
| 4353 |
0U, // G_READ_REGISTER |
4353 |
0U, // G_READ_REGISTER |
| 4354 |
0U, // G_WRITE_REGISTER |
4354 |
0U, // G_WRITE_REGISTER |
| 4355 |
0U, // G_MEMCPY |
4355 |
0U, // G_MEMCPY |
| 4356 |
0U, // G_MEMCPY_INLINE |
4356 |
0U, // G_MEMCPY_INLINE |
| 4357 |
0U, // G_MEMMOVE |
4357 |
0U, // G_MEMMOVE |
| 4358 |
0U, // G_MEMSET |
4358 |
0U, // G_MEMSET |
| 4359 |
0U, // G_BZERO |
4359 |
0U, // G_BZERO |
| 4360 |
0U, // G_VECREDUCE_SEQ_FADD |
4360 |
0U, // G_VECREDUCE_SEQ_FADD |
| 4361 |
0U, // G_VECREDUCE_SEQ_FMUL |
4361 |
0U, // G_VECREDUCE_SEQ_FMUL |
| 4362 |
0U, // G_VECREDUCE_FADD |
4362 |
0U, // G_VECREDUCE_FADD |
| 4363 |
0U, // G_VECREDUCE_FMUL |
4363 |
0U, // G_VECREDUCE_FMUL |
| 4364 |
0U, // G_VECREDUCE_FMAX |
4364 |
0U, // G_VECREDUCE_FMAX |
| 4365 |
0U, // G_VECREDUCE_FMIN |
4365 |
0U, // G_VECREDUCE_FMIN |
| 4366 |
0U, // G_VECREDUCE_ADD |
4366 |
0U, // G_VECREDUCE_ADD |
| 4367 |
0U, // G_VECREDUCE_MUL |
4367 |
0U, // G_VECREDUCE_MUL |
| 4368 |
0U, // G_VECREDUCE_AND |
4368 |
0U, // G_VECREDUCE_AND |
| 4369 |
0U, // G_VECREDUCE_OR |
4369 |
0U, // G_VECREDUCE_OR |
| 4370 |
0U, // G_VECREDUCE_XOR |
4370 |
0U, // G_VECREDUCE_XOR |
| 4371 |
0U, // G_VECREDUCE_SMAX |
4371 |
0U, // G_VECREDUCE_SMAX |
| 4372 |
0U, // G_VECREDUCE_SMIN |
4372 |
0U, // G_VECREDUCE_SMIN |
| 4373 |
0U, // G_VECREDUCE_UMAX |
4373 |
0U, // G_VECREDUCE_UMAX |
| 4374 |
0U, // G_VECREDUCE_UMIN |
4374 |
0U, // G_VECREDUCE_UMIN |
| 4375 |
0U, // G_SBFX |
4375 |
0U, // G_SBFX |
| 4376 |
0U, // G_UBFX |
4376 |
0U, // G_UBFX |
| 4377 |
0U, // ABSMacro |
4377 |
0U, // ABSMacro |
| 4378 |
0U, // ADJCALLSTACKDOWN |
4378 |
0U, // ADJCALLSTACKDOWN |
| 4379 |
0U, // ADJCALLSTACKUP |
4379 |
0U, // ADJCALLSTACKUP |
| 4380 |
0U, // AND_V_D_PSEUDO |
4380 |
0U, // AND_V_D_PSEUDO |
| 4381 |
0U, // AND_V_H_PSEUDO |
4381 |
0U, // AND_V_H_PSEUDO |
| 4382 |
0U, // AND_V_W_PSEUDO |
4382 |
0U, // AND_V_W_PSEUDO |
| 4383 |
0U, // ATOMIC_CMP_SWAP_I16 |
4383 |
0U, // ATOMIC_CMP_SWAP_I16 |
| 4384 |
0U, // ATOMIC_CMP_SWAP_I16_POSTRA |
4384 |
0U, // ATOMIC_CMP_SWAP_I16_POSTRA |
| 4385 |
0U, // ATOMIC_CMP_SWAP_I32 |
4385 |
0U, // ATOMIC_CMP_SWAP_I32 |
| 4386 |
0U, // ATOMIC_CMP_SWAP_I32_POSTRA |
4386 |
0U, // ATOMIC_CMP_SWAP_I32_POSTRA |
| 4387 |
0U, // ATOMIC_CMP_SWAP_I64 |
4387 |
0U, // ATOMIC_CMP_SWAP_I64 |
| 4388 |
0U, // ATOMIC_CMP_SWAP_I64_POSTRA |
4388 |
0U, // ATOMIC_CMP_SWAP_I64_POSTRA |
| 4389 |
0U, // ATOMIC_CMP_SWAP_I8 |
4389 |
0U, // ATOMIC_CMP_SWAP_I8 |
| 4390 |
0U, // ATOMIC_CMP_SWAP_I8_POSTRA |
4390 |
0U, // ATOMIC_CMP_SWAP_I8_POSTRA |
| 4391 |
0U, // ATOMIC_LOAD_ADD_I16 |
4391 |
0U, // ATOMIC_LOAD_ADD_I16 |
| 4392 |
0U, // ATOMIC_LOAD_ADD_I16_POSTRA |
4392 |
0U, // ATOMIC_LOAD_ADD_I16_POSTRA |
| 4393 |
0U, // ATOMIC_LOAD_ADD_I32 |
4393 |
0U, // ATOMIC_LOAD_ADD_I32 |
| 4394 |
0U, // ATOMIC_LOAD_ADD_I32_POSTRA |
4394 |
0U, // ATOMIC_LOAD_ADD_I32_POSTRA |
| 4395 |
0U, // ATOMIC_LOAD_ADD_I64 |
4395 |
0U, // ATOMIC_LOAD_ADD_I64 |
| 4396 |
0U, // ATOMIC_LOAD_ADD_I64_POSTRA |
4396 |
0U, // ATOMIC_LOAD_ADD_I64_POSTRA |
| 4397 |
0U, // ATOMIC_LOAD_ADD_I8 |
4397 |
0U, // ATOMIC_LOAD_ADD_I8 |
| 4398 |
0U, // ATOMIC_LOAD_ADD_I8_POSTRA |
4398 |
0U, // ATOMIC_LOAD_ADD_I8_POSTRA |
| 4399 |
0U, // ATOMIC_LOAD_AND_I16 |
4399 |
0U, // ATOMIC_LOAD_AND_I16 |
| 4400 |
0U, // ATOMIC_LOAD_AND_I16_POSTRA |
4400 |
0U, // ATOMIC_LOAD_AND_I16_POSTRA |
| 4401 |
0U, // ATOMIC_LOAD_AND_I32 |
4401 |
0U, // ATOMIC_LOAD_AND_I32 |
| 4402 |
0U, // ATOMIC_LOAD_AND_I32_POSTRA |
4402 |
0U, // ATOMIC_LOAD_AND_I32_POSTRA |
| 4403 |
0U, // ATOMIC_LOAD_AND_I64 |
4403 |
0U, // ATOMIC_LOAD_AND_I64 |
| 4404 |
0U, // ATOMIC_LOAD_AND_I64_POSTRA |
4404 |
0U, // ATOMIC_LOAD_AND_I64_POSTRA |
| 4405 |
0U, // ATOMIC_LOAD_AND_I8 |
4405 |
0U, // ATOMIC_LOAD_AND_I8 |
| 4406 |
0U, // ATOMIC_LOAD_AND_I8_POSTRA |
4406 |
0U, // ATOMIC_LOAD_AND_I8_POSTRA |
| 4407 |
0U, // ATOMIC_LOAD_MAX_I16 |
4407 |
0U, // ATOMIC_LOAD_MAX_I16 |
| 4408 |
0U, // ATOMIC_LOAD_MAX_I16_POSTRA |
4408 |
0U, // ATOMIC_LOAD_MAX_I16_POSTRA |
| 4409 |
0U, // ATOMIC_LOAD_MAX_I32 |
4409 |
0U, // ATOMIC_LOAD_MAX_I32 |
| 4410 |
0U, // ATOMIC_LOAD_MAX_I32_POSTRA |
4410 |
0U, // ATOMIC_LOAD_MAX_I32_POSTRA |
| 4411 |
0U, // ATOMIC_LOAD_MAX_I64 |
4411 |
0U, // ATOMIC_LOAD_MAX_I64 |
| 4412 |
0U, // ATOMIC_LOAD_MAX_I64_POSTRA |
4412 |
0U, // ATOMIC_LOAD_MAX_I64_POSTRA |
| 4413 |
0U, // ATOMIC_LOAD_MAX_I8 |
4413 |
0U, // ATOMIC_LOAD_MAX_I8 |
| 4414 |
0U, // ATOMIC_LOAD_MAX_I8_POSTRA |
4414 |
0U, // ATOMIC_LOAD_MAX_I8_POSTRA |
| 4415 |
0U, // ATOMIC_LOAD_MIN_I16 |
4415 |
0U, // ATOMIC_LOAD_MIN_I16 |
| 4416 |
0U, // ATOMIC_LOAD_MIN_I16_POSTRA |
4416 |
0U, // ATOMIC_LOAD_MIN_I16_POSTRA |
| 4417 |
0U, // ATOMIC_LOAD_MIN_I32 |
4417 |
0U, // ATOMIC_LOAD_MIN_I32 |
| 4418 |
0U, // ATOMIC_LOAD_MIN_I32_POSTRA |
4418 |
0U, // ATOMIC_LOAD_MIN_I32_POSTRA |
| 4419 |
0U, // ATOMIC_LOAD_MIN_I64 |
4419 |
0U, // ATOMIC_LOAD_MIN_I64 |
| 4420 |
0U, // ATOMIC_LOAD_MIN_I64_POSTRA |
4420 |
0U, // ATOMIC_LOAD_MIN_I64_POSTRA |
| 4421 |
0U, // ATOMIC_LOAD_MIN_I8 |
4421 |
0U, // ATOMIC_LOAD_MIN_I8 |
| 4422 |
0U, // ATOMIC_LOAD_MIN_I8_POSTRA |
4422 |
0U, // ATOMIC_LOAD_MIN_I8_POSTRA |
| 4423 |
0U, // ATOMIC_LOAD_NAND_I16 |
4423 |
0U, // ATOMIC_LOAD_NAND_I16 |
| 4424 |
0U, // ATOMIC_LOAD_NAND_I16_POSTRA |
4424 |
0U, // ATOMIC_LOAD_NAND_I16_POSTRA |
| 4425 |
0U, // ATOMIC_LOAD_NAND_I32 |
4425 |
0U, // ATOMIC_LOAD_NAND_I32 |
| 4426 |
0U, // ATOMIC_LOAD_NAND_I32_POSTRA |
4426 |
0U, // ATOMIC_LOAD_NAND_I32_POSTRA |
| 4427 |
0U, // ATOMIC_LOAD_NAND_I64 |
4427 |
0U, // ATOMIC_LOAD_NAND_I64 |
| 4428 |
0U, // ATOMIC_LOAD_NAND_I64_POSTRA |
4428 |
0U, // ATOMIC_LOAD_NAND_I64_POSTRA |
| 4429 |
0U, // ATOMIC_LOAD_NAND_I8 |
4429 |
0U, // ATOMIC_LOAD_NAND_I8 |
| 4430 |
0U, // ATOMIC_LOAD_NAND_I8_POSTRA |
4430 |
0U, // ATOMIC_LOAD_NAND_I8_POSTRA |
| 4431 |
0U, // ATOMIC_LOAD_OR_I16 |
4431 |
0U, // ATOMIC_LOAD_OR_I16 |
| 4432 |
0U, // ATOMIC_LOAD_OR_I16_POSTRA |
4432 |
0U, // ATOMIC_LOAD_OR_I16_POSTRA |
| 4433 |
0U, // ATOMIC_LOAD_OR_I32 |
4433 |
0U, // ATOMIC_LOAD_OR_I32 |
| 4434 |
0U, // ATOMIC_LOAD_OR_I32_POSTRA |
4434 |
0U, // ATOMIC_LOAD_OR_I32_POSTRA |
| 4435 |
0U, // ATOMIC_LOAD_OR_I64 |
4435 |
0U, // ATOMIC_LOAD_OR_I64 |
| 4436 |
0U, // ATOMIC_LOAD_OR_I64_POSTRA |
4436 |
0U, // ATOMIC_LOAD_OR_I64_POSTRA |
| 4437 |
0U, // ATOMIC_LOAD_OR_I8 |
4437 |
0U, // ATOMIC_LOAD_OR_I8 |
| 4438 |
0U, // ATOMIC_LOAD_OR_I8_POSTRA |
4438 |
0U, // ATOMIC_LOAD_OR_I8_POSTRA |
| 4439 |
0U, // ATOMIC_LOAD_SUB_I16 |
4439 |
0U, // ATOMIC_LOAD_SUB_I16 |
| 4440 |
0U, // ATOMIC_LOAD_SUB_I16_POSTRA |
4440 |
0U, // ATOMIC_LOAD_SUB_I16_POSTRA |
| 4441 |
0U, // ATOMIC_LOAD_SUB_I32 |
4441 |
0U, // ATOMIC_LOAD_SUB_I32 |
| 4442 |
0U, // ATOMIC_LOAD_SUB_I32_POSTRA |
4442 |
0U, // ATOMIC_LOAD_SUB_I32_POSTRA |
| 4443 |
0U, // ATOMIC_LOAD_SUB_I64 |
4443 |
0U, // ATOMIC_LOAD_SUB_I64 |
| 4444 |
0U, // ATOMIC_LOAD_SUB_I64_POSTRA |
4444 |
0U, // ATOMIC_LOAD_SUB_I64_POSTRA |
| 4445 |
0U, // ATOMIC_LOAD_SUB_I8 |
4445 |
0U, // ATOMIC_LOAD_SUB_I8 |
| 4446 |
0U, // ATOMIC_LOAD_SUB_I8_POSTRA |
4446 |
0U, // ATOMIC_LOAD_SUB_I8_POSTRA |
| 4447 |
0U, // ATOMIC_LOAD_UMAX_I16 |
4447 |
0U, // ATOMIC_LOAD_UMAX_I16 |
| 4448 |
0U, // ATOMIC_LOAD_UMAX_I16_POSTRA |
4448 |
0U, // ATOMIC_LOAD_UMAX_I16_POSTRA |
| 4449 |
0U, // ATOMIC_LOAD_UMAX_I32 |
4449 |
0U, // ATOMIC_LOAD_UMAX_I32 |
| 4450 |
0U, // ATOMIC_LOAD_UMAX_I32_POSTRA |
4450 |
0U, // ATOMIC_LOAD_UMAX_I32_POSTRA |
| 4451 |
0U, // ATOMIC_LOAD_UMAX_I64 |
4451 |
0U, // ATOMIC_LOAD_UMAX_I64 |
| 4452 |
0U, // ATOMIC_LOAD_UMAX_I64_POSTRA |
4452 |
0U, // ATOMIC_LOAD_UMAX_I64_POSTRA |
| 4453 |
0U, // ATOMIC_LOAD_UMAX_I8 |
4453 |
0U, // ATOMIC_LOAD_UMAX_I8 |
| 4454 |
0U, // ATOMIC_LOAD_UMAX_I8_POSTRA |
4454 |
0U, // ATOMIC_LOAD_UMAX_I8_POSTRA |
| 4455 |
0U, // ATOMIC_LOAD_UMIN_I16 |
4455 |
0U, // ATOMIC_LOAD_UMIN_I16 |
| 4456 |
0U, // ATOMIC_LOAD_UMIN_I16_POSTRA |
4456 |
0U, // ATOMIC_LOAD_UMIN_I16_POSTRA |
| 4457 |
0U, // ATOMIC_LOAD_UMIN_I32 |
4457 |
0U, // ATOMIC_LOAD_UMIN_I32 |
| 4458 |
0U, // ATOMIC_LOAD_UMIN_I32_POSTRA |
4458 |
0U, // ATOMIC_LOAD_UMIN_I32_POSTRA |
| 4459 |
0U, // ATOMIC_LOAD_UMIN_I64 |
4459 |
0U, // ATOMIC_LOAD_UMIN_I64 |
| 4460 |
0U, // ATOMIC_LOAD_UMIN_I64_POSTRA |
4460 |
0U, // ATOMIC_LOAD_UMIN_I64_POSTRA |
| 4461 |
0U, // ATOMIC_LOAD_UMIN_I8 |
4461 |
0U, // ATOMIC_LOAD_UMIN_I8 |
| 4462 |
0U, // ATOMIC_LOAD_UMIN_I8_POSTRA |
4462 |
0U, // ATOMIC_LOAD_UMIN_I8_POSTRA |
| 4463 |
0U, // ATOMIC_LOAD_XOR_I16 |
4463 |
0U, // ATOMIC_LOAD_XOR_I16 |
| 4464 |
0U, // ATOMIC_LOAD_XOR_I16_POSTRA |
4464 |
0U, // ATOMIC_LOAD_XOR_I16_POSTRA |
| 4465 |
0U, // ATOMIC_LOAD_XOR_I32 |
4465 |
0U, // ATOMIC_LOAD_XOR_I32 |
| 4466 |
0U, // ATOMIC_LOAD_XOR_I32_POSTRA |
4466 |
0U, // ATOMIC_LOAD_XOR_I32_POSTRA |
| 4467 |
0U, // ATOMIC_LOAD_XOR_I64 |
4467 |
0U, // ATOMIC_LOAD_XOR_I64 |
| 4468 |
0U, // ATOMIC_LOAD_XOR_I64_POSTRA |
4468 |
0U, // ATOMIC_LOAD_XOR_I64_POSTRA |
| 4469 |
0U, // ATOMIC_LOAD_XOR_I8 |
4469 |
0U, // ATOMIC_LOAD_XOR_I8 |
| 4470 |
0U, // ATOMIC_LOAD_XOR_I8_POSTRA |
4470 |
0U, // ATOMIC_LOAD_XOR_I8_POSTRA |
| 4471 |
0U, // ATOMIC_SWAP_I16 |
4471 |
0U, // ATOMIC_SWAP_I16 |
| 4472 |
0U, // ATOMIC_SWAP_I16_POSTRA |
4472 |
0U, // ATOMIC_SWAP_I16_POSTRA |
| 4473 |
0U, // ATOMIC_SWAP_I32 |
4473 |
0U, // ATOMIC_SWAP_I32 |
| 4474 |
0U, // ATOMIC_SWAP_I32_POSTRA |
4474 |
0U, // ATOMIC_SWAP_I32_POSTRA |
| 4475 |
0U, // ATOMIC_SWAP_I64 |
4475 |
0U, // ATOMIC_SWAP_I64 |
| 4476 |
0U, // ATOMIC_SWAP_I64_POSTRA |
4476 |
0U, // ATOMIC_SWAP_I64_POSTRA |
| 4477 |
0U, // ATOMIC_SWAP_I8 |
4477 |
0U, // ATOMIC_SWAP_I8 |
| 4478 |
0U, // ATOMIC_SWAP_I8_POSTRA |
4478 |
0U, // ATOMIC_SWAP_I8_POSTRA |
| 4479 |
0U, // B |
4479 |
0U, // B |
| 4480 |
0U, // BAL_BR |
4480 |
0U, // BAL_BR |
| 4481 |
0U, // BAL_BR_MM |
4481 |
0U, // BAL_BR_MM |
| 4482 |
0U, // BEQLImmMacro |
4482 |
0U, // BEQLImmMacro |
| 4483 |
0U, // BGE |
4483 |
0U, // BGE |
| 4484 |
0U, // BGEImmMacro |
4484 |
0U, // BGEImmMacro |
| 4485 |
0U, // BGEL |
4485 |
0U, // BGEL |
| 4486 |
0U, // BGELImmMacro |
4486 |
0U, // BGELImmMacro |
| 4487 |
0U, // BGEU |
4487 |
0U, // BGEU |
| 4488 |
0U, // BGEUImmMacro |
4488 |
0U, // BGEUImmMacro |
| 4489 |
0U, // BGEUL |
4489 |
0U, // BGEUL |
| 4490 |
0U, // BGEULImmMacro |
4490 |
0U, // BGEULImmMacro |
| 4491 |
0U, // BGT |
4491 |
0U, // BGT |
| 4492 |
0U, // BGTImmMacro |
4492 |
0U, // BGTImmMacro |
| 4493 |
0U, // BGTL |
4493 |
0U, // BGTL |
| 4494 |
0U, // BGTLImmMacro |
4494 |
0U, // BGTLImmMacro |
| 4495 |
0U, // BGTU |
4495 |
0U, // BGTU |
| 4496 |
0U, // BGTUImmMacro |
4496 |
0U, // BGTUImmMacro |
| 4497 |
0U, // BGTUL |
4497 |
0U, // BGTUL |
| 4498 |
0U, // BGTULImmMacro |
4498 |
0U, // BGTULImmMacro |
| 4499 |
0U, // BLE |
4499 |
0U, // BLE |
| 4500 |
0U, // BLEImmMacro |
4500 |
0U, // BLEImmMacro |
| 4501 |
0U, // BLEL |
4501 |
0U, // BLEL |
| 4502 |
0U, // BLELImmMacro |
4502 |
0U, // BLELImmMacro |
| 4503 |
0U, // BLEU |
4503 |
0U, // BLEU |
| 4504 |
0U, // BLEUImmMacro |
4504 |
0U, // BLEUImmMacro |
| 4505 |
0U, // BLEUL |
4505 |
0U, // BLEUL |
| 4506 |
0U, // BLEULImmMacro |
4506 |
0U, // BLEULImmMacro |
| 4507 |
0U, // BLT |
4507 |
0U, // BLT |
| 4508 |
0U, // BLTImmMacro |
4508 |
0U, // BLTImmMacro |
| 4509 |
0U, // BLTL |
4509 |
0U, // BLTL |
| 4510 |
0U, // BLTLImmMacro |
4510 |
0U, // BLTLImmMacro |
| 4511 |
0U, // BLTU |
4511 |
0U, // BLTU |
| 4512 |
0U, // BLTUImmMacro |
4512 |
0U, // BLTUImmMacro |
| 4513 |
0U, // BLTUL |
4513 |
0U, // BLTUL |
| 4514 |
0U, // BLTULImmMacro |
4514 |
0U, // BLTULImmMacro |
| 4515 |
0U, // BNELImmMacro |
4515 |
0U, // BNELImmMacro |
| 4516 |
0U, // BPOSGE32_PSEUDO |
4516 |
0U, // BPOSGE32_PSEUDO |
| 4517 |
0U, // BSEL_D_PSEUDO |
4517 |
0U, // BSEL_D_PSEUDO |
| 4518 |
0U, // BSEL_FD_PSEUDO |
4518 |
0U, // BSEL_FD_PSEUDO |
| 4519 |
0U, // BSEL_FW_PSEUDO |
4519 |
0U, // BSEL_FW_PSEUDO |
| 4520 |
0U, // BSEL_H_PSEUDO |
4520 |
0U, // BSEL_H_PSEUDO |
| 4521 |
0U, // BSEL_W_PSEUDO |
4521 |
0U, // BSEL_W_PSEUDO |
| 4522 |
0U, // B_MM |
4522 |
0U, // B_MM |
| 4523 |
0U, // B_MMR6_Pseudo |
4523 |
0U, // B_MMR6_Pseudo |
| 4524 |
0U, // B_MM_Pseudo |
4524 |
0U, // B_MM_Pseudo |
| 4525 |
0U, // BeqImm |
4525 |
0U, // BeqImm |
| 4526 |
0U, // BneImm |
4526 |
0U, // BneImm |
| 4527 |
0U, // BteqzT8CmpX16 |
4527 |
0U, // BteqzT8CmpX16 |
| 4528 |
0U, // BteqzT8CmpiX16 |
4528 |
0U, // BteqzT8CmpiX16 |
| 4529 |
0U, // BteqzT8SltX16 |
4529 |
0U, // BteqzT8SltX16 |
| 4530 |
0U, // BteqzT8SltiX16 |
4530 |
0U, // BteqzT8SltiX16 |
| 4531 |
0U, // BteqzT8SltiuX16 |
4531 |
0U, // BteqzT8SltiuX16 |
| 4532 |
0U, // BteqzT8SltuX16 |
4532 |
0U, // BteqzT8SltuX16 |
| 4533 |
0U, // BtnezT8CmpX16 |
4533 |
0U, // BtnezT8CmpX16 |
| 4534 |
0U, // BtnezT8CmpiX16 |
4534 |
0U, // BtnezT8CmpiX16 |
| 4535 |
0U, // BtnezT8SltX16 |
4535 |
0U, // BtnezT8SltX16 |
| 4536 |
0U, // BtnezT8SltiX16 |
4536 |
0U, // BtnezT8SltiX16 |
| 4537 |
0U, // BtnezT8SltiuX16 |
4537 |
0U, // BtnezT8SltiuX16 |
| 4538 |
0U, // BtnezT8SltuX16 |
4538 |
0U, // BtnezT8SltuX16 |
| 4539 |
0U, // BuildPairF64 |
4539 |
0U, // BuildPairF64 |
| 4540 |
0U, // BuildPairF64_64 |
4540 |
0U, // BuildPairF64_64 |
| 4541 |
0U, // CFTC1 |
4541 |
0U, // CFTC1 |
| 4542 |
0U, // CONSTPOOL_ENTRY |
4542 |
0U, // CONSTPOOL_ENTRY |
| 4543 |
0U, // COPY_FD_PSEUDO |
4543 |
0U, // COPY_FD_PSEUDO |
| 4544 |
0U, // COPY_FW_PSEUDO |
4544 |
0U, // COPY_FW_PSEUDO |
| 4545 |
0U, // CTTC1 |
4545 |
0U, // CTTC1 |
| 4546 |
0U, // Constant32 |
4546 |
0U, // Constant32 |
| 4547 |
4U, // DMULImmMacro |
4547 |
4U, // DMULImmMacro |
| 4548 |
4U, // DMULMacro |
4548 |
4U, // DMULMacro |
| 4549 |
4U, // DMULOMacro |
4549 |
4U, // DMULOMacro |
| 4550 |
4U, // DMULOUMacro |
4550 |
4U, // DMULOUMacro |
| 4551 |
4U, // DROL |
4551 |
4U, // DROL |
| 4552 |
4U, // DROLImm |
4552 |
4U, // DROLImm |
| 4553 |
4U, // DROR |
4553 |
4U, // DROR |
| 4554 |
4U, // DRORImm |
4554 |
4U, // DRORImm |
| 4555 |
4U, // DSDivIMacro |
4555 |
4U, // DSDivIMacro |
| 4556 |
4U, // DSDivMacro |
4556 |
4U, // DSDivMacro |
| 4557 |
4U, // DSRemIMacro |
4557 |
4U, // DSRemIMacro |
| 4558 |
4U, // DSRemMacro |
4558 |
4U, // DSRemMacro |
| 4559 |
4U, // DUDivIMacro |
4559 |
4U, // DUDivIMacro |
| 4560 |
4U, // DUDivMacro |
4560 |
4U, // DUDivMacro |
| 4561 |
4U, // DURemIMacro |
4561 |
4U, // DURemIMacro |
| 4562 |
4U, // DURemMacro |
4562 |
4U, // DURemMacro |
| 4563 |
0U, // ERet |
4563 |
0U, // ERet |
| 4564 |
0U, // ExtractElementF64 |
4564 |
0U, // ExtractElementF64 |
| 4565 |
0U, // ExtractElementF64_64 |
4565 |
0U, // ExtractElementF64_64 |
| 4566 |
0U, // FABS_D |
4566 |
0U, // FABS_D |
| 4567 |
0U, // FABS_W |
4567 |
0U, // FABS_W |
| 4568 |
0U, // FEXP2_D_1_PSEUDO |
4568 |
0U, // FEXP2_D_1_PSEUDO |
| 4569 |
0U, // FEXP2_W_1_PSEUDO |
4569 |
0U, // FEXP2_W_1_PSEUDO |
| 4570 |
0U, // FILL_FD_PSEUDO |
4570 |
0U, // FILL_FD_PSEUDO |
| 4571 |
0U, // FILL_FW_PSEUDO |
4571 |
0U, // FILL_FW_PSEUDO |
| 4572 |
0U, // GotPrologue16 |
4572 |
0U, // GotPrologue16 |
| 4573 |
0U, // INSERT_B_VIDX64_PSEUDO |
4573 |
0U, // INSERT_B_VIDX64_PSEUDO |
| 4574 |
0U, // INSERT_B_VIDX_PSEUDO |
4574 |
0U, // INSERT_B_VIDX_PSEUDO |
| 4575 |
0U, // INSERT_D_VIDX64_PSEUDO |
4575 |
0U, // INSERT_D_VIDX64_PSEUDO |
| 4576 |
0U, // INSERT_D_VIDX_PSEUDO |
4576 |
0U, // INSERT_D_VIDX_PSEUDO |
| 4577 |
0U, // INSERT_FD_PSEUDO |
4577 |
0U, // INSERT_FD_PSEUDO |
| 4578 |
0U, // INSERT_FD_VIDX64_PSEUDO |
4578 |
0U, // INSERT_FD_VIDX64_PSEUDO |
| 4579 |
0U, // INSERT_FD_VIDX_PSEUDO |
4579 |
0U, // INSERT_FD_VIDX_PSEUDO |
| 4580 |
0U, // INSERT_FW_PSEUDO |
4580 |
0U, // INSERT_FW_PSEUDO |
| 4581 |
0U, // INSERT_FW_VIDX64_PSEUDO |
4581 |
0U, // INSERT_FW_VIDX64_PSEUDO |
| 4582 |
0U, // INSERT_FW_VIDX_PSEUDO |
4582 |
0U, // INSERT_FW_VIDX_PSEUDO |
| 4583 |
0U, // INSERT_H_VIDX64_PSEUDO |
4583 |
0U, // INSERT_H_VIDX64_PSEUDO |
| 4584 |
0U, // INSERT_H_VIDX_PSEUDO |
4584 |
0U, // INSERT_H_VIDX_PSEUDO |
| 4585 |
0U, // INSERT_W_VIDX64_PSEUDO |
4585 |
0U, // INSERT_W_VIDX64_PSEUDO |
| 4586 |
0U, // INSERT_W_VIDX_PSEUDO |
4586 |
0U, // INSERT_W_VIDX_PSEUDO |
| 4587 |
0U, // JALR64Pseudo |
4587 |
0U, // JALR64Pseudo |
| 4588 |
0U, // JALRHB64Pseudo |
4588 |
0U, // JALRHB64Pseudo |
| 4589 |
0U, // JALRHBPseudo |
4589 |
0U, // JALRHBPseudo |
| 4590 |
0U, // JALRPseudo |
4590 |
0U, // JALRPseudo |
| 4591 |
0U, // JAL_MMR6 |
4591 |
0U, // JAL_MMR6 |
| 4592 |
0U, // JalOneReg |
4592 |
0U, // JalOneReg |
| 4593 |
0U, // JalTwoReg |
4593 |
0U, // JalTwoReg |
| 4594 |
0U, // LDMacro |
4594 |
0U, // LDMacro |
| 4595 |
0U, // LDR_D |
4595 |
0U, // LDR_D |
| 4596 |
0U, // LDR_W |
4596 |
0U, // LDR_W |
| 4597 |
0U, // LD_F16 |
4597 |
0U, // LD_F16 |
| 4598 |
0U, // LOAD_ACC128 |
4598 |
0U, // LOAD_ACC128 |
| 4599 |
0U, // LOAD_ACC64 |
4599 |
0U, // LOAD_ACC64 |
| 4600 |
0U, // LOAD_ACC64DSP |
4600 |
0U, // LOAD_ACC64DSP |
| 4601 |
0U, // LOAD_CCOND_DSP |
4601 |
0U, // LOAD_CCOND_DSP |
| 4602 |
0U, // LONG_BRANCH_ADDiu |
4602 |
0U, // LONG_BRANCH_ADDiu |
| 4603 |
0U, // LONG_BRANCH_ADDiu2Op |
4603 |
0U, // LONG_BRANCH_ADDiu2Op |
| 4604 |
0U, // LONG_BRANCH_DADDiu |
4604 |
0U, // LONG_BRANCH_DADDiu |
| 4605 |
0U, // LONG_BRANCH_DADDiu2Op |
4605 |
0U, // LONG_BRANCH_DADDiu2Op |
| 4606 |
0U, // LONG_BRANCH_LUi |
4606 |
0U, // LONG_BRANCH_LUi |
| 4607 |
0U, // LONG_BRANCH_LUi2Op |
4607 |
0U, // LONG_BRANCH_LUi2Op |
| 4608 |
0U, // LONG_BRANCH_LUi2Op_64 |
4608 |
0U, // LONG_BRANCH_LUi2Op_64 |
| 4609 |
0U, // LWM_MM |
4609 |
0U, // LWM_MM |
| 4610 |
0U, // LoadAddrImm32 |
4610 |
0U, // LoadAddrImm32 |
| 4611 |
0U, // LoadAddrImm64 |
4611 |
0U, // LoadAddrImm64 |
| 4612 |
0U, // LoadAddrReg32 |
4612 |
0U, // LoadAddrReg32 |
| 4613 |
0U, // LoadAddrReg64 |
4613 |
0U, // LoadAddrReg64 |
| 4614 |
0U, // LoadImm32 |
4614 |
0U, // LoadImm32 |
| 4615 |
0U, // LoadImm64 |
4615 |
0U, // LoadImm64 |
| 4616 |
0U, // LoadImmDoubleFGR |
4616 |
0U, // LoadImmDoubleFGR |
| 4617 |
0U, // LoadImmDoubleFGR_32 |
4617 |
0U, // LoadImmDoubleFGR_32 |
| 4618 |
0U, // LoadImmDoubleGPR |
4618 |
0U, // LoadImmDoubleGPR |
| 4619 |
0U, // LoadImmSingleFGR |
4619 |
0U, // LoadImmSingleFGR |
| 4620 |
0U, // LoadImmSingleGPR |
4620 |
0U, // LoadImmSingleGPR |
| 4621 |
0U, // LwConstant32 |
4621 |
0U, // LwConstant32 |
| 4622 |
0U, // MFTACX |
4622 |
0U, // MFTACX |
| 4623 |
8U, // MFTC0 |
4623 |
8U, // MFTC0 |
| 4624 |
0U, // MFTC1 |
4624 |
0U, // MFTC1 |
| 4625 |
0U, // MFTDSP |
4625 |
0U, // MFTDSP |
| 4626 |
0U, // MFTGPR |
4626 |
0U, // MFTGPR |
| 4627 |
0U, // MFTHC1 |
4627 |
0U, // MFTHC1 |
| 4628 |
0U, // MFTHI |
4628 |
0U, // MFTHI |
| 4629 |
0U, // MFTLO |
4629 |
0U, // MFTLO |
| 4630 |
0U, // MIPSeh_return32 |
4630 |
0U, // MIPSeh_return32 |
| 4631 |
0U, // MIPSeh_return64 |
4631 |
0U, // MIPSeh_return64 |
| 4632 |
0U, // MSA_FP_EXTEND_D_PSEUDO |
4632 |
0U, // MSA_FP_EXTEND_D_PSEUDO |
| 4633 |
0U, // MSA_FP_EXTEND_W_PSEUDO |
4633 |
0U, // MSA_FP_EXTEND_W_PSEUDO |
| 4634 |
0U, // MSA_FP_ROUND_D_PSEUDO |
4634 |
0U, // MSA_FP_ROUND_D_PSEUDO |
| 4635 |
0U, // MSA_FP_ROUND_W_PSEUDO |
4635 |
0U, // MSA_FP_ROUND_W_PSEUDO |
| 4636 |
0U, // MTTACX |
4636 |
0U, // MTTACX |
| 4637 |
0U, // MTTC0 |
4637 |
0U, // MTTC0 |
| 4638 |
0U, // MTTC1 |
4638 |
0U, // MTTC1 |
| 4639 |
0U, // MTTDSP |
4639 |
0U, // MTTDSP |
| 4640 |
0U, // MTTGPR |
4640 |
0U, // MTTGPR |
| 4641 |
0U, // MTTHC1 |
4641 |
0U, // MTTHC1 |
| 4642 |
0U, // MTTHI |
4642 |
0U, // MTTHI |
| 4643 |
0U, // MTTLO |
4643 |
0U, // MTTLO |
| 4644 |
4U, // MULImmMacro |
4644 |
4U, // MULImmMacro |
| 4645 |
4U, // MULOMacro |
4645 |
4U, // MULOMacro |
| 4646 |
4U, // MULOUMacro |
4646 |
4U, // MULOUMacro |
| 4647 |
0U, // MultRxRy16 |
4647 |
0U, // MultRxRy16 |
| 4648 |
0U, // MultRxRyRz16 |
4648 |
0U, // MultRxRyRz16 |
| 4649 |
0U, // MultuRxRy16 |
4649 |
0U, // MultuRxRy16 |
| 4650 |
0U, // MultuRxRyRz16 |
4650 |
0U, // MultuRxRyRz16 |
| 4651 |
0U, // NOP |
4651 |
0U, // NOP |
| 4652 |
4U, // NORImm |
4652 |
4U, // NORImm |
| 4653 |
4U, // NORImm64 |
4653 |
4U, // NORImm64 |
| 4654 |
0U, // NOR_V_D_PSEUDO |
4654 |
0U, // NOR_V_D_PSEUDO |
| 4655 |
0U, // NOR_V_H_PSEUDO |
4655 |
0U, // NOR_V_H_PSEUDO |
| 4656 |
0U, // NOR_V_W_PSEUDO |
4656 |
0U, // NOR_V_W_PSEUDO |
| 4657 |
0U, // OR_V_D_PSEUDO |
4657 |
0U, // OR_V_D_PSEUDO |
| 4658 |
0U, // OR_V_H_PSEUDO |
4658 |
0U, // OR_V_H_PSEUDO |
| 4659 |
0U, // OR_V_W_PSEUDO |
4659 |
0U, // OR_V_W_PSEUDO |
| 4660 |
0U, // PseudoCMPU_EQ_QB |
4660 |
0U, // PseudoCMPU_EQ_QB |
| 4661 |
0U, // PseudoCMPU_LE_QB |
4661 |
0U, // PseudoCMPU_LE_QB |
| 4662 |
0U, // PseudoCMPU_LT_QB |
4662 |
0U, // PseudoCMPU_LT_QB |
| 4663 |
0U, // PseudoCMP_EQ_PH |
4663 |
0U, // PseudoCMP_EQ_PH |
| 4664 |
0U, // PseudoCMP_LE_PH |
4664 |
0U, // PseudoCMP_LE_PH |
| 4665 |
0U, // PseudoCMP_LT_PH |
4665 |
0U, // PseudoCMP_LT_PH |
| 4666 |
0U, // PseudoCVT_D32_W |
4666 |
0U, // PseudoCVT_D32_W |
| 4667 |
0U, // PseudoCVT_D64_L |
4667 |
0U, // PseudoCVT_D64_L |
| 4668 |
0U, // PseudoCVT_D64_W |
4668 |
0U, // PseudoCVT_D64_W |
| 4669 |
0U, // PseudoCVT_S_L |
4669 |
0U, // PseudoCVT_S_L |
| 4670 |
0U, // PseudoCVT_S_W |
4670 |
0U, // PseudoCVT_S_W |
| 4671 |
0U, // PseudoDMULT |
4671 |
0U, // PseudoDMULT |
| 4672 |
0U, // PseudoDMULTu |
4672 |
0U, // PseudoDMULTu |
| 4673 |
0U, // PseudoDSDIV |
4673 |
0U, // PseudoDSDIV |
| 4674 |
0U, // PseudoDUDIV |
4674 |
0U, // PseudoDUDIV |
| 4675 |
0U, // PseudoD_SELECT_I |
4675 |
0U, // PseudoD_SELECT_I |
| 4676 |
0U, // PseudoD_SELECT_I64 |
4676 |
0U, // PseudoD_SELECT_I64 |
| 4677 |
0U, // PseudoIndirectBranch |
4677 |
0U, // PseudoIndirectBranch |
| 4678 |
0U, // PseudoIndirectBranch64 |
4678 |
0U, // PseudoIndirectBranch64 |
| 4679 |
0U, // PseudoIndirectBranch64R6 |
4679 |
0U, // PseudoIndirectBranch64R6 |
| 4680 |
0U, // PseudoIndirectBranchR6 |
4680 |
0U, // PseudoIndirectBranchR6 |
| 4681 |
0U, // PseudoIndirectBranch_MM |
4681 |
0U, // PseudoIndirectBranch_MM |
| 4682 |
0U, // PseudoIndirectBranch_MMR6 |
4682 |
0U, // PseudoIndirectBranch_MMR6 |
| 4683 |
0U, // PseudoIndirectHazardBranch |
4683 |
0U, // PseudoIndirectHazardBranch |
| 4684 |
0U, // PseudoIndirectHazardBranch64 |
4684 |
0U, // PseudoIndirectHazardBranch64 |
| 4685 |
0U, // PseudoIndrectHazardBranch64R6 |
4685 |
0U, // PseudoIndrectHazardBranch64R6 |
| 4686 |
0U, // PseudoIndrectHazardBranchR6 |
4686 |
0U, // PseudoIndrectHazardBranchR6 |
| 4687 |
0U, // PseudoMADD |
4687 |
0U, // PseudoMADD |
| 4688 |
0U, // PseudoMADDU |
4688 |
0U, // PseudoMADDU |
| 4689 |
0U, // PseudoMADDU_MM |
4689 |
0U, // PseudoMADDU_MM |
| 4690 |
0U, // PseudoMADD_MM |
4690 |
0U, // PseudoMADD_MM |
| 4691 |
0U, // PseudoMFHI |
4691 |
0U, // PseudoMFHI |
| 4692 |
0U, // PseudoMFHI64 |
4692 |
0U, // PseudoMFHI64 |
| 4693 |
0U, // PseudoMFHI_MM |
4693 |
0U, // PseudoMFHI_MM |
| 4694 |
0U, // PseudoMFLO |
4694 |
0U, // PseudoMFLO |
| 4695 |
0U, // PseudoMFLO64 |
4695 |
0U, // PseudoMFLO64 |
| 4696 |
0U, // PseudoMFLO_MM |
4696 |
0U, // PseudoMFLO_MM |
| 4697 |
0U, // PseudoMSUB |
4697 |
0U, // PseudoMSUB |
| 4698 |
0U, // PseudoMSUBU |
4698 |
0U, // PseudoMSUBU |
| 4699 |
0U, // PseudoMSUBU_MM |
4699 |
0U, // PseudoMSUBU_MM |
| 4700 |
0U, // PseudoMSUB_MM |
4700 |
0U, // PseudoMSUB_MM |
| 4701 |
0U, // PseudoMTLOHI |
4701 |
0U, // PseudoMTLOHI |
| 4702 |
0U, // PseudoMTLOHI64 |
4702 |
0U, // PseudoMTLOHI64 |
| 4703 |
0U, // PseudoMTLOHI_DSP |
4703 |
0U, // PseudoMTLOHI_DSP |
| 4704 |
0U, // PseudoMTLOHI_MM |
4704 |
0U, // PseudoMTLOHI_MM |
| 4705 |
0U, // PseudoMULT |
4705 |
0U, // PseudoMULT |
| 4706 |
0U, // PseudoMULT_MM |
4706 |
0U, // PseudoMULT_MM |
| 4707 |
0U, // PseudoMULTu |
4707 |
0U, // PseudoMULTu |
| 4708 |
0U, // PseudoMULTu_MM |
4708 |
0U, // PseudoMULTu_MM |
| 4709 |
0U, // PseudoPICK_PH |
4709 |
0U, // PseudoPICK_PH |
| 4710 |
0U, // PseudoPICK_QB |
4710 |
0U, // PseudoPICK_QB |
| 4711 |
0U, // PseudoReturn |
4711 |
0U, // PseudoReturn |
| 4712 |
0U, // PseudoReturn64 |
4712 |
0U, // PseudoReturn64 |
| 4713 |
0U, // PseudoSDIV |
4713 |
0U, // PseudoSDIV |
| 4714 |
0U, // PseudoSELECTFP_F_D32 |
4714 |
0U, // PseudoSELECTFP_F_D32 |
| 4715 |
0U, // PseudoSELECTFP_F_D64 |
4715 |
0U, // PseudoSELECTFP_F_D64 |
| 4716 |
0U, // PseudoSELECTFP_F_I |
4716 |
0U, // PseudoSELECTFP_F_I |
| 4717 |
0U, // PseudoSELECTFP_F_I64 |
4717 |
0U, // PseudoSELECTFP_F_I64 |
| 4718 |
0U, // PseudoSELECTFP_F_S |
4718 |
0U, // PseudoSELECTFP_F_S |
| 4719 |
0U, // PseudoSELECTFP_T_D32 |
4719 |
0U, // PseudoSELECTFP_T_D32 |
| 4720 |
0U, // PseudoSELECTFP_T_D64 |
4720 |
0U, // PseudoSELECTFP_T_D64 |
| 4721 |
0U, // PseudoSELECTFP_T_I |
4721 |
0U, // PseudoSELECTFP_T_I |
| 4722 |
0U, // PseudoSELECTFP_T_I64 |
4722 |
0U, // PseudoSELECTFP_T_I64 |
| 4723 |
0U, // PseudoSELECTFP_T_S |
4723 |
0U, // PseudoSELECTFP_T_S |
| 4724 |
0U, // PseudoSELECT_D32 |
4724 |
0U, // PseudoSELECT_D32 |
| 4725 |
0U, // PseudoSELECT_D64 |
4725 |
0U, // PseudoSELECT_D64 |
| 4726 |
0U, // PseudoSELECT_I |
4726 |
0U, // PseudoSELECT_I |
| 4727 |
0U, // PseudoSELECT_I64 |
4727 |
0U, // PseudoSELECT_I64 |
| 4728 |
0U, // PseudoSELECT_S |
4728 |
0U, // PseudoSELECT_S |
| 4729 |
4U, // PseudoTRUNC_W_D |
4729 |
4U, // PseudoTRUNC_W_D |
| 4730 |
4U, // PseudoTRUNC_W_D32 |
4730 |
4U, // PseudoTRUNC_W_D32 |
| 4731 |
4U, // PseudoTRUNC_W_S |
4731 |
4U, // PseudoTRUNC_W_S |
| 4732 |
0U, // PseudoUDIV |
4732 |
0U, // PseudoUDIV |
| 4733 |
4U, // ROL |
4733 |
4U, // ROL |
| 4734 |
4U, // ROLImm |
4734 |
4U, // ROLImm |
| 4735 |
4U, // ROR |
4735 |
4U, // ROR |
| 4736 |
4U, // RORImm |
4736 |
4U, // RORImm |
| 4737 |
0U, // RetRA |
4737 |
0U, // RetRA |
| 4738 |
0U, // RetRA16 |
4738 |
0U, // RetRA16 |
| 4739 |
0U, // SDC1_M1 |
4739 |
0U, // SDC1_M1 |
| 4740 |
0U, // SDIV_MM_Pseudo |
4740 |
0U, // SDIV_MM_Pseudo |
| 4741 |
0U, // SDMacro |
4741 |
0U, // SDMacro |
| 4742 |
4U, // SDivIMacro |
4742 |
4U, // SDivIMacro |
| 4743 |
4U, // SDivMacro |
4743 |
4U, // SDivMacro |
| 4744 |
4U, // SEQIMacro |
4744 |
4U, // SEQIMacro |
| 4745 |
4U, // SEQMacro |
4745 |
4U, // SEQMacro |
| 4746 |
4U, // SGE |
4746 |
4U, // SGE |
| 4747 |
4U, // SGEImm |
4747 |
4U, // SGEImm |
| 4748 |
4U, // SGEImm64 |
4748 |
4U, // SGEImm64 |
| 4749 |
4U, // SGEU |
4749 |
4U, // SGEU |
| 4750 |
4U, // SGEUImm |
4750 |
4U, // SGEUImm |
| 4751 |
4U, // SGEUImm64 |
4751 |
4U, // SGEUImm64 |
| 4752 |
4U, // SGTImm |
4752 |
4U, // SGTImm |
| 4753 |
4U, // SGTImm64 |
4753 |
4U, // SGTImm64 |
| 4754 |
4U, // SGTUImm |
4754 |
4U, // SGTUImm |
| 4755 |
4U, // SGTUImm64 |
4755 |
4U, // SGTUImm64 |
| 4756 |
4U, // SLE |
4756 |
4U, // SLE |
| 4757 |
4U, // SLEImm |
4757 |
4U, // SLEImm |
| 4758 |
4U, // SLEImm64 |
4758 |
4U, // SLEImm64 |
| 4759 |
4U, // SLEU |
4759 |
4U, // SLEU |
| 4760 |
4U, // SLEUImm |
4760 |
4U, // SLEUImm |
| 4761 |
4U, // SLEUImm64 |
4761 |
4U, // SLEUImm64 |
| 4762 |
4U, // SLTImm64 |
4762 |
4U, // SLTImm64 |
| 4763 |
4U, // SLTUImm64 |
4763 |
4U, // SLTUImm64 |
| 4764 |
4U, // SNEIMacro |
4764 |
4U, // SNEIMacro |
| 4765 |
4U, // SNEMacro |
4765 |
4U, // SNEMacro |
| 4766 |
0U, // SNZ_B_PSEUDO |
4766 |
0U, // SNZ_B_PSEUDO |
| 4767 |
0U, // SNZ_D_PSEUDO |
4767 |
0U, // SNZ_D_PSEUDO |
| 4768 |
0U, // SNZ_H_PSEUDO |
4768 |
0U, // SNZ_H_PSEUDO |
| 4769 |
0U, // SNZ_V_PSEUDO |
4769 |
0U, // SNZ_V_PSEUDO |
| 4770 |
0U, // SNZ_W_PSEUDO |
4770 |
0U, // SNZ_W_PSEUDO |
| 4771 |
4U, // SRemIMacro |
4771 |
4U, // SRemIMacro |
| 4772 |
4U, // SRemMacro |
4772 |
4U, // SRemMacro |
| 4773 |
0U, // STORE_ACC128 |
4773 |
0U, // STORE_ACC128 |
| 4774 |
0U, // STORE_ACC64 |
4774 |
0U, // STORE_ACC64 |
| 4775 |
0U, // STORE_ACC64DSP |
4775 |
0U, // STORE_ACC64DSP |
| 4776 |
0U, // STORE_CCOND_DSP |
4776 |
0U, // STORE_CCOND_DSP |
| 4777 |
0U, // STR_D |
4777 |
0U, // STR_D |
| 4778 |
0U, // STR_W |
4778 |
0U, // STR_W |
| 4779 |
0U, // ST_F16 |
4779 |
0U, // ST_F16 |
| 4780 |
0U, // SWM_MM |
4780 |
0U, // SWM_MM |
| 4781 |
0U, // SZ_B_PSEUDO |
4781 |
0U, // SZ_B_PSEUDO |
| 4782 |
0U, // SZ_D_PSEUDO |
4782 |
0U, // SZ_D_PSEUDO |
| 4783 |
0U, // SZ_H_PSEUDO |
4783 |
0U, // SZ_H_PSEUDO |
| 4784 |
0U, // SZ_V_PSEUDO |
4784 |
0U, // SZ_V_PSEUDO |
| 4785 |
0U, // SZ_W_PSEUDO |
4785 |
0U, // SZ_W_PSEUDO |
| 4786 |
0U, // SaaAddr |
4786 |
0U, // SaaAddr |
| 4787 |
0U, // SaadAddr |
4787 |
0U, // SaadAddr |
| 4788 |
0U, // SelBeqZ |
4788 |
0U, // SelBeqZ |
| 4789 |
0U, // SelBneZ |
4789 |
0U, // SelBneZ |
| 4790 |
0U, // SelTBteqZCmp |
4790 |
0U, // SelTBteqZCmp |
| 4791 |
0U, // SelTBteqZCmpi |
4791 |
0U, // SelTBteqZCmpi |
| 4792 |
0U, // SelTBteqZSlt |
4792 |
0U, // SelTBteqZSlt |
| 4793 |
0U, // SelTBteqZSlti |
4793 |
0U, // SelTBteqZSlti |
| 4794 |
0U, // SelTBteqZSltiu |
4794 |
0U, // SelTBteqZSltiu |
| 4795 |
0U, // SelTBteqZSltu |
4795 |
0U, // SelTBteqZSltu |
| 4796 |
0U, // SelTBtneZCmp |
4796 |
0U, // SelTBtneZCmp |
| 4797 |
0U, // SelTBtneZCmpi |
4797 |
0U, // SelTBtneZCmpi |
| 4798 |
0U, // SelTBtneZSlt |
4798 |
0U, // SelTBtneZSlt |
| 4799 |
0U, // SelTBtneZSlti |
4799 |
0U, // SelTBtneZSlti |
| 4800 |
0U, // SelTBtneZSltiu |
4800 |
0U, // SelTBtneZSltiu |
| 4801 |
0U, // SelTBtneZSltu |
4801 |
0U, // SelTBtneZSltu |
| 4802 |
0U, // SltCCRxRy16 |
4802 |
0U, // SltCCRxRy16 |
| 4803 |
0U, // SltiCCRxImmX16 |
4803 |
0U, // SltiCCRxImmX16 |
| 4804 |
0U, // SltiuCCRxImmX16 |
4804 |
0U, // SltiuCCRxImmX16 |
| 4805 |
0U, // SltuCCRxRy16 |
4805 |
0U, // SltuCCRxRy16 |
| 4806 |
0U, // SltuRxRyRz16 |
4806 |
0U, // SltuRxRyRz16 |
| 4807 |
0U, // TAILCALL |
4807 |
0U, // TAILCALL |
| 4808 |
0U, // TAILCALL64R6REG |
4808 |
0U, // TAILCALL64R6REG |
| 4809 |
0U, // TAILCALLHB64R6REG |
4809 |
0U, // TAILCALLHB64R6REG |
| 4810 |
0U, // TAILCALLHBR6REG |
4810 |
0U, // TAILCALLHBR6REG |
| 4811 |
0U, // TAILCALLR6REG |
4811 |
0U, // TAILCALLR6REG |
| 4812 |
0U, // TAILCALLREG |
4812 |
0U, // TAILCALLREG |
| 4813 |
0U, // TAILCALLREG64 |
4813 |
0U, // TAILCALLREG64 |
| 4814 |
0U, // TAILCALLREGHB |
4814 |
0U, // TAILCALLREGHB |
| 4815 |
0U, // TAILCALLREGHB64 |
4815 |
0U, // TAILCALLREGHB64 |
| 4816 |
0U, // TAILCALLREG_MM |
4816 |
0U, // TAILCALLREG_MM |
| 4817 |
0U, // TAILCALLREG_MMR6 |
4817 |
0U, // TAILCALLREG_MMR6 |
| 4818 |
0U, // TAILCALL_MM |
4818 |
0U, // TAILCALL_MM |
| 4819 |
0U, // TAILCALL_MMR6 |
4819 |
0U, // TAILCALL_MMR6 |
| 4820 |
0U, // TRAP |
4820 |
0U, // TRAP |
| 4821 |
0U, // TRAP_MM |
4821 |
0U, // TRAP_MM |
| 4822 |
0U, // UDIV_MM_Pseudo |
4822 |
0U, // UDIV_MM_Pseudo |
| 4823 |
4U, // UDivIMacro |
4823 |
4U, // UDivIMacro |
| 4824 |
4U, // UDivMacro |
4824 |
4U, // UDivMacro |
| 4825 |
4U, // URemIMacro |
4825 |
4U, // URemIMacro |
| 4826 |
4U, // URemMacro |
4826 |
4U, // URemMacro |
| 4827 |
0U, // Ulh |
4827 |
0U, // Ulh |
| 4828 |
0U, // Ulhu |
4828 |
0U, // Ulhu |
| 4829 |
0U, // Ulw |
4829 |
0U, // Ulw |
| 4830 |
0U, // Ush |
4830 |
0U, // Ush |
| 4831 |
0U, // Usw |
4831 |
0U, // Usw |
| 4832 |
0U, // XOR_V_D_PSEUDO |
4832 |
0U, // XOR_V_D_PSEUDO |
| 4833 |
0U, // XOR_V_H_PSEUDO |
4833 |
0U, // XOR_V_H_PSEUDO |
| 4834 |
0U, // XOR_V_W_PSEUDO |
4834 |
0U, // XOR_V_W_PSEUDO |
| 4835 |
0U, // ABSQ_S_PH |
4835 |
0U, // ABSQ_S_PH |
| 4836 |
0U, // ABSQ_S_PH_MM |
4836 |
0U, // ABSQ_S_PH_MM |
| 4837 |
0U, // ABSQ_S_QB |
4837 |
0U, // ABSQ_S_QB |
| 4838 |
0U, // ABSQ_S_QB_MMR2 |
4838 |
0U, // ABSQ_S_QB_MMR2 |
| 4839 |
0U, // ABSQ_S_W |
4839 |
0U, // ABSQ_S_W |
| 4840 |
0U, // ABSQ_S_W_MM |
4840 |
0U, // ABSQ_S_W_MM |
| 4841 |
4U, // ADD |
4841 |
4U, // ADD |
| 4842 |
0U, // ADDIUPC |
4842 |
0U, // ADDIUPC |
| 4843 |
0U, // ADDIUPC_MM |
4843 |
0U, // ADDIUPC_MM |
| 4844 |
0U, // ADDIUPC_MMR6 |
4844 |
0U, // ADDIUPC_MMR6 |
| 4845 |
0U, // ADDIUR1SP_MM |
4845 |
0U, // ADDIUR1SP_MM |
| 4846 |
4U, // ADDIUR2_MM |
4846 |
4U, // ADDIUR2_MM |
| 4847 |
0U, // ADDIUS5_MM |
4847 |
0U, // ADDIUS5_MM |
| 4848 |
0U, // ADDIUSP_MM |
4848 |
0U, // ADDIUSP_MM |
| 4849 |
4U, // ADDIU_MMR6 |
4849 |
4U, // ADDIU_MMR6 |
| 4850 |
4U, // ADDQH_PH |
4850 |
4U, // ADDQH_PH |
| 4851 |
4U, // ADDQH_PH_MMR2 |
4851 |
4U, // ADDQH_PH_MMR2 |
| 4852 |
4U, // ADDQH_R_PH |
4852 |
4U, // ADDQH_R_PH |
| 4853 |
4U, // ADDQH_R_PH_MMR2 |
4853 |
4U, // ADDQH_R_PH_MMR2 |
| 4854 |
4U, // ADDQH_R_W |
4854 |
4U, // ADDQH_R_W |
| 4855 |
4U, // ADDQH_R_W_MMR2 |
4855 |
4U, // ADDQH_R_W_MMR2 |
| 4856 |
4U, // ADDQH_W |
4856 |
4U, // ADDQH_W |
| 4857 |
4U, // ADDQH_W_MMR2 |
4857 |
4U, // ADDQH_W_MMR2 |
| 4858 |
4U, // ADDQ_PH |
4858 |
4U, // ADDQ_PH |
| 4859 |
4U, // ADDQ_PH_MM |
4859 |
4U, // ADDQ_PH_MM |
| 4860 |
4U, // ADDQ_S_PH |
4860 |
4U, // ADDQ_S_PH |
| 4861 |
4U, // ADDQ_S_PH_MM |
4861 |
4U, // ADDQ_S_PH_MM |
| 4862 |
4U, // ADDQ_S_W |
4862 |
4U, // ADDQ_S_W |
| 4863 |
4U, // ADDQ_S_W_MM |
4863 |
4U, // ADDQ_S_W_MM |
| 4864 |
4U, // ADDR_PS64 |
4864 |
4U, // ADDR_PS64 |
| 4865 |
4U, // ADDSC |
4865 |
4U, // ADDSC |
| 4866 |
4U, // ADDSC_MM |
4866 |
4U, // ADDSC_MM |
| 4867 |
4U, // ADDS_A_B |
4867 |
4U, // ADDS_A_B |
| 4868 |
4U, // ADDS_A_D |
4868 |
4U, // ADDS_A_D |
| 4869 |
4U, // ADDS_A_H |
4869 |
4U, // ADDS_A_H |
| 4870 |
4U, // ADDS_A_W |
4870 |
4U, // ADDS_A_W |
| 4871 |
4U, // ADDS_S_B |
4871 |
4U, // ADDS_S_B |
| 4872 |
4U, // ADDS_S_D |
4872 |
4U, // ADDS_S_D |
| 4873 |
4U, // ADDS_S_H |
4873 |
4U, // ADDS_S_H |
| 4874 |
4U, // ADDS_S_W |
4874 |
4U, // ADDS_S_W |
| 4875 |
4U, // ADDS_U_B |
4875 |
4U, // ADDS_U_B |
| 4876 |
4U, // ADDS_U_D |
4876 |
4U, // ADDS_U_D |
| 4877 |
4U, // ADDS_U_H |
4877 |
4U, // ADDS_U_H |
| 4878 |
4U, // ADDS_U_W |
4878 |
4U, // ADDS_U_W |
| 4879 |
4U, // ADDU16_MM |
4879 |
4U, // ADDU16_MM |
| 4880 |
4U, // ADDU16_MMR6 |
4880 |
4U, // ADDU16_MMR6 |
| 4881 |
4U, // ADDUH_QB |
4881 |
4U, // ADDUH_QB |
| 4882 |
4U, // ADDUH_QB_MMR2 |
4882 |
4U, // ADDUH_QB_MMR2 |
| 4883 |
4U, // ADDUH_R_QB |
4883 |
4U, // ADDUH_R_QB |
| 4884 |
4U, // ADDUH_R_QB_MMR2 |
4884 |
4U, // ADDUH_R_QB_MMR2 |
| 4885 |
4U, // ADDU_MMR6 |
4885 |
4U, // ADDU_MMR6 |
| 4886 |
4U, // ADDU_PH |
4886 |
4U, // ADDU_PH |
| 4887 |
4U, // ADDU_PH_MMR2 |
4887 |
4U, // ADDU_PH_MMR2 |
| 4888 |
4U, // ADDU_QB |
4888 |
4U, // ADDU_QB |
| 4889 |
4U, // ADDU_QB_MM |
4889 |
4U, // ADDU_QB_MM |
| 4890 |
4U, // ADDU_S_PH |
4890 |
4U, // ADDU_S_PH |
| 4891 |
4U, // ADDU_S_PH_MMR2 |
4891 |
4U, // ADDU_S_PH_MMR2 |
| 4892 |
4U, // ADDU_S_QB |
4892 |
4U, // ADDU_S_QB |
| 4893 |
4U, // ADDU_S_QB_MM |
4893 |
4U, // ADDU_S_QB_MM |
| 4894 |
12U, // ADDVI_B |
4894 |
12U, // ADDVI_B |
| 4895 |
12U, // ADDVI_D |
4895 |
12U, // ADDVI_D |
| 4896 |
12U, // ADDVI_H |
4896 |
12U, // ADDVI_H |
| 4897 |
12U, // ADDVI_W |
4897 |
12U, // ADDVI_W |
| 4898 |
4U, // ADDV_B |
4898 |
4U, // ADDV_B |
| 4899 |
4U, // ADDV_D |
4899 |
4U, // ADDV_D |
| 4900 |
4U, // ADDV_H |
4900 |
4U, // ADDV_H |
| 4901 |
4U, // ADDV_W |
4901 |
4U, // ADDV_W |
| 4902 |
4U, // ADDWC |
4902 |
4U, // ADDWC |
| 4903 |
4U, // ADDWC_MM |
4903 |
4U, // ADDWC_MM |
| 4904 |
4U, // ADD_A_B |
4904 |
4U, // ADD_A_B |
| 4905 |
4U, // ADD_A_D |
4905 |
4U, // ADD_A_D |
| 4906 |
4U, // ADD_A_H |
4906 |
4U, // ADD_A_H |
| 4907 |
4U, // ADD_A_W |
4907 |
4U, // ADD_A_W |
| 4908 |
4U, // ADD_MM |
4908 |
4U, // ADD_MM |
| 4909 |
4U, // ADD_MMR6 |
4909 |
4U, // ADD_MMR6 |
| 4910 |
4U, // ADDi |
4910 |
4U, // ADDi |
| 4911 |
4U, // ADDi_MM |
4911 |
4U, // ADDi_MM |
| 4912 |
4U, // ADDiu |
4912 |
4U, // ADDiu |
| 4913 |
4U, // ADDiu_MM |
4913 |
4U, // ADDiu_MM |
| 4914 |
4U, // ADDu |
4914 |
4U, // ADDu |
| 4915 |
4U, // ADDu_MM |
4915 |
4U, // ADDu_MM |
| 4916 |
132U, // ALIGN |
4916 |
132U, // ALIGN |
| 4917 |
132U, // ALIGN_MMR6 |
4917 |
132U, // ALIGN_MMR6 |
| 4918 |
0U, // ALUIPC |
4918 |
0U, // ALUIPC |
| 4919 |
0U, // ALUIPC_MMR6 |
4919 |
0U, // ALUIPC_MMR6 |
| 4920 |
4U, // AND |
4920 |
4U, // AND |
| 4921 |
0U, // AND16_MM |
4921 |
0U, // AND16_MM |
| 4922 |
0U, // AND16_MMR6 |
4922 |
0U, // AND16_MMR6 |
| 4923 |
4U, // AND64 |
4923 |
4U, // AND64 |
| 4924 |
4U, // ANDI16_MM |
4924 |
4U, // ANDI16_MM |
| 4925 |
4U, // ANDI16_MMR6 |
4925 |
4U, // ANDI16_MMR6 |
| 4926 |
16U, // ANDI_B |
4926 |
16U, // ANDI_B |
| 4927 |
20U, // ANDI_MMR6 |
4927 |
20U, // ANDI_MMR6 |
| 4928 |
4U, // AND_MM |
4928 |
4U, // AND_MM |
| 4929 |
4U, // AND_MMR6 |
4929 |
4U, // AND_MMR6 |
| 4930 |
4U, // AND_V |
4930 |
4U, // AND_V |
| 4931 |
20U, // ANDi |
4931 |
20U, // ANDi |
| 4932 |
20U, // ANDi64 |
4932 |
20U, // ANDi64 |
| 4933 |
20U, // ANDi_MM |
4933 |
20U, // ANDi_MM |
| 4934 |
12U, // APPEND |
4934 |
12U, // APPEND |
| 4935 |
12U, // APPEND_MMR2 |
4935 |
12U, // APPEND_MMR2 |
| 4936 |
4U, // ASUB_S_B |
4936 |
4U, // ASUB_S_B |
| 4937 |
4U, // ASUB_S_D |
4937 |
4U, // ASUB_S_D |
| 4938 |
4U, // ASUB_S_H |
4938 |
4U, // ASUB_S_H |
| 4939 |
4U, // ASUB_S_W |
4939 |
4U, // ASUB_S_W |
| 4940 |
4U, // ASUB_U_B |
4940 |
4U, // ASUB_U_B |
| 4941 |
4U, // ASUB_U_D |
4941 |
4U, // ASUB_U_D |
| 4942 |
4U, // ASUB_U_H |
4942 |
4U, // ASUB_U_H |
| 4943 |
4U, // ASUB_U_W |
4943 |
4U, // ASUB_U_W |
| 4944 |
20U, // AUI |
4944 |
20U, // AUI |
| 4945 |
0U, // AUIPC |
4945 |
0U, // AUIPC |
| 4946 |
0U, // AUIPC_MMR6 |
4946 |
0U, // AUIPC_MMR6 |
| 4947 |
20U, // AUI_MMR6 |
4947 |
20U, // AUI_MMR6 |
| 4948 |
4U, // AVER_S_B |
4948 |
4U, // AVER_S_B |
| 4949 |
4U, // AVER_S_D |
4949 |
4U, // AVER_S_D |
| 4950 |
4U, // AVER_S_H |
4950 |
4U, // AVER_S_H |
| 4951 |
4U, // AVER_S_W |
4951 |
4U, // AVER_S_W |
| 4952 |
4U, // AVER_U_B |
4952 |
4U, // AVER_U_B |
| 4953 |
4U, // AVER_U_D |
4953 |
4U, // AVER_U_D |
| 4954 |
4U, // AVER_U_H |
4954 |
4U, // AVER_U_H |
| 4955 |
4U, // AVER_U_W |
4955 |
4U, // AVER_U_W |
| 4956 |
4U, // AVE_S_B |
4956 |
4U, // AVE_S_B |
| 4957 |
4U, // AVE_S_D |
4957 |
4U, // AVE_S_D |
| 4958 |
4U, // AVE_S_H |
4958 |
4U, // AVE_S_H |
| 4959 |
4U, // AVE_S_W |
4959 |
4U, // AVE_S_W |
| 4960 |
4U, // AVE_U_B |
4960 |
4U, // AVE_U_B |
| 4961 |
4U, // AVE_U_D |
4961 |
4U, // AVE_U_D |
| 4962 |
4U, // AVE_U_H |
4962 |
4U, // AVE_U_H |
| 4963 |
4U, // AVE_U_W |
4963 |
4U, // AVE_U_W |
| 4964 |
0U, // AddiuRxImmX16 |
4964 |
0U, // AddiuRxImmX16 |
| 4965 |
0U, // AddiuRxPcImmX16 |
4965 |
0U, // AddiuRxPcImmX16 |
| 4966 |
1U, // AddiuRxRxImm16 |
4966 |
1U, // AddiuRxRxImm16 |
| 4967 |
0U, // AddiuRxRxImmX16 |
4967 |
0U, // AddiuRxRxImmX16 |
| 4968 |
0U, // AddiuRxRyOffMemX16 |
4968 |
0U, // AddiuRxRyOffMemX16 |
| 4969 |
0U, // AddiuSpImm16 |
4969 |
0U, // AddiuSpImm16 |
| 4970 |
0U, // AddiuSpImmX16 |
4970 |
0U, // AddiuSpImmX16 |
| 4971 |
4U, // AdduRxRyRz16 |
4971 |
4U, // AdduRxRyRz16 |
| 4972 |
0U, // AndRxRxRy16 |
4972 |
0U, // AndRxRxRy16 |
| 4973 |
0U, // B16_MM |
4973 |
0U, // B16_MM |
| 4974 |
4U, // BADDu |
4974 |
4U, // BADDu |
| 4975 |
0U, // BAL |
4975 |
0U, // BAL |
| 4976 |
0U, // BALC |
4976 |
0U, // BALC |
| 4977 |
0U, // BALC_MMR6 |
4977 |
0U, // BALC_MMR6 |
| 4978 |
24U, // BALIGN |
4978 |
24U, // BALIGN |
| 4979 |
24U, // BALIGN_MMR2 |
4979 |
24U, // BALIGN_MMR2 |
| 4980 |
0U, // BBIT0 |
4980 |
0U, // BBIT0 |
| 4981 |
0U, // BBIT032 |
4981 |
0U, // BBIT032 |
| 4982 |
0U, // BBIT1 |
4982 |
0U, // BBIT1 |
| 4983 |
0U, // BBIT132 |
4983 |
0U, // BBIT132 |
| 4984 |
0U, // BC |
4984 |
0U, // BC |
| 4985 |
0U, // BC16_MMR6 |
4985 |
0U, // BC16_MMR6 |
| 4986 |
0U, // BC1EQZ |
4986 |
0U, // BC1EQZ |
| 4987 |
0U, // BC1EQZC_MMR6 |
4987 |
0U, // BC1EQZC_MMR6 |
| 4988 |
0U, // BC1F |
4988 |
0U, // BC1F |
| 4989 |
0U, // BC1FL |
4989 |
0U, // BC1FL |
| 4990 |
0U, // BC1F_MM |
4990 |
0U, // BC1F_MM |
| 4991 |
0U, // BC1NEZ |
4991 |
0U, // BC1NEZ |
| 4992 |
0U, // BC1NEZC_MMR6 |
4992 |
0U, // BC1NEZC_MMR6 |
| 4993 |
0U, // BC1T |
4993 |
0U, // BC1T |
| 4994 |
0U, // BC1TL |
4994 |
0U, // BC1TL |
| 4995 |
0U, // BC1T_MM |
4995 |
0U, // BC1T_MM |
| 4996 |
0U, // BC2EQZ |
4996 |
0U, // BC2EQZ |
| 4997 |
0U, // BC2EQZC_MMR6 |
4997 |
0U, // BC2EQZC_MMR6 |
| 4998 |
0U, // BC2NEZ |
4998 |
0U, // BC2NEZ |
| 4999 |
0U, // BC2NEZC_MMR6 |
4999 |
0U, // BC2NEZC_MMR6 |
| 5000 |
8U, // BCLRI_B |
5000 |
8U, // BCLRI_B |
| 5001 |
28U, // BCLRI_D |
5001 |
28U, // BCLRI_D |
| 5002 |
32U, // BCLRI_H |
5002 |
32U, // BCLRI_H |
| 5003 |
12U, // BCLRI_W |
5003 |
12U, // BCLRI_W |
| 5004 |
4U, // BCLR_B |
5004 |
4U, // BCLR_B |
| 5005 |
4U, // BCLR_D |
5005 |
4U, // BCLR_D |
| 5006 |
4U, // BCLR_H |
5006 |
4U, // BCLR_H |
| 5007 |
4U, // BCLR_W |
5007 |
4U, // BCLR_W |
| 5008 |
0U, // BC_MMR6 |
5008 |
0U, // BC_MMR6 |
| 5009 |
0U, // BEQ |
5009 |
0U, // BEQ |
| 5010 |
0U, // BEQ64 |
5010 |
0U, // BEQ64 |
| 5011 |
0U, // BEQC |
5011 |
0U, // BEQC |
| 5012 |
0U, // BEQC64 |
5012 |
0U, // BEQC64 |
| 5013 |
0U, // BEQC_MMR6 |
5013 |
0U, // BEQC_MMR6 |
| 5014 |
0U, // BEQL |
5014 |
0U, // BEQL |
| 5015 |
0U, // BEQZ16_MM |
5015 |
0U, // BEQZ16_MM |
| 5016 |
0U, // BEQZALC |
5016 |
0U, // BEQZALC |
| 5017 |
0U, // BEQZALC_MMR6 |
5017 |
0U, // BEQZALC_MMR6 |
| 5018 |
0U, // BEQZC |
5018 |
0U, // BEQZC |
| 5019 |
0U, // BEQZC16_MMR6 |
5019 |
0U, // BEQZC16_MMR6 |
| 5020 |
0U, // BEQZC64 |
5020 |
0U, // BEQZC64 |
| 5021 |
0U, // BEQZC_MM |
5021 |
0U, // BEQZC_MM |
| 5022 |
0U, // BEQZC_MMR6 |
5022 |
0U, // BEQZC_MMR6 |
| 5023 |
0U, // BEQ_MM |
5023 |
0U, // BEQ_MM |
| 5024 |
0U, // BGEC |
5024 |
0U, // BGEC |
| 5025 |
0U, // BGEC64 |
5025 |
0U, // BGEC64 |
| 5026 |
0U, // BGEC_MMR6 |
5026 |
0U, // BGEC_MMR6 |
| 5027 |
0U, // BGEUC |
5027 |
0U, // BGEUC |
| 5028 |
0U, // BGEUC64 |
5028 |
0U, // BGEUC64 |
| 5029 |
0U, // BGEUC_MMR6 |
5029 |
0U, // BGEUC_MMR6 |
| 5030 |
0U, // BGEZ |
5030 |
0U, // BGEZ |
| 5031 |
0U, // BGEZ64 |
5031 |
0U, // BGEZ64 |
| 5032 |
0U, // BGEZAL |
5032 |
0U, // BGEZAL |
| 5033 |
0U, // BGEZALC |
5033 |
0U, // BGEZALC |
| 5034 |
0U, // BGEZALC_MMR6 |
5034 |
0U, // BGEZALC_MMR6 |
| 5035 |
0U, // BGEZALL |
5035 |
0U, // BGEZALL |
| 5036 |
0U, // BGEZALS_MM |
5036 |
0U, // BGEZALS_MM |
| 5037 |
0U, // BGEZAL_MM |
5037 |
0U, // BGEZAL_MM |
| 5038 |
0U, // BGEZC |
5038 |
0U, // BGEZC |
| 5039 |
0U, // BGEZC64 |
5039 |
0U, // BGEZC64 |
| 5040 |
0U, // BGEZC_MMR6 |
5040 |
0U, // BGEZC_MMR6 |
| 5041 |
0U, // BGEZL |
5041 |
0U, // BGEZL |
| 5042 |
0U, // BGEZ_MM |
5042 |
0U, // BGEZ_MM |
| 5043 |
0U, // BGTZ |
5043 |
0U, // BGTZ |
| 5044 |
0U, // BGTZ64 |
5044 |
0U, // BGTZ64 |
| 5045 |
0U, // BGTZALC |
5045 |
0U, // BGTZALC |
| 5046 |
0U, // BGTZALC_MMR6 |
5046 |
0U, // BGTZALC_MMR6 |
| 5047 |
0U, // BGTZC |
5047 |
0U, // BGTZC |
| 5048 |
0U, // BGTZC64 |
5048 |
0U, // BGTZC64 |
| 5049 |
0U, // BGTZC_MMR6 |
5049 |
0U, // BGTZC_MMR6 |
| 5050 |
0U, // BGTZL |
5050 |
0U, // BGTZL |
| 5051 |
0U, // BGTZ_MM |
5051 |
0U, // BGTZ_MM |
| 5052 |
36U, // BINSLI_B |
5052 |
36U, // BINSLI_B |
| 5053 |
40U, // BINSLI_D |
5053 |
40U, // BINSLI_D |
| 5054 |
44U, // BINSLI_H |
5054 |
44U, // BINSLI_H |
| 5055 |
48U, // BINSLI_W |
5055 |
48U, // BINSLI_W |
| 5056 |
52U, // BINSL_B |
5056 |
52U, // BINSL_B |
| 5057 |
52U, // BINSL_D |
5057 |
52U, // BINSL_D |
| 5058 |
52U, // BINSL_H |
5058 |
52U, // BINSL_H |
| 5059 |
52U, // BINSL_W |
5059 |
52U, // BINSL_W |
| 5060 |
36U, // BINSRI_B |
5060 |
36U, // BINSRI_B |
| 5061 |
40U, // BINSRI_D |
5061 |
40U, // BINSRI_D |
| 5062 |
44U, // BINSRI_H |
5062 |
44U, // BINSRI_H |
| 5063 |
48U, // BINSRI_W |
5063 |
48U, // BINSRI_W |
| 5064 |
52U, // BINSR_B |
5064 |
52U, // BINSR_B |
| 5065 |
52U, // BINSR_D |
5065 |
52U, // BINSR_D |
| 5066 |
52U, // BINSR_H |
5066 |
52U, // BINSR_H |
| 5067 |
52U, // BINSR_W |
5067 |
52U, // BINSR_W |
| 5068 |
0U, // BITREV |
5068 |
0U, // BITREV |
| 5069 |
0U, // BITREV_MM |
5069 |
0U, // BITREV_MM |
| 5070 |
0U, // BITSWAP |
5070 |
0U, // BITSWAP |
| 5071 |
0U, // BITSWAP_MMR6 |
5071 |
0U, // BITSWAP_MMR6 |
| 5072 |
0U, // BLEZ |
5072 |
0U, // BLEZ |
| 5073 |
0U, // BLEZ64 |
5073 |
0U, // BLEZ64 |
| 5074 |
0U, // BLEZALC |
5074 |
0U, // BLEZALC |
| 5075 |
0U, // BLEZALC_MMR6 |
5075 |
0U, // BLEZALC_MMR6 |
| 5076 |
0U, // BLEZC |
5076 |
0U, // BLEZC |
| 5077 |
0U, // BLEZC64 |
5077 |
0U, // BLEZC64 |
| 5078 |
0U, // BLEZC_MMR6 |
5078 |
0U, // BLEZC_MMR6 |
| 5079 |
0U, // BLEZL |
5079 |
0U, // BLEZL |
| 5080 |
0U, // BLEZ_MM |
5080 |
0U, // BLEZ_MM |
| 5081 |
0U, // BLTC |
5081 |
0U, // BLTC |
| 5082 |
0U, // BLTC64 |
5082 |
0U, // BLTC64 |
| 5083 |
0U, // BLTC_MMR6 |
5083 |
0U, // BLTC_MMR6 |
| 5084 |
0U, // BLTUC |
5084 |
0U, // BLTUC |
| 5085 |
0U, // BLTUC64 |
5085 |
0U, // BLTUC64 |
| 5086 |
0U, // BLTUC_MMR6 |
5086 |
0U, // BLTUC_MMR6 |
| 5087 |
0U, // BLTZ |
5087 |
0U, // BLTZ |
| 5088 |
0U, // BLTZ64 |
5088 |
0U, // BLTZ64 |
| 5089 |
0U, // BLTZAL |
5089 |
0U, // BLTZAL |
| 5090 |
0U, // BLTZALC |
5090 |
0U, // BLTZALC |
| 5091 |
0U, // BLTZALC_MMR6 |
5091 |
0U, // BLTZALC_MMR6 |
| 5092 |
0U, // BLTZALL |
5092 |
0U, // BLTZALL |
| 5093 |
0U, // BLTZALS_MM |
5093 |
0U, // BLTZALS_MM |
| 5094 |
0U, // BLTZAL_MM |
5094 |
0U, // BLTZAL_MM |
| 5095 |
0U, // BLTZC |
5095 |
0U, // BLTZC |
| 5096 |
0U, // BLTZC64 |
5096 |
0U, // BLTZC64 |
| 5097 |
0U, // BLTZC_MMR6 |
5097 |
0U, // BLTZC_MMR6 |
| 5098 |
0U, // BLTZL |
5098 |
0U, // BLTZL |
| 5099 |
0U, // BLTZ_MM |
5099 |
0U, // BLTZ_MM |
| 5100 |
56U, // BMNZI_B |
5100 |
56U, // BMNZI_B |
| 5101 |
52U, // BMNZ_V |
5101 |
52U, // BMNZ_V |
| 5102 |
56U, // BMZI_B |
5102 |
56U, // BMZI_B |
| 5103 |
52U, // BMZ_V |
5103 |
52U, // BMZ_V |
| 5104 |
0U, // BNE |
5104 |
0U, // BNE |
| 5105 |
0U, // BNE64 |
5105 |
0U, // BNE64 |
| 5106 |
0U, // BNEC |
5106 |
0U, // BNEC |
| 5107 |
0U, // BNEC64 |
5107 |
0U, // BNEC64 |
| 5108 |
0U, // BNEC_MMR6 |
5108 |
0U, // BNEC_MMR6 |
| 5109 |
8U, // BNEGI_B |
5109 |
8U, // BNEGI_B |
| 5110 |
28U, // BNEGI_D |
5110 |
28U, // BNEGI_D |
| 5111 |
32U, // BNEGI_H |
5111 |
32U, // BNEGI_H |
| 5112 |
12U, // BNEGI_W |
5112 |
12U, // BNEGI_W |
| 5113 |
4U, // BNEG_B |
5113 |
4U, // BNEG_B |
| 5114 |
4U, // BNEG_D |
5114 |
4U, // BNEG_D |
| 5115 |
4U, // BNEG_H |
5115 |
4U, // BNEG_H |
| 5116 |
4U, // BNEG_W |
5116 |
4U, // BNEG_W |
| 5117 |
0U, // BNEL |
5117 |
0U, // BNEL |
| 5118 |
0U, // BNEZ16_MM |
5118 |
0U, // BNEZ16_MM |
| 5119 |
0U, // BNEZALC |
5119 |
0U, // BNEZALC |
| 5120 |
0U, // BNEZALC_MMR6 |
5120 |
0U, // BNEZALC_MMR6 |
| 5121 |
0U, // BNEZC |
5121 |
0U, // BNEZC |
| 5122 |
0U, // BNEZC16_MMR6 |
5122 |
0U, // BNEZC16_MMR6 |
| 5123 |
0U, // BNEZC64 |
5123 |
0U, // BNEZC64 |
| 5124 |
0U, // BNEZC_MM |
5124 |
0U, // BNEZC_MM |
| 5125 |
0U, // BNEZC_MMR6 |
5125 |
0U, // BNEZC_MMR6 |
| 5126 |
0U, // BNE_MM |
5126 |
0U, // BNE_MM |
| 5127 |
0U, // BNVC |
5127 |
0U, // BNVC |
| 5128 |
0U, // BNVC_MMR6 |
5128 |
0U, // BNVC_MMR6 |
| 5129 |
0U, // BNZ_B |
5129 |
0U, // BNZ_B |
| 5130 |
0U, // BNZ_D |
5130 |
0U, // BNZ_D |
| 5131 |
0U, // BNZ_H |
5131 |
0U, // BNZ_H |
| 5132 |
0U, // BNZ_V |
5132 |
0U, // BNZ_V |
| 5133 |
0U, // BNZ_W |
5133 |
0U, // BNZ_W |
| 5134 |
0U, // BOVC |
5134 |
0U, // BOVC |
| 5135 |
0U, // BOVC_MMR6 |
5135 |
0U, // BOVC_MMR6 |
| 5136 |
0U, // BPOSGE32 |
5136 |
0U, // BPOSGE32 |
| 5137 |
0U, // BPOSGE32C_MMR3 |
5137 |
0U, // BPOSGE32C_MMR3 |
| 5138 |
0U, // BPOSGE32_MM |
5138 |
0U, // BPOSGE32_MM |
| 5139 |
0U, // BREAK |
5139 |
0U, // BREAK |
| 5140 |
0U, // BREAK16_MM |
5140 |
0U, // BREAK16_MM |
| 5141 |
0U, // BREAK16_MMR6 |
5141 |
0U, // BREAK16_MMR6 |
| 5142 |
0U, // BREAK_MM |
5142 |
0U, // BREAK_MM |
| 5143 |
0U, // BREAK_MMR6 |
5143 |
0U, // BREAK_MMR6 |
| 5144 |
56U, // BSELI_B |
5144 |
56U, // BSELI_B |
| 5145 |
52U, // BSEL_V |
5145 |
52U, // BSEL_V |
| 5146 |
8U, // BSETI_B |
5146 |
8U, // BSETI_B |
| 5147 |
28U, // BSETI_D |
5147 |
28U, // BSETI_D |
| 5148 |
32U, // BSETI_H |
5148 |
32U, // BSETI_H |
| 5149 |
12U, // BSETI_W |
5149 |
12U, // BSETI_W |
| 5150 |
4U, // BSET_B |
5150 |
4U, // BSET_B |
| 5151 |
4U, // BSET_D |
5151 |
4U, // BSET_D |
| 5152 |
4U, // BSET_H |
5152 |
4U, // BSET_H |
| 5153 |
4U, // BSET_W |
5153 |
4U, // BSET_W |
| 5154 |
0U, // BZ_B |
5154 |
0U, // BZ_B |
| 5155 |
0U, // BZ_D |
5155 |
0U, // BZ_D |
| 5156 |
0U, // BZ_H |
5156 |
0U, // BZ_H |
| 5157 |
0U, // BZ_V |
5157 |
0U, // BZ_V |
| 5158 |
0U, // BZ_W |
5158 |
0U, // BZ_W |
| 5159 |
1U, // BeqzRxImm16 |
5159 |
1U, // BeqzRxImm16 |
| 5160 |
0U, // BeqzRxImmX16 |
5160 |
0U, // BeqzRxImmX16 |
| 5161 |
0U, // Bimm16 |
5161 |
0U, // Bimm16 |
| 5162 |
0U, // BimmX16 |
5162 |
0U, // BimmX16 |
| 5163 |
1U, // BnezRxImm16 |
5163 |
1U, // BnezRxImm16 |
| 5164 |
0U, // BnezRxImmX16 |
5164 |
0U, // BnezRxImmX16 |
| 5165 |
0U, // Break16 |
5165 |
0U, // Break16 |
| 5166 |
0U, // Bteqz16 |
5166 |
0U, // Bteqz16 |
| 5167 |
0U, // BteqzX16 |
5167 |
0U, // BteqzX16 |
| 5168 |
0U, // Btnez16 |
5168 |
0U, // Btnez16 |
| 5169 |
0U, // BtnezX16 |
5169 |
0U, // BtnezX16 |
| 5170 |
0U, // CACHE |
5170 |
0U, // CACHE |
| 5171 |
0U, // CACHEE |
5171 |
0U, // CACHEE |
| 5172 |
0U, // CACHEE_MM |
5172 |
0U, // CACHEE_MM |
| 5173 |
0U, // CACHE_MM |
5173 |
0U, // CACHE_MM |
| 5174 |
0U, // CACHE_MMR6 |
5174 |
0U, // CACHE_MMR6 |
| 5175 |
0U, // CACHE_R6 |
5175 |
0U, // CACHE_R6 |
| 5176 |
0U, // CEIL_L_D64 |
5176 |
0U, // CEIL_L_D64 |
| 5177 |
0U, // CEIL_L_D_MMR6 |
5177 |
0U, // CEIL_L_D_MMR6 |
| 5178 |
0U, // CEIL_L_S |
5178 |
0U, // CEIL_L_S |
| 5179 |
0U, // CEIL_L_S_MMR6 |
5179 |
0U, // CEIL_L_S_MMR6 |
| 5180 |
0U, // CEIL_W_D32 |
5180 |
0U, // CEIL_W_D32 |
| 5181 |
0U, // CEIL_W_D64 |
5181 |
0U, // CEIL_W_D64 |
| 5182 |
0U, // CEIL_W_D_MMR6 |
5182 |
0U, // CEIL_W_D_MMR6 |
| 5183 |
0U, // CEIL_W_MM |
5183 |
0U, // CEIL_W_MM |
| 5184 |
0U, // CEIL_W_S |
5184 |
0U, // CEIL_W_S |
| 5185 |
0U, // CEIL_W_S_MM |
5185 |
0U, // CEIL_W_S_MM |
| 5186 |
0U, // CEIL_W_S_MMR6 |
5186 |
0U, // CEIL_W_S_MMR6 |
| 5187 |
4U, // CEQI_B |
5187 |
4U, // CEQI_B |
| 5188 |
4U, // CEQI_D |
5188 |
4U, // CEQI_D |
| 5189 |
4U, // CEQI_H |
5189 |
4U, // CEQI_H |
| 5190 |
4U, // CEQI_W |
5190 |
4U, // CEQI_W |
| 5191 |
4U, // CEQ_B |
5191 |
4U, // CEQ_B |
| 5192 |
4U, // CEQ_D |
5192 |
4U, // CEQ_D |
| 5193 |
4U, // CEQ_H |
5193 |
4U, // CEQ_H |
| 5194 |
4U, // CEQ_W |
5194 |
4U, // CEQ_W |
| 5195 |
0U, // CFC1 |
5195 |
0U, // CFC1 |
| 5196 |
0U, // CFC1_MM |
5196 |
0U, // CFC1_MM |
| 5197 |
0U, // CFC2_MM |
5197 |
0U, // CFC2_MM |
| 5198 |
0U, // CFCMSA |
5198 |
0U, // CFCMSA |
| 5199 |
1164U, // CINS |
5199 |
1164U, // CINS |
| 5200 |
1164U, // CINS32 |
5200 |
1164U, // CINS32 |
| 5201 |
1164U, // CINS64_32 |
5201 |
1164U, // CINS64_32 |
| 5202 |
1164U, // CINS_i32 |
5202 |
1164U, // CINS_i32 |
| 5203 |
0U, // CLASS_D |
5203 |
0U, // CLASS_D |
| 5204 |
0U, // CLASS_D_MMR6 |
5204 |
0U, // CLASS_D_MMR6 |
| 5205 |
0U, // CLASS_S |
5205 |
0U, // CLASS_S |
| 5206 |
0U, // CLASS_S_MMR6 |
5206 |
0U, // CLASS_S_MMR6 |
| 5207 |
4U, // CLEI_S_B |
5207 |
4U, // CLEI_S_B |
| 5208 |
4U, // CLEI_S_D |
5208 |
4U, // CLEI_S_D |
| 5209 |
4U, // CLEI_S_H |
5209 |
4U, // CLEI_S_H |
| 5210 |
4U, // CLEI_S_W |
5210 |
4U, // CLEI_S_W |
| 5211 |
12U, // CLEI_U_B |
5211 |
12U, // CLEI_U_B |
| 5212 |
12U, // CLEI_U_D |
5212 |
12U, // CLEI_U_D |
| 5213 |
12U, // CLEI_U_H |
5213 |
12U, // CLEI_U_H |
| 5214 |
12U, // CLEI_U_W |
5214 |
12U, // CLEI_U_W |
| 5215 |
4U, // CLE_S_B |
5215 |
4U, // CLE_S_B |
| 5216 |
4U, // CLE_S_D |
5216 |
4U, // CLE_S_D |
| 5217 |
4U, // CLE_S_H |
5217 |
4U, // CLE_S_H |
| 5218 |
4U, // CLE_S_W |
5218 |
4U, // CLE_S_W |
| 5219 |
4U, // CLE_U_B |
5219 |
4U, // CLE_U_B |
| 5220 |
4U, // CLE_U_D |
5220 |
4U, // CLE_U_D |
| 5221 |
4U, // CLE_U_H |
5221 |
4U, // CLE_U_H |
| 5222 |
4U, // CLE_U_W |
5222 |
4U, // CLE_U_W |
| 5223 |
0U, // CLO |
5223 |
0U, // CLO |
| 5224 |
0U, // CLO_MM |
5224 |
0U, // CLO_MM |
| 5225 |
0U, // CLO_MMR6 |
5225 |
0U, // CLO_MMR6 |
| 5226 |
0U, // CLO_R6 |
5226 |
0U, // CLO_R6 |
| 5227 |
4U, // CLTI_S_B |
5227 |
4U, // CLTI_S_B |
| 5228 |
4U, // CLTI_S_D |
5228 |
4U, // CLTI_S_D |
| 5229 |
4U, // CLTI_S_H |
5229 |
4U, // CLTI_S_H |
| 5230 |
4U, // CLTI_S_W |
5230 |
4U, // CLTI_S_W |
| 5231 |
12U, // CLTI_U_B |
5231 |
12U, // CLTI_U_B |
| 5232 |
12U, // CLTI_U_D |
5232 |
12U, // CLTI_U_D |
| 5233 |
12U, // CLTI_U_H |
5233 |
12U, // CLTI_U_H |
| 5234 |
12U, // CLTI_U_W |
5234 |
12U, // CLTI_U_W |
| 5235 |
4U, // CLT_S_B |
5235 |
4U, // CLT_S_B |
| 5236 |
4U, // CLT_S_D |
5236 |
4U, // CLT_S_D |
| 5237 |
4U, // CLT_S_H |
5237 |
4U, // CLT_S_H |
| 5238 |
4U, // CLT_S_W |
5238 |
4U, // CLT_S_W |
| 5239 |
4U, // CLT_U_B |
5239 |
4U, // CLT_U_B |
| 5240 |
4U, // CLT_U_D |
5240 |
4U, // CLT_U_D |
| 5241 |
4U, // CLT_U_H |
5241 |
4U, // CLT_U_H |
| 5242 |
4U, // CLT_U_W |
5242 |
4U, // CLT_U_W |
| 5243 |
0U, // CLZ |
5243 |
0U, // CLZ |
| 5244 |
0U, // CLZ_MM |
5244 |
0U, // CLZ_MM |
| 5245 |
0U, // CLZ_MMR6 |
5245 |
0U, // CLZ_MMR6 |
| 5246 |
0U, // CLZ_R6 |
5246 |
0U, // CLZ_R6 |
| 5247 |
4U, // CMPGDU_EQ_QB |
5247 |
4U, // CMPGDU_EQ_QB |
| 5248 |
4U, // CMPGDU_EQ_QB_MMR2 |
5248 |
4U, // CMPGDU_EQ_QB_MMR2 |
| 5249 |
4U, // CMPGDU_LE_QB |
5249 |
4U, // CMPGDU_LE_QB |
| 5250 |
4U, // CMPGDU_LE_QB_MMR2 |
5250 |
4U, // CMPGDU_LE_QB_MMR2 |
| 5251 |
4U, // CMPGDU_LT_QB |
5251 |
4U, // CMPGDU_LT_QB |
| 5252 |
4U, // CMPGDU_LT_QB_MMR2 |
5252 |
4U, // CMPGDU_LT_QB_MMR2 |
| 5253 |
4U, // CMPGU_EQ_QB |
5253 |
4U, // CMPGU_EQ_QB |
| 5254 |
4U, // CMPGU_EQ_QB_MM |
5254 |
4U, // CMPGU_EQ_QB_MM |
| 5255 |
4U, // CMPGU_LE_QB |
5255 |
4U, // CMPGU_LE_QB |
| 5256 |
4U, // CMPGU_LE_QB_MM |
5256 |
4U, // CMPGU_LE_QB_MM |
| 5257 |
4U, // CMPGU_LT_QB |
5257 |
4U, // CMPGU_LT_QB |
| 5258 |
4U, // CMPGU_LT_QB_MM |
5258 |
4U, // CMPGU_LT_QB_MM |
| 5259 |
0U, // CMPU_EQ_QB |
5259 |
0U, // CMPU_EQ_QB |
| 5260 |
0U, // CMPU_EQ_QB_MM |
5260 |
0U, // CMPU_EQ_QB_MM |
| 5261 |
0U, // CMPU_LE_QB |
5261 |
0U, // CMPU_LE_QB |
| 5262 |
0U, // CMPU_LE_QB_MM |
5262 |
0U, // CMPU_LE_QB_MM |
| 5263 |
0U, // CMPU_LT_QB |
5263 |
0U, // CMPU_LT_QB |
| 5264 |
0U, // CMPU_LT_QB_MM |
5264 |
0U, // CMPU_LT_QB_MM |
| 5265 |
4U, // CMP_AF_D_MMR6 |
5265 |
4U, // CMP_AF_D_MMR6 |
| 5266 |
4U, // CMP_AF_S_MMR6 |
5266 |
4U, // CMP_AF_S_MMR6 |
| 5267 |
4U, // CMP_EQ_D |
5267 |
4U, // CMP_EQ_D |
| 5268 |
4U, // CMP_EQ_D_MMR6 |
5268 |
4U, // CMP_EQ_D_MMR6 |
| 5269 |
0U, // CMP_EQ_PH |
5269 |
0U, // CMP_EQ_PH |
| 5270 |
0U, // CMP_EQ_PH_MM |
5270 |
0U, // CMP_EQ_PH_MM |
| 5271 |
4U, // CMP_EQ_S |
5271 |
4U, // CMP_EQ_S |
| 5272 |
4U, // CMP_EQ_S_MMR6 |
5272 |
4U, // CMP_EQ_S_MMR6 |
| 5273 |
4U, // CMP_F_D |
5273 |
4U, // CMP_F_D |
| 5274 |
4U, // CMP_F_S |
5274 |
4U, // CMP_F_S |
| 5275 |
4U, // CMP_LE_D |
5275 |
4U, // CMP_LE_D |
| 5276 |
4U, // CMP_LE_D_MMR6 |
5276 |
4U, // CMP_LE_D_MMR6 |
| 5277 |
0U, // CMP_LE_PH |
5277 |
0U, // CMP_LE_PH |
| 5278 |
0U, // CMP_LE_PH_MM |
5278 |
0U, // CMP_LE_PH_MM |
| 5279 |
4U, // CMP_LE_S |
5279 |
4U, // CMP_LE_S |
| 5280 |
4U, // CMP_LE_S_MMR6 |
5280 |
4U, // CMP_LE_S_MMR6 |
| 5281 |
4U, // CMP_LT_D |
5281 |
4U, // CMP_LT_D |
| 5282 |
4U, // CMP_LT_D_MMR6 |
5282 |
4U, // CMP_LT_D_MMR6 |
| 5283 |
0U, // CMP_LT_PH |
5283 |
0U, // CMP_LT_PH |
| 5284 |
0U, // CMP_LT_PH_MM |
5284 |
0U, // CMP_LT_PH_MM |
| 5285 |
4U, // CMP_LT_S |
5285 |
4U, // CMP_LT_S |
| 5286 |
4U, // CMP_LT_S_MMR6 |
5286 |
4U, // CMP_LT_S_MMR6 |
| 5287 |
4U, // CMP_SAF_D |
5287 |
4U, // CMP_SAF_D |
| 5288 |
4U, // CMP_SAF_D_MMR6 |
5288 |
4U, // CMP_SAF_D_MMR6 |
| 5289 |
4U, // CMP_SAF_S |
5289 |
4U, // CMP_SAF_S |
| 5290 |
4U, // CMP_SAF_S_MMR6 |
5290 |
4U, // CMP_SAF_S_MMR6 |
| 5291 |
4U, // CMP_SEQ_D |
5291 |
4U, // CMP_SEQ_D |
| 5292 |
4U, // CMP_SEQ_D_MMR6 |
5292 |
4U, // CMP_SEQ_D_MMR6 |
| 5293 |
4U, // CMP_SEQ_S |
5293 |
4U, // CMP_SEQ_S |
| 5294 |
4U, // CMP_SEQ_S_MMR6 |
5294 |
4U, // CMP_SEQ_S_MMR6 |
| 5295 |
4U, // CMP_SLE_D |
5295 |
4U, // CMP_SLE_D |
| 5296 |
4U, // CMP_SLE_D_MMR6 |
5296 |
4U, // CMP_SLE_D_MMR6 |
| 5297 |
4U, // CMP_SLE_S |
5297 |
4U, // CMP_SLE_S |
| 5298 |
4U, // CMP_SLE_S_MMR6 |
5298 |
4U, // CMP_SLE_S_MMR6 |
| 5299 |
4U, // CMP_SLT_D |
5299 |
4U, // CMP_SLT_D |
| 5300 |
4U, // CMP_SLT_D_MMR6 |
5300 |
4U, // CMP_SLT_D_MMR6 |
| 5301 |
4U, // CMP_SLT_S |
5301 |
4U, // CMP_SLT_S |
| 5302 |
4U, // CMP_SLT_S_MMR6 |
5302 |
4U, // CMP_SLT_S_MMR6 |
| 5303 |
4U, // CMP_SUEQ_D |
5303 |
4U, // CMP_SUEQ_D |
| 5304 |
4U, // CMP_SUEQ_D_MMR6 |
5304 |
4U, // CMP_SUEQ_D_MMR6 |
| 5305 |
4U, // CMP_SUEQ_S |
5305 |
4U, // CMP_SUEQ_S |
| 5306 |
4U, // CMP_SUEQ_S_MMR6 |
5306 |
4U, // CMP_SUEQ_S_MMR6 |
| 5307 |
4U, // CMP_SULE_D |
5307 |
4U, // CMP_SULE_D |
| 5308 |
4U, // CMP_SULE_D_MMR6 |
5308 |
4U, // CMP_SULE_D_MMR6 |
| 5309 |
4U, // CMP_SULE_S |
5309 |
4U, // CMP_SULE_S |
| 5310 |
4U, // CMP_SULE_S_MMR6 |
5310 |
4U, // CMP_SULE_S_MMR6 |
| 5311 |
4U, // CMP_SULT_D |
5311 |
4U, // CMP_SULT_D |
| 5312 |
4U, // CMP_SULT_D_MMR6 |
5312 |
4U, // CMP_SULT_D_MMR6 |
| 5313 |
4U, // CMP_SULT_S |
5313 |
4U, // CMP_SULT_S |
| 5314 |
4U, // CMP_SULT_S_MMR6 |
5314 |
4U, // CMP_SULT_S_MMR6 |
| 5315 |
4U, // CMP_SUN_D |
5315 |
4U, // CMP_SUN_D |
| 5316 |
4U, // CMP_SUN_D_MMR6 |
5316 |
4U, // CMP_SUN_D_MMR6 |
| 5317 |
4U, // CMP_SUN_S |
5317 |
4U, // CMP_SUN_S |
| 5318 |
4U, // CMP_SUN_S_MMR6 |
5318 |
4U, // CMP_SUN_S_MMR6 |
| 5319 |
4U, // CMP_UEQ_D |
5319 |
4U, // CMP_UEQ_D |
| 5320 |
4U, // CMP_UEQ_D_MMR6 |
5320 |
4U, // CMP_UEQ_D_MMR6 |
| 5321 |
4U, // CMP_UEQ_S |
5321 |
4U, // CMP_UEQ_S |
| 5322 |
4U, // CMP_UEQ_S_MMR6 |
5322 |
4U, // CMP_UEQ_S_MMR6 |
| 5323 |
4U, // CMP_ULE_D |
5323 |
4U, // CMP_ULE_D |
| 5324 |
4U, // CMP_ULE_D_MMR6 |
5324 |
4U, // CMP_ULE_D_MMR6 |
| 5325 |
4U, // CMP_ULE_S |
5325 |
4U, // CMP_ULE_S |
| 5326 |
4U, // CMP_ULE_S_MMR6 |
5326 |
4U, // CMP_ULE_S_MMR6 |
| 5327 |
4U, // CMP_ULT_D |
5327 |
4U, // CMP_ULT_D |
| 5328 |
4U, // CMP_ULT_D_MMR6 |
5328 |
4U, // CMP_ULT_D_MMR6 |
| 5329 |
4U, // CMP_ULT_S |
5329 |
4U, // CMP_ULT_S |
| 5330 |
4U, // CMP_ULT_S_MMR6 |
5330 |
4U, // CMP_ULT_S_MMR6 |
| 5331 |
4U, // CMP_UN_D |
5331 |
4U, // CMP_UN_D |
| 5332 |
4U, // CMP_UN_D_MMR6 |
5332 |
4U, // CMP_UN_D_MMR6 |
| 5333 |
4U, // CMP_UN_S |
5333 |
4U, // CMP_UN_S |
| 5334 |
4U, // CMP_UN_S_MMR6 |
5334 |
4U, // CMP_UN_S_MMR6 |
| 5335 |
289U, // COPY_S_B |
5335 |
289U, // COPY_S_B |
| 5336 |
317U, // COPY_S_D |
5336 |
317U, // COPY_S_D |
| 5337 |
265U, // COPY_S_H |
5337 |
265U, // COPY_S_H |
| 5338 |
281U, // COPY_S_W |
5338 |
281U, // COPY_S_W |
| 5339 |
289U, // COPY_U_B |
5339 |
289U, // COPY_U_B |
| 5340 |
265U, // COPY_U_H |
5340 |
265U, // COPY_U_H |
| 5341 |
281U, // COPY_U_W |
5341 |
281U, // COPY_U_W |
| 5342 |
4U, // CRC32B |
5342 |
4U, // CRC32B |
| 5343 |
4U, // CRC32CB |
5343 |
4U, // CRC32CB |
| 5344 |
4U, // CRC32CD |
5344 |
4U, // CRC32CD |
| 5345 |
4U, // CRC32CH |
5345 |
4U, // CRC32CH |
| 5346 |
4U, // CRC32CW |
5346 |
4U, // CRC32CW |
| 5347 |
4U, // CRC32D |
5347 |
4U, // CRC32D |
| 5348 |
4U, // CRC32H |
5348 |
4U, // CRC32H |
| 5349 |
4U, // CRC32W |
5349 |
4U, // CRC32W |
| 5350 |
0U, // CTC1 |
5350 |
0U, // CTC1 |
| 5351 |
0U, // CTC1_MM |
5351 |
0U, // CTC1_MM |
| 5352 |
0U, // CTC2_MM |
5352 |
0U, // CTC2_MM |
| 5353 |
0U, // CTCMSA |
5353 |
0U, // CTCMSA |
| 5354 |
0U, // CVT_D32_S |
5354 |
0U, // CVT_D32_S |
| 5355 |
0U, // CVT_D32_S_MM |
5355 |
0U, // CVT_D32_S_MM |
| 5356 |
0U, // CVT_D32_W |
5356 |
0U, // CVT_D32_W |
| 5357 |
0U, // CVT_D32_W_MM |
5357 |
0U, // CVT_D32_W_MM |
| 5358 |
0U, // CVT_D64_L |
5358 |
0U, // CVT_D64_L |
| 5359 |
0U, // CVT_D64_S |
5359 |
0U, // CVT_D64_S |
| 5360 |
0U, // CVT_D64_S_MM |
5360 |
0U, // CVT_D64_S_MM |
| 5361 |
0U, // CVT_D64_W |
5361 |
0U, // CVT_D64_W |
| 5362 |
0U, // CVT_D64_W_MM |
5362 |
0U, // CVT_D64_W_MM |
| 5363 |
0U, // CVT_D_L_MMR6 |
5363 |
0U, // CVT_D_L_MMR6 |
| 5364 |
0U, // CVT_L_D64 |
5364 |
0U, // CVT_L_D64 |
| 5365 |
0U, // CVT_L_D64_MM |
5365 |
0U, // CVT_L_D64_MM |
| 5366 |
0U, // CVT_L_D_MMR6 |
5366 |
0U, // CVT_L_D_MMR6 |
| 5367 |
0U, // CVT_L_S |
5367 |
0U, // CVT_L_S |
| 5368 |
0U, // CVT_L_S_MM |
5368 |
0U, // CVT_L_S_MM |
| 5369 |
0U, // CVT_L_S_MMR6 |
5369 |
0U, // CVT_L_S_MMR6 |
| 5370 |
0U, // CVT_PS_PW64 |
5370 |
0U, // CVT_PS_PW64 |
| 5371 |
4U, // CVT_PS_S64 |
5371 |
4U, // CVT_PS_S64 |
| 5372 |
0U, // CVT_PW_PS64 |
5372 |
0U, // CVT_PW_PS64 |
| 5373 |
0U, // CVT_S_D32 |
5373 |
0U, // CVT_S_D32 |
| 5374 |
0U, // CVT_S_D32_MM |
5374 |
0U, // CVT_S_D32_MM |
| 5375 |
0U, // CVT_S_D64 |
5375 |
0U, // CVT_S_D64 |
| 5376 |
0U, // CVT_S_D64_MM |
5376 |
0U, // CVT_S_D64_MM |
| 5377 |
0U, // CVT_S_L |
5377 |
0U, // CVT_S_L |
| 5378 |
0U, // CVT_S_L_MMR6 |
5378 |
0U, // CVT_S_L_MMR6 |
| 5379 |
0U, // CVT_S_PL64 |
5379 |
0U, // CVT_S_PL64 |
| 5380 |
0U, // CVT_S_PU64 |
5380 |
0U, // CVT_S_PU64 |
| 5381 |
0U, // CVT_S_W |
5381 |
0U, // CVT_S_W |
| 5382 |
0U, // CVT_S_W_MM |
5382 |
0U, // CVT_S_W_MM |
| 5383 |
0U, // CVT_S_W_MMR6 |
5383 |
0U, // CVT_S_W_MMR6 |
| 5384 |
0U, // CVT_W_D32 |
5384 |
0U, // CVT_W_D32 |
| 5385 |
0U, // CVT_W_D32_MM |
5385 |
0U, // CVT_W_D32_MM |
| 5386 |
0U, // CVT_W_D64 |
5386 |
0U, // CVT_W_D64 |
| 5387 |
0U, // CVT_W_D64_MM |
5387 |
0U, // CVT_W_D64_MM |
| 5388 |
0U, // CVT_W_S |
5388 |
0U, // CVT_W_S |
| 5389 |
0U, // CVT_W_S_MM |
5389 |
0U, // CVT_W_S_MM |
| 5390 |
0U, // CVT_W_S_MMR6 |
5390 |
0U, // CVT_W_S_MMR6 |
| 5391 |
4U, // C_EQ_D32 |
5391 |
4U, // C_EQ_D32 |
| 5392 |
4U, // C_EQ_D32_MM |
5392 |
4U, // C_EQ_D32_MM |
| 5393 |
4U, // C_EQ_D64 |
5393 |
4U, // C_EQ_D64 |
| 5394 |
4U, // C_EQ_D64_MM |
5394 |
4U, // C_EQ_D64_MM |
| 5395 |
4U, // C_EQ_S |
5395 |
4U, // C_EQ_S |
| 5396 |
4U, // C_EQ_S_MM |
5396 |
4U, // C_EQ_S_MM |
| 5397 |
4U, // C_F_D32 |
5397 |
4U, // C_F_D32 |
| 5398 |
4U, // C_F_D32_MM |
5398 |
4U, // C_F_D32_MM |
| 5399 |
4U, // C_F_D64 |
5399 |
4U, // C_F_D64 |
| 5400 |
4U, // C_F_D64_MM |
5400 |
4U, // C_F_D64_MM |
| 5401 |
4U, // C_F_S |
5401 |
4U, // C_F_S |
| 5402 |
4U, // C_F_S_MM |
5402 |
4U, // C_F_S_MM |
| 5403 |
4U, // C_LE_D32 |
5403 |
4U, // C_LE_D32 |
| 5404 |
4U, // C_LE_D32_MM |
5404 |
4U, // C_LE_D32_MM |
| 5405 |
4U, // C_LE_D64 |
5405 |
4U, // C_LE_D64 |
| 5406 |
4U, // C_LE_D64_MM |
5406 |
4U, // C_LE_D64_MM |
| 5407 |
4U, // C_LE_S |
5407 |
4U, // C_LE_S |
| 5408 |
4U, // C_LE_S_MM |
5408 |
4U, // C_LE_S_MM |
| 5409 |
4U, // C_LT_D32 |
5409 |
4U, // C_LT_D32 |
| 5410 |
4U, // C_LT_D32_MM |
5410 |
4U, // C_LT_D32_MM |
| 5411 |
4U, // C_LT_D64 |
5411 |
4U, // C_LT_D64 |
| 5412 |
4U, // C_LT_D64_MM |
5412 |
4U, // C_LT_D64_MM |
| 5413 |
4U, // C_LT_S |
5413 |
4U, // C_LT_S |
| 5414 |
4U, // C_LT_S_MM |
5414 |
4U, // C_LT_S_MM |
| 5415 |
4U, // C_NGE_D32 |
5415 |
4U, // C_NGE_D32 |
| 5416 |
4U, // C_NGE_D32_MM |
5416 |
4U, // C_NGE_D32_MM |
| 5417 |
4U, // C_NGE_D64 |
5417 |
4U, // C_NGE_D64 |
| 5418 |
4U, // C_NGE_D64_MM |
5418 |
4U, // C_NGE_D64_MM |
| 5419 |
4U, // C_NGE_S |
5419 |
4U, // C_NGE_S |
| 5420 |
4U, // C_NGE_S_MM |
5420 |
4U, // C_NGE_S_MM |
| 5421 |
4U, // C_NGLE_D32 |
5421 |
4U, // C_NGLE_D32 |
| 5422 |
4U, // C_NGLE_D32_MM |
5422 |
4U, // C_NGLE_D32_MM |
| 5423 |
4U, // C_NGLE_D64 |
5423 |
4U, // C_NGLE_D64 |
| 5424 |
4U, // C_NGLE_D64_MM |
5424 |
4U, // C_NGLE_D64_MM |
| 5425 |
4U, // C_NGLE_S |
5425 |
4U, // C_NGLE_S |
| 5426 |
4U, // C_NGLE_S_MM |
5426 |
4U, // C_NGLE_S_MM |
| 5427 |
4U, // C_NGL_D32 |
5427 |
4U, // C_NGL_D32 |
| 5428 |
4U, // C_NGL_D32_MM |
5428 |
4U, // C_NGL_D32_MM |
| 5429 |
4U, // C_NGL_D64 |
5429 |
4U, // C_NGL_D64 |
| 5430 |
4U, // C_NGL_D64_MM |
5430 |
4U, // C_NGL_D64_MM |
| 5431 |
4U, // C_NGL_S |
5431 |
4U, // C_NGL_S |
| 5432 |
4U, // C_NGL_S_MM |
5432 |
4U, // C_NGL_S_MM |
| 5433 |
4U, // C_NGT_D32 |
5433 |
4U, // C_NGT_D32 |
| 5434 |
4U, // C_NGT_D32_MM |
5434 |
4U, // C_NGT_D32_MM |
| 5435 |
4U, // C_NGT_D64 |
5435 |
4U, // C_NGT_D64 |
| 5436 |
4U, // C_NGT_D64_MM |
5436 |
4U, // C_NGT_D64_MM |
| 5437 |
4U, // C_NGT_S |
5437 |
4U, // C_NGT_S |
| 5438 |
4U, // C_NGT_S_MM |
5438 |
4U, // C_NGT_S_MM |
| 5439 |
4U, // C_OLE_D32 |
5439 |
4U, // C_OLE_D32 |
| 5440 |
4U, // C_OLE_D32_MM |
5440 |
4U, // C_OLE_D32_MM |
| 5441 |
4U, // C_OLE_D64 |
5441 |
4U, // C_OLE_D64 |
| 5442 |
4U, // C_OLE_D64_MM |
5442 |
4U, // C_OLE_D64_MM |
| 5443 |
4U, // C_OLE_S |
5443 |
4U, // C_OLE_S |
| 5444 |
4U, // C_OLE_S_MM |
5444 |
4U, // C_OLE_S_MM |
| 5445 |
4U, // C_OLT_D32 |
5445 |
4U, // C_OLT_D32 |
| 5446 |
4U, // C_OLT_D32_MM |
5446 |
4U, // C_OLT_D32_MM |
| 5447 |
4U, // C_OLT_D64 |
5447 |
4U, // C_OLT_D64 |
| 5448 |
4U, // C_OLT_D64_MM |
5448 |
4U, // C_OLT_D64_MM |
| 5449 |
4U, // C_OLT_S |
5449 |
4U, // C_OLT_S |
| 5450 |
4U, // C_OLT_S_MM |
5450 |
4U, // C_OLT_S_MM |
| 5451 |
4U, // C_SEQ_D32 |
5451 |
4U, // C_SEQ_D32 |
| 5452 |
4U, // C_SEQ_D32_MM |
5452 |
4U, // C_SEQ_D32_MM |
| 5453 |
4U, // C_SEQ_D64 |
5453 |
4U, // C_SEQ_D64 |
| 5454 |
4U, // C_SEQ_D64_MM |
5454 |
4U, // C_SEQ_D64_MM |
| 5455 |
4U, // C_SEQ_S |
5455 |
4U, // C_SEQ_S |
| 5456 |
4U, // C_SEQ_S_MM |
5456 |
4U, // C_SEQ_S_MM |
| 5457 |
4U, // C_SF_D32 |
5457 |
4U, // C_SF_D32 |
| 5458 |
4U, // C_SF_D32_MM |
5458 |
4U, // C_SF_D32_MM |
| 5459 |
4U, // C_SF_D64 |
5459 |
4U, // C_SF_D64 |
| 5460 |
4U, // C_SF_D64_MM |
5460 |
4U, // C_SF_D64_MM |
| 5461 |
4U, // C_SF_S |
5461 |
4U, // C_SF_S |
| 5462 |
4U, // C_SF_S_MM |
5462 |
4U, // C_SF_S_MM |
| 5463 |
4U, // C_UEQ_D32 |
5463 |
4U, // C_UEQ_D32 |
| 5464 |
4U, // C_UEQ_D32_MM |
5464 |
4U, // C_UEQ_D32_MM |
| 5465 |
4U, // C_UEQ_D64 |
5465 |
4U, // C_UEQ_D64 |
| 5466 |
4U, // C_UEQ_D64_MM |
5466 |
4U, // C_UEQ_D64_MM |
| 5467 |
4U, // C_UEQ_S |
5467 |
4U, // C_UEQ_S |
| 5468 |
4U, // C_UEQ_S_MM |
5468 |
4U, // C_UEQ_S_MM |
| 5469 |
4U, // C_ULE_D32 |
5469 |
4U, // C_ULE_D32 |
| 5470 |
4U, // C_ULE_D32_MM |
5470 |
4U, // C_ULE_D32_MM |
| 5471 |
4U, // C_ULE_D64 |
5471 |
4U, // C_ULE_D64 |
| 5472 |
4U, // C_ULE_D64_MM |
5472 |
4U, // C_ULE_D64_MM |
| 5473 |
4U, // C_ULE_S |
5473 |
4U, // C_ULE_S |
| 5474 |
4U, // C_ULE_S_MM |
5474 |
4U, // C_ULE_S_MM |
| 5475 |
4U, // C_ULT_D32 |
5475 |
4U, // C_ULT_D32 |
| 5476 |
4U, // C_ULT_D32_MM |
5476 |
4U, // C_ULT_D32_MM |
| 5477 |
4U, // C_ULT_D64 |
5477 |
4U, // C_ULT_D64 |
| 5478 |
4U, // C_ULT_D64_MM |
5478 |
4U, // C_ULT_D64_MM |
| 5479 |
4U, // C_ULT_S |
5479 |
4U, // C_ULT_S |
| 5480 |
4U, // C_ULT_S_MM |
5480 |
4U, // C_ULT_S_MM |
| 5481 |
4U, // C_UN_D32 |
5481 |
4U, // C_UN_D32 |
| 5482 |
4U, // C_UN_D32_MM |
5482 |
4U, // C_UN_D32_MM |
| 5483 |
4U, // C_UN_D64 |
5483 |
4U, // C_UN_D64 |
| 5484 |
4U, // C_UN_D64_MM |
5484 |
4U, // C_UN_D64_MM |
| 5485 |
4U, // C_UN_S |
5485 |
4U, // C_UN_S |
| 5486 |
4U, // C_UN_S_MM |
5486 |
4U, // C_UN_S_MM |
| 5487 |
0U, // CmpRxRy16 |
5487 |
0U, // CmpRxRy16 |
| 5488 |
1U, // CmpiRxImm16 |
5488 |
1U, // CmpiRxImm16 |
| 5489 |
0U, // CmpiRxImmX16 |
5489 |
0U, // CmpiRxImmX16 |
| 5490 |
4U, // DADD |
5490 |
4U, // DADD |
| 5491 |
4U, // DADDi |
5491 |
4U, // DADDi |
| 5492 |
4U, // DADDiu |
5492 |
4U, // DADDiu |
| 5493 |
4U, // DADDu |
5493 |
4U, // DADDu |
| 5494 |
20U, // DAHI |
5494 |
20U, // DAHI |
| 5495 |
2180U, // DALIGN |
5495 |
2180U, // DALIGN |
| 5496 |
20U, // DATI |
5496 |
20U, // DATI |
| 5497 |
20U, // DAUI |
5497 |
20U, // DAUI |
| 5498 |
0U, // DBITSWAP |
5498 |
0U, // DBITSWAP |
| 5499 |
0U, // DCLO |
5499 |
0U, // DCLO |
| 5500 |
0U, // DCLO_R6 |
5500 |
0U, // DCLO_R6 |
| 5501 |
0U, // DCLZ |
5501 |
0U, // DCLZ |
| 5502 |
0U, // DCLZ_R6 |
5502 |
0U, // DCLZ_R6 |
| 5503 |
4U, // DDIV |
5503 |
4U, // DDIV |
| 5504 |
4U, // DDIVU |
5504 |
4U, // DDIVU |
| 5505 |
0U, // DERET |
5505 |
0U, // DERET |
| 5506 |
0U, // DERET_MM |
5506 |
0U, // DERET_MM |
| 5507 |
0U, // DERET_MMR6 |
5507 |
0U, // DERET_MMR6 |
| 5508 |
3228U, // DEXT |
5508 |
3228U, // DEXT |
| 5509 |
4252U, // DEXT64_32 |
5509 |
4252U, // DEXT64_32 |
| 5510 |
5260U, // DEXTM |
5510 |
5260U, // DEXTM |
| 5511 |
448U, // DEXTU |
5511 |
448U, // DEXTU |
| 5512 |
0U, // DI |
5512 |
0U, // DI |
| 5513 |
6300U, // DINS |
5513 |
6300U, // DINS |
| 5514 |
7308U, // DINSM |
5514 |
7308U, // DINSM |
| 5515 |
576U, // DINSU |
5515 |
576U, // DINSU |
| 5516 |
4U, // DIV |
5516 |
4U, // DIV |
| 5517 |
4U, // DIVU |
5517 |
4U, // DIVU |
| 5518 |
4U, // DIVU_MMR6 |
5518 |
4U, // DIVU_MMR6 |
| 5519 |
4U, // DIV_MMR6 |
5519 |
4U, // DIV_MMR6 |
| 5520 |
4U, // DIV_S_B |
5520 |
4U, // DIV_S_B |
| 5521 |
4U, // DIV_S_D |
5521 |
4U, // DIV_S_D |
| 5522 |
4U, // DIV_S_H |
5522 |
4U, // DIV_S_H |
| 5523 |
4U, // DIV_S_W |
5523 |
4U, // DIV_S_W |
| 5524 |
4U, // DIV_U_B |
5524 |
4U, // DIV_U_B |
| 5525 |
4U, // DIV_U_D |
5525 |
4U, // DIV_U_D |
| 5526 |
4U, // DIV_U_H |
5526 |
4U, // DIV_U_H |
| 5527 |
4U, // DIV_U_W |
5527 |
4U, // DIV_U_W |
| 5528 |
0U, // DI_MM |
5528 |
0U, // DI_MM |
| 5529 |
0U, // DI_MMR6 |
5529 |
0U, // DI_MMR6 |
| 5530 |
8324U, // DLSA |
5530 |
8324U, // DLSA |
| 5531 |
8324U, // DLSA_R6 |
5531 |
8324U, // DLSA_R6 |
| 5532 |
8U, // DMFC0 |
5532 |
8U, // DMFC0 |
| 5533 |
0U, // DMFC1 |
5533 |
0U, // DMFC1 |
| 5534 |
8U, // DMFC2 |
5534 |
8U, // DMFC2 |
| 5535 |
0U, // DMFC2_OCTEON |
5535 |
0U, // DMFC2_OCTEON |
| 5536 |
8U, // DMFGC0 |
5536 |
8U, // DMFGC0 |
| 5537 |
4U, // DMOD |
5537 |
4U, // DMOD |
| 5538 |
4U, // DMODU |
5538 |
4U, // DMODU |
| 5539 |
0U, // DMT |
5539 |
0U, // DMT |
| 5540 |
0U, // DMTC0 |
5540 |
0U, // DMTC0 |
| 5541 |
0U, // DMTC1 |
5541 |
0U, // DMTC1 |
| 5542 |
0U, // DMTC2 |
5542 |
0U, // DMTC2 |
| 5543 |
0U, // DMTC2_OCTEON |
5543 |
0U, // DMTC2_OCTEON |
| 5544 |
0U, // DMTGC0 |
5544 |
0U, // DMTGC0 |
| 5545 |
4U, // DMUH |
5545 |
4U, // DMUH |
| 5546 |
4U, // DMUHU |
5546 |
4U, // DMUHU |
| 5547 |
4U, // DMUL |
5547 |
4U, // DMUL |
| 5548 |
0U, // DMULT |
5548 |
0U, // DMULT |
| 5549 |
0U, // DMULTu |
5549 |
0U, // DMULTu |
| 5550 |
4U, // DMULU |
5550 |
4U, // DMULU |
| 5551 |
4U, // DMUL_R6 |
5551 |
4U, // DMUL_R6 |
| 5552 |
4U, // DOTP_S_D |
5552 |
4U, // DOTP_S_D |
| 5553 |
4U, // DOTP_S_H |
5553 |
4U, // DOTP_S_H |
| 5554 |
4U, // DOTP_S_W |
5554 |
4U, // DOTP_S_W |
| 5555 |
4U, // DOTP_U_D |
5555 |
4U, // DOTP_U_D |
| 5556 |
4U, // DOTP_U_H |
5556 |
4U, // DOTP_U_H |
| 5557 |
4U, // DOTP_U_W |
5557 |
4U, // DOTP_U_W |
| 5558 |
52U, // DPADD_S_D |
5558 |
52U, // DPADD_S_D |
| 5559 |
52U, // DPADD_S_H |
5559 |
52U, // DPADD_S_H |
| 5560 |
52U, // DPADD_S_W |
5560 |
52U, // DPADD_S_W |
| 5561 |
52U, // DPADD_U_D |
5561 |
52U, // DPADD_U_D |
| 5562 |
52U, // DPADD_U_H |
5562 |
52U, // DPADD_U_H |
| 5563 |
52U, // DPADD_U_W |
5563 |
52U, // DPADD_U_W |
| 5564 |
4U, // DPAQX_SA_W_PH |
5564 |
4U, // DPAQX_SA_W_PH |
| 5565 |
4U, // DPAQX_SA_W_PH_MMR2 |
5565 |
4U, // DPAQX_SA_W_PH_MMR2 |
| 5566 |
4U, // DPAQX_S_W_PH |
5566 |
4U, // DPAQX_S_W_PH |
| 5567 |
4U, // DPAQX_S_W_PH_MMR2 |
5567 |
4U, // DPAQX_S_W_PH_MMR2 |
| 5568 |
4U, // DPAQ_SA_L_W |
5568 |
4U, // DPAQ_SA_L_W |
| 5569 |
4U, // DPAQ_SA_L_W_MM |
5569 |
4U, // DPAQ_SA_L_W_MM |
| 5570 |
4U, // DPAQ_S_W_PH |
5570 |
4U, // DPAQ_S_W_PH |
| 5571 |
4U, // DPAQ_S_W_PH_MM |
5571 |
4U, // DPAQ_S_W_PH_MM |
| 5572 |
4U, // DPAU_H_QBL |
5572 |
4U, // DPAU_H_QBL |
| 5573 |
4U, // DPAU_H_QBL_MM |
5573 |
4U, // DPAU_H_QBL_MM |
| 5574 |
4U, // DPAU_H_QBR |
5574 |
4U, // DPAU_H_QBR |
| 5575 |
4U, // DPAU_H_QBR_MM |
5575 |
4U, // DPAU_H_QBR_MM |
| 5576 |
4U, // DPAX_W_PH |
5576 |
4U, // DPAX_W_PH |
| 5577 |
4U, // DPAX_W_PH_MMR2 |
5577 |
4U, // DPAX_W_PH_MMR2 |
| 5578 |
4U, // DPA_W_PH |
5578 |
4U, // DPA_W_PH |
| 5579 |
4U, // DPA_W_PH_MMR2 |
5579 |
4U, // DPA_W_PH_MMR2 |
| 5580 |
0U, // DPOP |
5580 |
0U, // DPOP |
| 5581 |
4U, // DPSQX_SA_W_PH |
5581 |
4U, // DPSQX_SA_W_PH |
| 5582 |
4U, // DPSQX_SA_W_PH_MMR2 |
5582 |
4U, // DPSQX_SA_W_PH_MMR2 |
| 5583 |
4U, // DPSQX_S_W_PH |
5583 |
4U, // DPSQX_S_W_PH |
| 5584 |
4U, // DPSQX_S_W_PH_MMR2 |
5584 |
4U, // DPSQX_S_W_PH_MMR2 |
| 5585 |
4U, // DPSQ_SA_L_W |
5585 |
4U, // DPSQ_SA_L_W |
| 5586 |
4U, // DPSQ_SA_L_W_MM |
5586 |
4U, // DPSQ_SA_L_W_MM |
| 5587 |
4U, // DPSQ_S_W_PH |
5587 |
4U, // DPSQ_S_W_PH |
| 5588 |
4U, // DPSQ_S_W_PH_MM |
5588 |
4U, // DPSQ_S_W_PH_MM |
| 5589 |
52U, // DPSUB_S_D |
5589 |
52U, // DPSUB_S_D |
| 5590 |
52U, // DPSUB_S_H |
5590 |
52U, // DPSUB_S_H |
| 5591 |
52U, // DPSUB_S_W |
5591 |
52U, // DPSUB_S_W |
| 5592 |
52U, // DPSUB_U_D |
5592 |
52U, // DPSUB_U_D |
| 5593 |
52U, // DPSUB_U_H |
5593 |
52U, // DPSUB_U_H |
| 5594 |
52U, // DPSUB_U_W |
5594 |
52U, // DPSUB_U_W |
| 5595 |
4U, // DPSU_H_QBL |
5595 |
4U, // DPSU_H_QBL |
| 5596 |
4U, // DPSU_H_QBL_MM |
5596 |
4U, // DPSU_H_QBL_MM |
| 5597 |
4U, // DPSU_H_QBR |
5597 |
4U, // DPSU_H_QBR |
| 5598 |
4U, // DPSU_H_QBR_MM |
5598 |
4U, // DPSU_H_QBR_MM |
| 5599 |
4U, // DPSX_W_PH |
5599 |
4U, // DPSX_W_PH |
| 5600 |
4U, // DPSX_W_PH_MMR2 |
5600 |
4U, // DPSX_W_PH_MMR2 |
| 5601 |
4U, // DPS_W_PH |
5601 |
4U, // DPS_W_PH |
| 5602 |
4U, // DPS_W_PH_MMR2 |
5602 |
4U, // DPS_W_PH_MMR2 |
| 5603 |
28U, // DROTR |
5603 |
28U, // DROTR |
| 5604 |
12U, // DROTR32 |
5604 |
12U, // DROTR32 |
| 5605 |
4U, // DROTRV |
5605 |
4U, // DROTRV |
| 5606 |
0U, // DSBH |
5606 |
0U, // DSBH |
| 5607 |
0U, // DSDIV |
5607 |
0U, // DSDIV |
| 5608 |
0U, // DSHD |
5608 |
0U, // DSHD |
| 5609 |
28U, // DSLL |
5609 |
28U, // DSLL |
| 5610 |
12U, // DSLL32 |
5610 |
12U, // DSLL32 |
| 5611 |
1U, // DSLL64_32 |
5611 |
1U, // DSLL64_32 |
| 5612 |
4U, // DSLLV |
5612 |
4U, // DSLLV |
| 5613 |
28U, // DSRA |
5613 |
28U, // DSRA |
| 5614 |
12U, // DSRA32 |
5614 |
12U, // DSRA32 |
| 5615 |
4U, // DSRAV |
5615 |
4U, // DSRAV |
| 5616 |
28U, // DSRL |
5616 |
28U, // DSRL |
| 5617 |
12U, // DSRL32 |
5617 |
12U, // DSRL32 |
| 5618 |
4U, // DSRLV |
5618 |
4U, // DSRLV |
| 5619 |
4U, // DSUB |
5619 |
4U, // DSUB |
| 5620 |
4U, // DSUBu |
5620 |
4U, // DSUBu |
| 5621 |
0U, // DUDIV |
5621 |
0U, // DUDIV |
| 5622 |
0U, // DVP |
5622 |
0U, // DVP |
| 5623 |
0U, // DVPE |
5623 |
0U, // DVPE |
| 5624 |
0U, // DVP_MMR6 |
5624 |
0U, // DVP_MMR6 |
| 5625 |
0U, // DivRxRy16 |
5625 |
0U, // DivRxRy16 |
| 5626 |
0U, // DivuRxRy16 |
5626 |
0U, // DivuRxRy16 |
| 5627 |
0U, // EHB |
5627 |
0U, // EHB |
| 5628 |
0U, // EHB_MM |
5628 |
0U, // EHB_MM |
| 5629 |
0U, // EHB_MMR6 |
5629 |
0U, // EHB_MMR6 |
| 5630 |
0U, // EI |
5630 |
0U, // EI |
| 5631 |
0U, // EI_MM |
5631 |
0U, // EI_MM |
| 5632 |
0U, // EI_MMR6 |
5632 |
0U, // EI_MMR6 |
| 5633 |
0U, // EMT |
5633 |
0U, // EMT |
| 5634 |
0U, // ERET |
5634 |
0U, // ERET |
| 5635 |
0U, // ERETNC |
5635 |
0U, // ERETNC |
| 5636 |
0U, // ERETNC_MMR6 |
5636 |
0U, // ERETNC_MMR6 |
| 5637 |
0U, // ERET_MM |
5637 |
0U, // ERET_MM |
| 5638 |
0U, // ERET_MMR6 |
5638 |
0U, // ERET_MMR6 |
| 5639 |
0U, // EVP |
5639 |
0U, // EVP |
| 5640 |
0U, // EVPE |
5640 |
0U, // EVPE |
| 5641 |
0U, // EVP_MMR6 |
5641 |
0U, // EVP_MMR6 |
| 5642 |
4236U, // EXT |
5642 |
4236U, // EXT |
| 5643 |
12U, // EXTP |
5643 |
12U, // EXTP |
| 5644 |
12U, // EXTPDP |
5644 |
12U, // EXTPDP |
| 5645 |
4U, // EXTPDPV |
5645 |
4U, // EXTPDPV |
| 5646 |
4U, // EXTPDPV_MM |
5646 |
4U, // EXTPDPV_MM |
| 5647 |
12U, // EXTPDP_MM |
5647 |
12U, // EXTPDP_MM |
| 5648 |
4U, // EXTPV |
5648 |
4U, // EXTPV |
| 5649 |
4U, // EXTPV_MM |
5649 |
4U, // EXTPV_MM |
| 5650 |
12U, // EXTP_MM |
5650 |
12U, // EXTP_MM |
| 5651 |
4U, // EXTRV_RS_W |
5651 |
4U, // EXTRV_RS_W |
| 5652 |
4U, // EXTRV_RS_W_MM |
5652 |
4U, // EXTRV_RS_W_MM |
| 5653 |
4U, // EXTRV_R_W |
5653 |
4U, // EXTRV_R_W |
| 5654 |
4U, // EXTRV_R_W_MM |
5654 |
4U, // EXTRV_R_W_MM |
| 5655 |
4U, // EXTRV_S_H |
5655 |
4U, // EXTRV_S_H |
| 5656 |
4U, // EXTRV_S_H_MM |
5656 |
4U, // EXTRV_S_H_MM |
| 5657 |
4U, // EXTRV_W |
5657 |
4U, // EXTRV_W |
| 5658 |
4U, // EXTRV_W_MM |
5658 |
4U, // EXTRV_W_MM |
| 5659 |
12U, // EXTR_RS_W |
5659 |
12U, // EXTR_RS_W |
| 5660 |
12U, // EXTR_RS_W_MM |
5660 |
12U, // EXTR_RS_W_MM |
| 5661 |
12U, // EXTR_R_W |
5661 |
12U, // EXTR_R_W |
| 5662 |
12U, // EXTR_R_W_MM |
5662 |
12U, // EXTR_R_W_MM |
| 5663 |
12U, // EXTR_S_H |
5663 |
12U, // EXTR_S_H |
| 5664 |
12U, // EXTR_S_H_MM |
5664 |
12U, // EXTR_S_H_MM |
| 5665 |
12U, // EXTR_W |
5665 |
12U, // EXTR_W |
| 5666 |
12U, // EXTR_W_MM |
5666 |
12U, // EXTR_W_MM |
| 5667 |
1164U, // EXTS |
5667 |
1164U, // EXTS |
| 5668 |
1164U, // EXTS32 |
5668 |
1164U, // EXTS32 |
| 5669 |
4236U, // EXT_MM |
5669 |
4236U, // EXT_MM |
| 5670 |
4236U, // EXT_MMR6 |
5670 |
4236U, // EXT_MMR6 |
| 5671 |
0U, // FABS_D32 |
5671 |
0U, // FABS_D32 |
| 5672 |
0U, // FABS_D32_MM |
5672 |
0U, // FABS_D32_MM |
| 5673 |
0U, // FABS_D64 |
5673 |
0U, // FABS_D64 |
| 5674 |
0U, // FABS_D64_MM |
5674 |
0U, // FABS_D64_MM |
| 5675 |
0U, // FABS_S |
5675 |
0U, // FABS_S |
| 5676 |
0U, // FABS_S_MM |
5676 |
0U, // FABS_S_MM |
| 5677 |
4U, // FADD_D |
5677 |
4U, // FADD_D |
| 5678 |
4U, // FADD_D32 |
5678 |
4U, // FADD_D32 |
| 5679 |
4U, // FADD_D32_MM |
5679 |
4U, // FADD_D32_MM |
| 5680 |
4U, // FADD_D64 |
5680 |
4U, // FADD_D64 |
| 5681 |
4U, // FADD_D64_MM |
5681 |
4U, // FADD_D64_MM |
| 5682 |
4U, // FADD_PS64 |
5682 |
4U, // FADD_PS64 |
| 5683 |
4U, // FADD_S |
5683 |
4U, // FADD_S |
| 5684 |
4U, // FADD_S_MM |
5684 |
4U, // FADD_S_MM |
| 5685 |
68U, // FADD_S_MMR6 |
5685 |
68U, // FADD_S_MMR6 |
| 5686 |
4U, // FADD_W |
5686 |
4U, // FADD_W |
| 5687 |
4U, // FCAF_D |
5687 |
4U, // FCAF_D |
| 5688 |
4U, // FCAF_W |
5688 |
4U, // FCAF_W |
| 5689 |
4U, // FCEQ_D |
5689 |
4U, // FCEQ_D |
| 5690 |
4U, // FCEQ_W |
5690 |
4U, // FCEQ_W |
| 5691 |
0U, // FCLASS_D |
5691 |
0U, // FCLASS_D |
| 5692 |
0U, // FCLASS_W |
5692 |
0U, // FCLASS_W |
| 5693 |
4U, // FCLE_D |
5693 |
4U, // FCLE_D |
| 5694 |
4U, // FCLE_W |
5694 |
4U, // FCLE_W |
| 5695 |
4U, // FCLT_D |
5695 |
4U, // FCLT_D |
| 5696 |
4U, // FCLT_W |
5696 |
4U, // FCLT_W |
| 5697 |
0U, // FCMP_D32 |
5697 |
0U, // FCMP_D32 |
| 5698 |
0U, // FCMP_D32_MM |
5698 |
0U, // FCMP_D32_MM |
| 5699 |
0U, // FCMP_D64 |
5699 |
0U, // FCMP_D64 |
| 5700 |
0U, // FCMP_S32 |
5700 |
0U, // FCMP_S32 |
| 5701 |
0U, // FCMP_S32_MM |
5701 |
0U, // FCMP_S32_MM |
| 5702 |
4U, // FCNE_D |
5702 |
4U, // FCNE_D |
| 5703 |
4U, // FCNE_W |
5703 |
4U, // FCNE_W |
| 5704 |
4U, // FCOR_D |
5704 |
4U, // FCOR_D |
| 5705 |
4U, // FCOR_W |
5705 |
4U, // FCOR_W |
| 5706 |
4U, // FCUEQ_D |
5706 |
4U, // FCUEQ_D |
| 5707 |
4U, // FCUEQ_W |
5707 |
4U, // FCUEQ_W |
| 5708 |
4U, // FCULE_D |
5708 |
4U, // FCULE_D |
| 5709 |
4U, // FCULE_W |
5709 |
4U, // FCULE_W |
| 5710 |
4U, // FCULT_D |
5710 |
4U, // FCULT_D |
| 5711 |
4U, // FCULT_W |
5711 |
4U, // FCULT_W |
| 5712 |
4U, // FCUNE_D |
5712 |
4U, // FCUNE_D |
| 5713 |
4U, // FCUNE_W |
5713 |
4U, // FCUNE_W |
| 5714 |
4U, // FCUN_D |
5714 |
4U, // FCUN_D |
| 5715 |
4U, // FCUN_W |
5715 |
4U, // FCUN_W |
| 5716 |
4U, // FDIV_D |
5716 |
4U, // FDIV_D |
| 5717 |
4U, // FDIV_D32 |
5717 |
4U, // FDIV_D32 |
| 5718 |
4U, // FDIV_D32_MM |
5718 |
4U, // FDIV_D32_MM |
| 5719 |
4U, // FDIV_D64 |
5719 |
4U, // FDIV_D64 |
| 5720 |
4U, // FDIV_D64_MM |
5720 |
4U, // FDIV_D64_MM |
| 5721 |
4U, // FDIV_S |
5721 |
4U, // FDIV_S |
| 5722 |
4U, // FDIV_S_MM |
5722 |
4U, // FDIV_S_MM |
| 5723 |
68U, // FDIV_S_MMR6 |
5723 |
68U, // FDIV_S_MMR6 |
| 5724 |
4U, // FDIV_W |
5724 |
4U, // FDIV_W |
| 5725 |
4U, // FEXDO_H |
5725 |
4U, // FEXDO_H |
| 5726 |
4U, // FEXDO_W |
5726 |
4U, // FEXDO_W |
| 5727 |
4U, // FEXP2_D |
5727 |
4U, // FEXP2_D |
| 5728 |
4U, // FEXP2_W |
5728 |
4U, // FEXP2_W |
| 5729 |
0U, // FEXUPL_D |
5729 |
0U, // FEXUPL_D |
| 5730 |
0U, // FEXUPL_W |
5730 |
0U, // FEXUPL_W |
| 5731 |
0U, // FEXUPR_D |
5731 |
0U, // FEXUPR_D |
| 5732 |
0U, // FEXUPR_W |
5732 |
0U, // FEXUPR_W |
| 5733 |
0U, // FFINT_S_D |
5733 |
0U, // FFINT_S_D |
| 5734 |
0U, // FFINT_S_W |
5734 |
0U, // FFINT_S_W |
| 5735 |
0U, // FFINT_U_D |
5735 |
0U, // FFINT_U_D |
| 5736 |
0U, // FFINT_U_W |
5736 |
0U, // FFINT_U_W |
| 5737 |
0U, // FFQL_D |
5737 |
0U, // FFQL_D |
| 5738 |
0U, // FFQL_W |
5738 |
0U, // FFQL_W |
| 5739 |
0U, // FFQR_D |
5739 |
0U, // FFQR_D |
| 5740 |
0U, // FFQR_W |
5740 |
0U, // FFQR_W |
| 5741 |
0U, // FILL_B |
5741 |
0U, // FILL_B |
| 5742 |
0U, // FILL_D |
5742 |
0U, // FILL_D |
| 5743 |
0U, // FILL_H |
5743 |
0U, // FILL_H |
| 5744 |
0U, // FILL_W |
5744 |
0U, // FILL_W |
| 5745 |
0U, // FLOG2_D |
5745 |
0U, // FLOG2_D |
| 5746 |
0U, // FLOG2_W |
5746 |
0U, // FLOG2_W |
| 5747 |
0U, // FLOOR_L_D64 |
5747 |
0U, // FLOOR_L_D64 |
| 5748 |
0U, // FLOOR_L_D_MMR6 |
5748 |
0U, // FLOOR_L_D_MMR6 |
| 5749 |
0U, // FLOOR_L_S |
5749 |
0U, // FLOOR_L_S |
| 5750 |
0U, // FLOOR_L_S_MMR6 |
5750 |
0U, // FLOOR_L_S_MMR6 |
| 5751 |
0U, // FLOOR_W_D32 |
5751 |
0U, // FLOOR_W_D32 |
| 5752 |
0U, // FLOOR_W_D64 |
5752 |
0U, // FLOOR_W_D64 |
| 5753 |
0U, // FLOOR_W_D_MMR6 |
5753 |
0U, // FLOOR_W_D_MMR6 |
| 5754 |
0U, // FLOOR_W_MM |
5754 |
0U, // FLOOR_W_MM |
| 5755 |
0U, // FLOOR_W_S |
5755 |
0U, // FLOOR_W_S |
| 5756 |
0U, // FLOOR_W_S_MM |
5756 |
0U, // FLOOR_W_S_MM |
| 5757 |
0U, // FLOOR_W_S_MMR6 |
5757 |
0U, // FLOOR_W_S_MMR6 |
| 5758 |
52U, // FMADD_D |
5758 |
52U, // FMADD_D |
| 5759 |
52U, // FMADD_W |
5759 |
52U, // FMADD_W |
| 5760 |
4U, // FMAX_A_D |
5760 |
4U, // FMAX_A_D |
| 5761 |
4U, // FMAX_A_W |
5761 |
4U, // FMAX_A_W |
| 5762 |
4U, // FMAX_D |
5762 |
4U, // FMAX_D |
| 5763 |
4U, // FMAX_W |
5763 |
4U, // FMAX_W |
| 5764 |
4U, // FMIN_A_D |
5764 |
4U, // FMIN_A_D |
| 5765 |
4U, // FMIN_A_W |
5765 |
4U, // FMIN_A_W |
| 5766 |
4U, // FMIN_D |
5766 |
4U, // FMIN_D |
| 5767 |
4U, // FMIN_W |
5767 |
4U, // FMIN_W |
| 5768 |
0U, // FMOV_D32 |
5768 |
0U, // FMOV_D32 |
| 5769 |
0U, // FMOV_D32_MM |
5769 |
0U, // FMOV_D32_MM |
| 5770 |
0U, // FMOV_D64 |
5770 |
0U, // FMOV_D64 |
| 5771 |
0U, // FMOV_D64_MM |
5771 |
0U, // FMOV_D64_MM |
| 5772 |
0U, // FMOV_D_MMR6 |
5772 |
0U, // FMOV_D_MMR6 |
| 5773 |
0U, // FMOV_S |
5773 |
0U, // FMOV_S |
| 5774 |
0U, // FMOV_S_MM |
5774 |
0U, // FMOV_S_MM |
| 5775 |
0U, // FMOV_S_MMR6 |
5775 |
0U, // FMOV_S_MMR6 |
| 5776 |
52U, // FMSUB_D |
5776 |
52U, // FMSUB_D |
| 5777 |
52U, // FMSUB_W |
5777 |
52U, // FMSUB_W |
| 5778 |
4U, // FMUL_D |
5778 |
4U, // FMUL_D |
| 5779 |
4U, // FMUL_D32 |
5779 |
4U, // FMUL_D32 |
| 5780 |
4U, // FMUL_D32_MM |
5780 |
4U, // FMUL_D32_MM |
| 5781 |
4U, // FMUL_D64 |
5781 |
4U, // FMUL_D64 |
| 5782 |
4U, // FMUL_D64_MM |
5782 |
4U, // FMUL_D64_MM |
| 5783 |
4U, // FMUL_PS64 |
5783 |
4U, // FMUL_PS64 |
| 5784 |
4U, // FMUL_S |
5784 |
4U, // FMUL_S |
| 5785 |
4U, // FMUL_S_MM |
5785 |
4U, // FMUL_S_MM |
| 5786 |
68U, // FMUL_S_MMR6 |
5786 |
68U, // FMUL_S_MMR6 |
| 5787 |
4U, // FMUL_W |
5787 |
4U, // FMUL_W |
| 5788 |
0U, // FNEG_D32 |
5788 |
0U, // FNEG_D32 |
| 5789 |
0U, // FNEG_D32_MM |
5789 |
0U, // FNEG_D32_MM |
| 5790 |
0U, // FNEG_D64 |
5790 |
0U, // FNEG_D64 |
| 5791 |
0U, // FNEG_D64_MM |
5791 |
0U, // FNEG_D64_MM |
| 5792 |
0U, // FNEG_S |
5792 |
0U, // FNEG_S |
| 5793 |
0U, // FNEG_S_MM |
5793 |
0U, // FNEG_S_MM |
| 5794 |
0U, // FNEG_S_MMR6 |
5794 |
0U, // FNEG_S_MMR6 |
| 5795 |
1U, // FORK |
5795 |
1U, // FORK |
| 5796 |
0U, // FRCP_D |
5796 |
0U, // FRCP_D |
| 5797 |
0U, // FRCP_W |
5797 |
0U, // FRCP_W |
| 5798 |
0U, // FRINT_D |
5798 |
0U, // FRINT_D |
| 5799 |
0U, // FRINT_W |
5799 |
0U, // FRINT_W |
| 5800 |
0U, // FRSQRT_D |
5800 |
0U, // FRSQRT_D |
| 5801 |
0U, // FRSQRT_W |
5801 |
0U, // FRSQRT_W |
| 5802 |
4U, // FSAF_D |
5802 |
4U, // FSAF_D |
| 5803 |
4U, // FSAF_W |
5803 |
4U, // FSAF_W |
| 5804 |
4U, // FSEQ_D |
5804 |
4U, // FSEQ_D |
| 5805 |
4U, // FSEQ_W |
5805 |
4U, // FSEQ_W |
| 5806 |
4U, // FSLE_D |
5806 |
4U, // FSLE_D |
| 5807 |
4U, // FSLE_W |
5807 |
4U, // FSLE_W |
| 5808 |
4U, // FSLT_D |
5808 |
4U, // FSLT_D |
| 5809 |
4U, // FSLT_W |
5809 |
4U, // FSLT_W |
| 5810 |
4U, // FSNE_D |
5810 |
4U, // FSNE_D |
| 5811 |
4U, // FSNE_W |
5811 |
4U, // FSNE_W |
| 5812 |
4U, // FSOR_D |
5812 |
4U, // FSOR_D |
| 5813 |
4U, // FSOR_W |
5813 |
4U, // FSOR_W |
| 5814 |
0U, // FSQRT_D |
5814 |
0U, // FSQRT_D |
| 5815 |
0U, // FSQRT_D32 |
5815 |
0U, // FSQRT_D32 |
| 5816 |
0U, // FSQRT_D32_MM |
5816 |
0U, // FSQRT_D32_MM |
| 5817 |
0U, // FSQRT_D64 |
5817 |
0U, // FSQRT_D64 |
| 5818 |
0U, // FSQRT_D64_MM |
5818 |
0U, // FSQRT_D64_MM |
| 5819 |
0U, // FSQRT_S |
5819 |
0U, // FSQRT_S |
| 5820 |
0U, // FSQRT_S_MM |
5820 |
0U, // FSQRT_S_MM |
| 5821 |
0U, // FSQRT_W |
5821 |
0U, // FSQRT_W |
| 5822 |
4U, // FSUB_D |
5822 |
4U, // FSUB_D |
| 5823 |
4U, // FSUB_D32 |
5823 |
4U, // FSUB_D32 |
| 5824 |
4U, // FSUB_D32_MM |
5824 |
4U, // FSUB_D32_MM |
| 5825 |
4U, // FSUB_D64 |
5825 |
4U, // FSUB_D64 |
| 5826 |
4U, // FSUB_D64_MM |
5826 |
4U, // FSUB_D64_MM |
| 5827 |
4U, // FSUB_PS64 |
5827 |
4U, // FSUB_PS64 |
| 5828 |
4U, // FSUB_S |
5828 |
4U, // FSUB_S |
| 5829 |
4U, // FSUB_S_MM |
5829 |
4U, // FSUB_S_MM |
| 5830 |
68U, // FSUB_S_MMR6 |
5830 |
68U, // FSUB_S_MMR6 |
| 5831 |
4U, // FSUB_W |
5831 |
4U, // FSUB_W |
| 5832 |
4U, // FSUEQ_D |
5832 |
4U, // FSUEQ_D |
| 5833 |
4U, // FSUEQ_W |
5833 |
4U, // FSUEQ_W |
| 5834 |
4U, // FSULE_D |
5834 |
4U, // FSULE_D |
| 5835 |
4U, // FSULE_W |
5835 |
4U, // FSULE_W |
| 5836 |
4U, // FSULT_D |
5836 |
4U, // FSULT_D |
| 5837 |
4U, // FSULT_W |
5837 |
4U, // FSULT_W |
| 5838 |
4U, // FSUNE_D |
5838 |
4U, // FSUNE_D |
| 5839 |
4U, // FSUNE_W |
5839 |
4U, // FSUNE_W |
| 5840 |
4U, // FSUN_D |
5840 |
4U, // FSUN_D |
| 5841 |
4U, // FSUN_W |
5841 |
4U, // FSUN_W |
| 5842 |
0U, // FTINT_S_D |
5842 |
0U, // FTINT_S_D |
| 5843 |
0U, // FTINT_S_W |
5843 |
0U, // FTINT_S_W |
| 5844 |
0U, // FTINT_U_D |
5844 |
0U, // FTINT_U_D |
| 5845 |
0U, // FTINT_U_W |
5845 |
0U, // FTINT_U_W |
| 5846 |
4U, // FTQ_H |
5846 |
4U, // FTQ_H |
| 5847 |
4U, // FTQ_W |
5847 |
4U, // FTQ_W |
| 5848 |
0U, // FTRUNC_S_D |
5848 |
0U, // FTRUNC_S_D |
| 5849 |
0U, // FTRUNC_S_W |
5849 |
0U, // FTRUNC_S_W |
| 5850 |
0U, // FTRUNC_U_D |
5850 |
0U, // FTRUNC_U_D |
| 5851 |
0U, // FTRUNC_U_W |
5851 |
0U, // FTRUNC_U_W |
| 5852 |
0U, // GINVI |
5852 |
0U, // GINVI |
| 5853 |
0U, // GINVI_MMR6 |
5853 |
0U, // GINVI_MMR6 |
| 5854 |
0U, // GINVT |
5854 |
0U, // GINVT |
| 5855 |
0U, // GINVT_MMR6 |
5855 |
0U, // GINVT_MMR6 |
| 5856 |
4U, // HADD_S_D |
5856 |
4U, // HADD_S_D |
| 5857 |
4U, // HADD_S_H |
5857 |
4U, // HADD_S_H |
| 5858 |
4U, // HADD_S_W |
5858 |
4U, // HADD_S_W |
| 5859 |
4U, // HADD_U_D |
5859 |
4U, // HADD_U_D |
| 5860 |
4U, // HADD_U_H |
5860 |
4U, // HADD_U_H |
| 5861 |
4U, // HADD_U_W |
5861 |
4U, // HADD_U_W |
| 5862 |
4U, // HSUB_S_D |
5862 |
4U, // HSUB_S_D |
| 5863 |
4U, // HSUB_S_H |
5863 |
4U, // HSUB_S_H |
| 5864 |
4U, // HSUB_S_W |
5864 |
4U, // HSUB_S_W |
| 5865 |
4U, // HSUB_U_D |
5865 |
4U, // HSUB_U_D |
| 5866 |
4U, // HSUB_U_H |
5866 |
4U, // HSUB_U_H |
| 5867 |
4U, // HSUB_U_W |
5867 |
4U, // HSUB_U_W |
| 5868 |
0U, // HYPCALL |
5868 |
0U, // HYPCALL |
| 5869 |
0U, // HYPCALL_MM |
5869 |
0U, // HYPCALL_MM |
| 5870 |
4U, // ILVEV_B |
5870 |
4U, // ILVEV_B |
| 5871 |
4U, // ILVEV_D |
5871 |
4U, // ILVEV_D |
| 5872 |
4U, // ILVEV_H |
5872 |
4U, // ILVEV_H |
| 5873 |
4U, // ILVEV_W |
5873 |
4U, // ILVEV_W |
| 5874 |
4U, // ILVL_B |
5874 |
4U, // ILVL_B |
| 5875 |
4U, // ILVL_D |
5875 |
4U, // ILVL_D |
| 5876 |
4U, // ILVL_H |
5876 |
4U, // ILVL_H |
| 5877 |
4U, // ILVL_W |
5877 |
4U, // ILVL_W |
| 5878 |
4U, // ILVOD_B |
5878 |
4U, // ILVOD_B |
| 5879 |
4U, // ILVOD_D |
5879 |
4U, // ILVOD_D |
| 5880 |
4U, // ILVOD_H |
5880 |
4U, // ILVOD_H |
| 5881 |
4U, // ILVOD_W |
5881 |
4U, // ILVOD_W |
| 5882 |
4U, // ILVR_B |
5882 |
4U, // ILVR_B |
| 5883 |
4U, // ILVR_D |
5883 |
4U, // ILVR_D |
| 5884 |
4U, // ILVR_H |
5884 |
4U, // ILVR_H |
| 5885 |
4U, // ILVR_W |
5885 |
4U, // ILVR_W |
| 5886 |
6284U, // INS |
5886 |
6284U, // INS |
| 5887 |
0U, // INSERT_B |
5887 |
0U, // INSERT_B |
| 5888 |
0U, // INSERT_D |
5888 |
0U, // INSERT_D |
| 5889 |
0U, // INSERT_H |
5889 |
0U, // INSERT_H |
| 5890 |
0U, // INSERT_W |
5890 |
0U, // INSERT_W |
| 5891 |
0U, // INSV |
5891 |
0U, // INSV |
| 5892 |
0U, // INSVE_B |
5892 |
0U, // INSVE_B |
| 5893 |
0U, // INSVE_D |
5893 |
0U, // INSVE_D |
| 5894 |
0U, // INSVE_H |
5894 |
0U, // INSVE_H |
| 5895 |
0U, // INSVE_W |
5895 |
0U, // INSVE_W |
| 5896 |
0U, // INSV_MM |
5896 |
0U, // INSV_MM |
| 5897 |
6284U, // INS_MM |
5897 |
6284U, // INS_MM |
| 5898 |
6284U, // INS_MMR6 |
5898 |
6284U, // INS_MMR6 |
| 5899 |
0U, // J |
5899 |
0U, // J |
| 5900 |
0U, // JAL |
5900 |
0U, // JAL |
| 5901 |
0U, // JALR |
5901 |
0U, // JALR |
| 5902 |
0U, // JALR16_MM |
5902 |
0U, // JALR16_MM |
| 5903 |
0U, // JALR64 |
5903 |
0U, // JALR64 |
| 5904 |
0U, // JALRC16_MMR6 |
5904 |
0U, // JALRC16_MMR6 |
| 5905 |
0U, // JALRC_HB_MMR6 |
5905 |
0U, // JALRC_HB_MMR6 |
| 5906 |
0U, // JALRC_MMR6 |
5906 |
0U, // JALRC_MMR6 |
| 5907 |
0U, // JALRS16_MM |
5907 |
0U, // JALRS16_MM |
| 5908 |
0U, // JALRS_MM |
5908 |
0U, // JALRS_MM |
| 5909 |
0U, // JALR_HB |
5909 |
0U, // JALR_HB |
| 5910 |
0U, // JALR_HB64 |
5910 |
0U, // JALR_HB64 |
| 5911 |
0U, // JALR_MM |
5911 |
0U, // JALR_MM |
| 5912 |
0U, // JALS_MM |
5912 |
0U, // JALS_MM |
| 5913 |
0U, // JALX |
5913 |
0U, // JALX |
| 5914 |
0U, // JALX_MM |
5914 |
0U, // JALX_MM |
| 5915 |
0U, // JAL_MM |
5915 |
0U, // JAL_MM |
| 5916 |
0U, // JIALC |
5916 |
0U, // JIALC |
| 5917 |
0U, // JIALC64 |
5917 |
0U, // JIALC64 |
| 5918 |
0U, // JIALC_MMR6 |
5918 |
0U, // JIALC_MMR6 |
| 5919 |
0U, // JIC |
5919 |
0U, // JIC |
| 5920 |
0U, // JIC64 |
5920 |
0U, // JIC64 |
| 5921 |
0U, // JIC_MMR6 |
5921 |
0U, // JIC_MMR6 |
| 5922 |
0U, // JR |
5922 |
0U, // JR |
| 5923 |
0U, // JR16_MM |
5923 |
0U, // JR16_MM |
| 5924 |
0U, // JR64 |
5924 |
0U, // JR64 |
| 5925 |
0U, // JRADDIUSP |
5925 |
0U, // JRADDIUSP |
| 5926 |
0U, // JRC16_MM |
5926 |
0U, // JRC16_MM |
| 5927 |
0U, // JRC16_MMR6 |
5927 |
0U, // JRC16_MMR6 |
| 5928 |
0U, // JRCADDIUSP_MMR6 |
5928 |
0U, // JRCADDIUSP_MMR6 |
| 5929 |
0U, // JR_HB |
5929 |
0U, // JR_HB |
| 5930 |
0U, // JR_HB64 |
5930 |
0U, // JR_HB64 |
| 5931 |
0U, // JR_HB64_R6 |
5931 |
0U, // JR_HB64_R6 |
| 5932 |
0U, // JR_HB_R6 |
5932 |
0U, // JR_HB_R6 |
| 5933 |
0U, // JR_MM |
5933 |
0U, // JR_MM |
| 5934 |
0U, // J_MM |
5934 |
0U, // J_MM |
| 5935 |
0U, // Jal16 |
5935 |
0U, // Jal16 |
| 5936 |
0U, // JalB16 |
5936 |
0U, // JalB16 |
| 5937 |
0U, // JrRa16 |
5937 |
0U, // JrRa16 |
| 5938 |
0U, // JrcRa16 |
5938 |
0U, // JrcRa16 |
| 5939 |
0U, // JrcRx16 |
5939 |
0U, // JrcRx16 |
| 5940 |
0U, // JumpLinkReg16 |
5940 |
0U, // JumpLinkReg16 |
| 5941 |
0U, // LB |
5941 |
0U, // LB |
| 5942 |
0U, // LB64 |
5942 |
0U, // LB64 |
| 5943 |
0U, // LBE |
5943 |
0U, // LBE |
| 5944 |
0U, // LBE_MM |
5944 |
0U, // LBE_MM |
| 5945 |
0U, // LBU16_MM |
5945 |
0U, // LBU16_MM |
| 5946 |
1U, // LBUX |
5946 |
1U, // LBUX |
| 5947 |
1U, // LBUX_MM |
5947 |
1U, // LBUX_MM |
| 5948 |
0U, // LBU_MMR6 |
5948 |
0U, // LBU_MMR6 |
| 5949 |
0U, // LB_MM |
5949 |
0U, // LB_MM |
| 5950 |
0U, // LB_MMR6 |
5950 |
0U, // LB_MMR6 |
| 5951 |
0U, // LBu |
5951 |
0U, // LBu |
| 5952 |
0U, // LBu64 |
5952 |
0U, // LBu64 |
| 5953 |
0U, // LBuE |
5953 |
0U, // LBuE |
| 5954 |
0U, // LBuE_MM |
5954 |
0U, // LBuE_MM |
| 5955 |
0U, // LBu_MM |
5955 |
0U, // LBu_MM |
| 5956 |
0U, // LD |
5956 |
0U, // LD |
| 5957 |
0U, // LDC1 |
5957 |
0U, // LDC1 |
| 5958 |
0U, // LDC164 |
5958 |
0U, // LDC164 |
| 5959 |
0U, // LDC1_D64_MMR6 |
5959 |
0U, // LDC1_D64_MMR6 |
| 5960 |
0U, // LDC1_MM_D32 |
5960 |
0U, // LDC1_MM_D32 |
| 5961 |
0U, // LDC1_MM_D64 |
5961 |
0U, // LDC1_MM_D64 |
| 5962 |
0U, // LDC2 |
5962 |
0U, // LDC2 |
| 5963 |
0U, // LDC2_MMR6 |
5963 |
0U, // LDC2_MMR6 |
| 5964 |
0U, // LDC2_R6 |
5964 |
0U, // LDC2_R6 |
| 5965 |
0U, // LDC3 |
5965 |
0U, // LDC3 |
| 5966 |
0U, // LDI_B |
5966 |
0U, // LDI_B |
| 5967 |
0U, // LDI_D |
5967 |
0U, // LDI_D |
| 5968 |
0U, // LDI_H |
5968 |
0U, // LDI_H |
| 5969 |
0U, // LDI_W |
5969 |
0U, // LDI_W |
| 5970 |
0U, // LDL |
5970 |
0U, // LDL |
| 5971 |
0U, // LDPC |
5971 |
0U, // LDPC |
| 5972 |
0U, // LDR |
5972 |
0U, // LDR |
| 5973 |
1U, // LDXC1 |
5973 |
1U, // LDXC1 |
| 5974 |
1U, // LDXC164 |
5974 |
1U, // LDXC164 |
| 5975 |
0U, // LD_B |
5975 |
0U, // LD_B |
| 5976 |
0U, // LD_D |
5976 |
0U, // LD_D |
| 5977 |
0U, // LD_H |
5977 |
0U, // LD_H |
| 5978 |
0U, // LD_W |
5978 |
0U, // LD_W |
| 5979 |
0U, // LEA_ADDiu |
5979 |
0U, // LEA_ADDiu |
| 5980 |
0U, // LEA_ADDiu64 |
5980 |
0U, // LEA_ADDiu64 |
| 5981 |
0U, // LEA_ADDiu_MM |
5981 |
0U, // LEA_ADDiu_MM |
| 5982 |
0U, // LH |
5982 |
0U, // LH |
| 5983 |
0U, // LH64 |
5983 |
0U, // LH64 |
| 5984 |
0U, // LHE |
5984 |
0U, // LHE |
| 5985 |
0U, // LHE_MM |
5985 |
0U, // LHE_MM |
| 5986 |
0U, // LHU16_MM |
5986 |
0U, // LHU16_MM |
| 5987 |
1U, // LHX |
5987 |
1U, // LHX |
| 5988 |
1U, // LHX_MM |
5988 |
1U, // LHX_MM |
| 5989 |
0U, // LH_MM |
5989 |
0U, // LH_MM |
| 5990 |
0U, // LHu |
5990 |
0U, // LHu |
| 5991 |
0U, // LHu64 |
5991 |
0U, // LHu64 |
| 5992 |
0U, // LHuE |
5992 |
0U, // LHuE |
| 5993 |
0U, // LHuE_MM |
5993 |
0U, // LHuE_MM |
| 5994 |
0U, // LHu_MM |
5994 |
0U, // LHu_MM |
| 5995 |
0U, // LI16_MM |
5995 |
0U, // LI16_MM |
| 5996 |
0U, // LI16_MMR6 |
5996 |
0U, // LI16_MMR6 |
| 5997 |
0U, // LL |
5997 |
0U, // LL |
| 5998 |
0U, // LL64 |
5998 |
0U, // LL64 |
| 5999 |
0U, // LL64_R6 |
5999 |
0U, // LL64_R6 |
| 6000 |
0U, // LLD |
6000 |
0U, // LLD |
| 6001 |
0U, // LLD_R6 |
6001 |
0U, // LLD_R6 |
| 6002 |
0U, // LLE |
6002 |
0U, // LLE |
| 6003 |
0U, // LLE_MM |
6003 |
0U, // LLE_MM |
| 6004 |
0U, // LL_MM |
6004 |
0U, // LL_MM |
| 6005 |
0U, // LL_MMR6 |
6005 |
0U, // LL_MMR6 |
| 6006 |
0U, // LL_R6 |
6006 |
0U, // LL_R6 |
| 6007 |
8324U, // LSA |
6007 |
8324U, // LSA |
| 6008 |
1U, // LSA_MMR6 |
6008 |
1U, // LSA_MMR6 |
| 6009 |
8324U, // LSA_R6 |
6009 |
8324U, // LSA_R6 |
| 6010 |
0U, // LUI_MMR6 |
6010 |
0U, // LUI_MMR6 |
| 6011 |
1U, // LUXC1 |
6011 |
1U, // LUXC1 |
| 6012 |
1U, // LUXC164 |
6012 |
1U, // LUXC164 |
| 6013 |
1U, // LUXC1_MM |
6013 |
1U, // LUXC1_MM |
| 6014 |
0U, // LUi |
6014 |
0U, // LUi |
| 6015 |
0U, // LUi64 |
6015 |
0U, // LUi64 |
| 6016 |
0U, // LUi_MM |
6016 |
0U, // LUi_MM |
| 6017 |
0U, // LW |
6017 |
0U, // LW |
| 6018 |
0U, // LW16_MM |
6018 |
0U, // LW16_MM |
| 6019 |
0U, // LW64 |
6019 |
0U, // LW64 |
| 6020 |
0U, // LWC1 |
6020 |
0U, // LWC1 |
| 6021 |
0U, // LWC1_MM |
6021 |
0U, // LWC1_MM |
| 6022 |
0U, // LWC2 |
6022 |
0U, // LWC2 |
| 6023 |
0U, // LWC2_MMR6 |
6023 |
0U, // LWC2_MMR6 |
| 6024 |
0U, // LWC2_R6 |
6024 |
0U, // LWC2_R6 |
| 6025 |
0U, // LWC3 |
6025 |
0U, // LWC3 |
| 6026 |
0U, // LWDSP |
6026 |
0U, // LWDSP |
| 6027 |
0U, // LWDSP_MM |
6027 |
0U, // LWDSP_MM |
| 6028 |
0U, // LWE |
6028 |
0U, // LWE |
| 6029 |
0U, // LWE_MM |
6029 |
0U, // LWE_MM |
| 6030 |
0U, // LWGP_MM |
6030 |
0U, // LWGP_MM |
| 6031 |
0U, // LWL |
6031 |
0U, // LWL |
| 6032 |
0U, // LWL64 |
6032 |
0U, // LWL64 |
| 6033 |
0U, // LWLE |
6033 |
0U, // LWLE |
| 6034 |
0U, // LWLE_MM |
6034 |
0U, // LWLE_MM |
| 6035 |
0U, // LWL_MM |
6035 |
0U, // LWL_MM |
| 6036 |
0U, // LWM16_MM |
6036 |
0U, // LWM16_MM |
| 6037 |
0U, // LWM16_MMR6 |
6037 |
0U, // LWM16_MMR6 |
| 6038 |
0U, // LWM32_MM |
6038 |
0U, // LWM32_MM |
| 6039 |
0U, // LWPC |
6039 |
0U, // LWPC |
| 6040 |
0U, // LWPC_MMR6 |
6040 |
0U, // LWPC_MMR6 |
| 6041 |
0U, // LWP_MM |
6041 |
0U, // LWP_MM |
| 6042 |
0U, // LWR |
6042 |
0U, // LWR |
| 6043 |
0U, // LWR64 |
6043 |
0U, // LWR64 |
| 6044 |
0U, // LWRE |
6044 |
0U, // LWRE |
| 6045 |
0U, // LWRE_MM |
6045 |
0U, // LWRE_MM |
| 6046 |
0U, // LWR_MM |
6046 |
0U, // LWR_MM |
| 6047 |
0U, // LWSP_MM |
6047 |
0U, // LWSP_MM |
| 6048 |
0U, // LWUPC |
6048 |
0U, // LWUPC |
| 6049 |
0U, // LWU_MM |
6049 |
0U, // LWU_MM |
| 6050 |
1U, // LWX |
6050 |
1U, // LWX |
| 6051 |
1U, // LWXC1 |
6051 |
1U, // LWXC1 |
| 6052 |
1U, // LWXC1_MM |
6052 |
1U, // LWXC1_MM |
| 6053 |
1U, // LWXS_MM |
6053 |
1U, // LWXS_MM |
| 6054 |
1U, // LWX_MM |
6054 |
1U, // LWX_MM |
| 6055 |
0U, // LW_MM |
6055 |
0U, // LW_MM |
| 6056 |
0U, // LW_MMR6 |
6056 |
0U, // LW_MMR6 |
| 6057 |
0U, // LWu |
6057 |
0U, // LWu |
| 6058 |
0U, // LbRxRyOffMemX16 |
6058 |
0U, // LbRxRyOffMemX16 |
| 6059 |
0U, // LbuRxRyOffMemX16 |
6059 |
0U, // LbuRxRyOffMemX16 |
| 6060 |
0U, // LhRxRyOffMemX16 |
6060 |
0U, // LhRxRyOffMemX16 |
| 6061 |
0U, // LhuRxRyOffMemX16 |
6061 |
0U, // LhuRxRyOffMemX16 |
| 6062 |
1U, // LiRxImm16 |
6062 |
1U, // LiRxImm16 |
| 6063 |
0U, // LiRxImmAlignX16 |
6063 |
0U, // LiRxImmAlignX16 |
| 6064 |
0U, // LiRxImmX16 |
6064 |
0U, // LiRxImmX16 |
| 6065 |
1U, // LwRxPcTcp16 |
6065 |
1U, // LwRxPcTcp16 |
| 6066 |
0U, // LwRxPcTcpX16 |
6066 |
0U, // LwRxPcTcpX16 |
| 6067 |
0U, // LwRxRyOffMemX16 |
6067 |
0U, // LwRxRyOffMemX16 |
| 6068 |
0U, // LwRxSpImmX16 |
6068 |
0U, // LwRxSpImmX16 |
| 6069 |
0U, // MADD |
6069 |
0U, // MADD |
| 6070 |
52U, // MADDF_D |
6070 |
52U, // MADDF_D |
| 6071 |
52U, // MADDF_D_MMR6 |
6071 |
52U, // MADDF_D_MMR6 |
| 6072 |
52U, // MADDF_S |
6072 |
52U, // MADDF_S |
| 6073 |
52U, // MADDF_S_MMR6 |
6073 |
52U, // MADDF_S_MMR6 |
| 6074 |
52U, // MADDR_Q_H |
6074 |
52U, // MADDR_Q_H |
| 6075 |
52U, // MADDR_Q_W |
6075 |
52U, // MADDR_Q_W |
| 6076 |
0U, // MADDU |
6076 |
0U, // MADDU |
| 6077 |
4U, // MADDU_DSP |
6077 |
4U, // MADDU_DSP |
| 6078 |
4U, // MADDU_DSP_MM |
6078 |
4U, // MADDU_DSP_MM |
| 6079 |
0U, // MADDU_MM |
6079 |
0U, // MADDU_MM |
| 6080 |
52U, // MADDV_B |
6080 |
52U, // MADDV_B |
| 6081 |
52U, // MADDV_D |
6081 |
52U, // MADDV_D |
| 6082 |
52U, // MADDV_H |
6082 |
52U, // MADDV_H |
| 6083 |
52U, // MADDV_W |
6083 |
52U, // MADDV_W |
| 6084 |
9348U, // MADD_D32 |
6084 |
9348U, // MADD_D32 |
| 6085 |
9348U, // MADD_D32_MM |
6085 |
9348U, // MADD_D32_MM |
| 6086 |
9348U, // MADD_D64 |
6086 |
9348U, // MADD_D64 |
| 6087 |
4U, // MADD_DSP |
6087 |
4U, // MADD_DSP |
| 6088 |
4U, // MADD_DSP_MM |
6088 |
4U, // MADD_DSP_MM |
| 6089 |
0U, // MADD_MM |
6089 |
0U, // MADD_MM |
| 6090 |
52U, // MADD_Q_H |
6090 |
52U, // MADD_Q_H |
| 6091 |
52U, // MADD_Q_W |
6091 |
52U, // MADD_Q_W |
| 6092 |
9348U, // MADD_S |
6092 |
9348U, // MADD_S |
| 6093 |
9348U, // MADD_S_MM |
6093 |
9348U, // MADD_S_MM |
| 6094 |
4U, // MAQ_SA_W_PHL |
6094 |
4U, // MAQ_SA_W_PHL |
| 6095 |
4U, // MAQ_SA_W_PHL_MM |
6095 |
4U, // MAQ_SA_W_PHL_MM |
| 6096 |
4U, // MAQ_SA_W_PHR |
6096 |
4U, // MAQ_SA_W_PHR |
| 6097 |
4U, // MAQ_SA_W_PHR_MM |
6097 |
4U, // MAQ_SA_W_PHR_MM |
| 6098 |
4U, // MAQ_S_W_PHL |
6098 |
4U, // MAQ_S_W_PHL |
| 6099 |
4U, // MAQ_S_W_PHL_MM |
6099 |
4U, // MAQ_S_W_PHL_MM |
| 6100 |
4U, // MAQ_S_W_PHR |
6100 |
4U, // MAQ_S_W_PHR |
| 6101 |
4U, // MAQ_S_W_PHR_MM |
6101 |
4U, // MAQ_S_W_PHR_MM |
| 6102 |
4U, // MAXA_D |
6102 |
4U, // MAXA_D |
| 6103 |
4U, // MAXA_D_MMR6 |
6103 |
4U, // MAXA_D_MMR6 |
| 6104 |
4U, // MAXA_S |
6104 |
4U, // MAXA_S |
| 6105 |
4U, // MAXA_S_MMR6 |
6105 |
4U, // MAXA_S_MMR6 |
| 6106 |
4U, // MAXI_S_B |
6106 |
4U, // MAXI_S_B |
| 6107 |
4U, // MAXI_S_D |
6107 |
4U, // MAXI_S_D |
| 6108 |
4U, // MAXI_S_H |
6108 |
4U, // MAXI_S_H |
| 6109 |
4U, // MAXI_S_W |
6109 |
4U, // MAXI_S_W |
| 6110 |
12U, // MAXI_U_B |
6110 |
12U, // MAXI_U_B |
| 6111 |
12U, // MAXI_U_D |
6111 |
12U, // MAXI_U_D |
| 6112 |
12U, // MAXI_U_H |
6112 |
12U, // MAXI_U_H |
| 6113 |
12U, // MAXI_U_W |
6113 |
12U, // MAXI_U_W |
| 6114 |
4U, // MAX_A_B |
6114 |
4U, // MAX_A_B |
| 6115 |
4U, // MAX_A_D |
6115 |
4U, // MAX_A_D |
| 6116 |
4U, // MAX_A_H |
6116 |
4U, // MAX_A_H |
| 6117 |
4U, // MAX_A_W |
6117 |
4U, // MAX_A_W |
| 6118 |
4U, // MAX_D |
6118 |
4U, // MAX_D |
| 6119 |
4U, // MAX_D_MMR6 |
6119 |
4U, // MAX_D_MMR6 |
| 6120 |
4U, // MAX_S |
6120 |
4U, // MAX_S |
| 6121 |
4U, // MAX_S_B |
6121 |
4U, // MAX_S_B |
| 6122 |
4U, // MAX_S_D |
6122 |
4U, // MAX_S_D |
| 6123 |
4U, // MAX_S_H |
6123 |
4U, // MAX_S_H |
| 6124 |
4U, // MAX_S_MMR6 |
6124 |
4U, // MAX_S_MMR6 |
| 6125 |
4U, // MAX_S_W |
6125 |
4U, // MAX_S_W |
| 6126 |
4U, // MAX_U_B |
6126 |
4U, // MAX_U_B |
| 6127 |
4U, // MAX_U_D |
6127 |
4U, // MAX_U_D |
| 6128 |
4U, // MAX_U_H |
6128 |
4U, // MAX_U_H |
| 6129 |
4U, // MAX_U_W |
6129 |
4U, // MAX_U_W |
| 6130 |
8U, // MFC0 |
6130 |
8U, // MFC0 |
| 6131 |
8U, // MFC0_MMR6 |
6131 |
8U, // MFC0_MMR6 |
| 6132 |
0U, // MFC1 |
6132 |
0U, // MFC1 |
| 6133 |
0U, // MFC1_D64 |
6133 |
0U, // MFC1_D64 |
| 6134 |
0U, // MFC1_MM |
6134 |
0U, // MFC1_MM |
| 6135 |
0U, // MFC1_MMR6 |
6135 |
0U, // MFC1_MMR6 |
| 6136 |
8U, // MFC2 |
6136 |
8U, // MFC2 |
| 6137 |
0U, // MFC2_MMR6 |
6137 |
0U, // MFC2_MMR6 |
| 6138 |
8U, // MFGC0 |
6138 |
8U, // MFGC0 |
| 6139 |
8U, // MFGC0_MM |
6139 |
8U, // MFGC0_MM |
| 6140 |
8U, // MFHC0_MMR6 |
6140 |
8U, // MFHC0_MMR6 |
| 6141 |
0U, // MFHC1_D32 |
6141 |
0U, // MFHC1_D32 |
| 6142 |
0U, // MFHC1_D32_MM |
6142 |
0U, // MFHC1_D32_MM |
| 6143 |
0U, // MFHC1_D64 |
6143 |
0U, // MFHC1_D64 |
| 6144 |
0U, // MFHC1_D64_MM |
6144 |
0U, // MFHC1_D64_MM |
| 6145 |
0U, // MFHC2_MMR6 |
6145 |
0U, // MFHC2_MMR6 |
| 6146 |
8U, // MFHGC0 |
6146 |
8U, // MFHGC0 |
| 6147 |
8U, // MFHGC0_MM |
6147 |
8U, // MFHGC0_MM |
| 6148 |
0U, // MFHI |
6148 |
0U, // MFHI |
| 6149 |
0U, // MFHI16_MM |
6149 |
0U, // MFHI16_MM |
| 6150 |
0U, // MFHI64 |
6150 |
0U, // MFHI64 |
| 6151 |
0U, // MFHI_DSP |
6151 |
0U, // MFHI_DSP |
| 6152 |
0U, // MFHI_DSP_MM |
6152 |
0U, // MFHI_DSP_MM |
| 6153 |
0U, // MFHI_MM |
6153 |
0U, // MFHI_MM |
| 6154 |
0U, // MFLO |
6154 |
0U, // MFLO |
| 6155 |
0U, // MFLO16_MM |
6155 |
0U, // MFLO16_MM |
| 6156 |
0U, // MFLO64 |
6156 |
0U, // MFLO64 |
| 6157 |
0U, // MFLO_DSP |
6157 |
0U, // MFLO_DSP |
| 6158 |
0U, // MFLO_DSP_MM |
6158 |
0U, // MFLO_DSP_MM |
| 6159 |
0U, // MFLO_MM |
6159 |
0U, // MFLO_MM |
| 6160 |
18620U, // MFTR |
6160 |
18620U, // MFTR |
| 6161 |
4U, // MINA_D |
6161 |
4U, // MINA_D |
| 6162 |
4U, // MINA_D_MMR6 |
6162 |
4U, // MINA_D_MMR6 |
| 6163 |
4U, // MINA_S |
6163 |
4U, // MINA_S |
| 6164 |
4U, // MINA_S_MMR6 |
6164 |
4U, // MINA_S_MMR6 |
| 6165 |
4U, // MINI_S_B |
6165 |
4U, // MINI_S_B |
| 6166 |
4U, // MINI_S_D |
6166 |
4U, // MINI_S_D |
| 6167 |
4U, // MINI_S_H |
6167 |
4U, // MINI_S_H |
| 6168 |
4U, // MINI_S_W |
6168 |
4U, // MINI_S_W |
| 6169 |
12U, // MINI_U_B |
6169 |
12U, // MINI_U_B |
| 6170 |
12U, // MINI_U_D |
6170 |
12U, // MINI_U_D |
| 6171 |
12U, // MINI_U_H |
6171 |
12U, // MINI_U_H |
| 6172 |
12U, // MINI_U_W |
6172 |
12U, // MINI_U_W |
| 6173 |
4U, // MIN_A_B |
6173 |
4U, // MIN_A_B |
| 6174 |
4U, // MIN_A_D |
6174 |
4U, // MIN_A_D |
| 6175 |
4U, // MIN_A_H |
6175 |
4U, // MIN_A_H |
| 6176 |
4U, // MIN_A_W |
6176 |
4U, // MIN_A_W |
| 6177 |
4U, // MIN_D |
6177 |
4U, // MIN_D |
| 6178 |
4U, // MIN_D_MMR6 |
6178 |
4U, // MIN_D_MMR6 |
| 6179 |
4U, // MIN_S |
6179 |
4U, // MIN_S |
| 6180 |
4U, // MIN_S_B |
6180 |
4U, // MIN_S_B |
| 6181 |
4U, // MIN_S_D |
6181 |
4U, // MIN_S_D |
| 6182 |
4U, // MIN_S_H |
6182 |
4U, // MIN_S_H |
| 6183 |
4U, // MIN_S_MMR6 |
6183 |
4U, // MIN_S_MMR6 |
| 6184 |
4U, // MIN_S_W |
6184 |
4U, // MIN_S_W |
| 6185 |
4U, // MIN_U_B |
6185 |
4U, // MIN_U_B |
| 6186 |
4U, // MIN_U_D |
6186 |
4U, // MIN_U_D |
| 6187 |
4U, // MIN_U_H |
6187 |
4U, // MIN_U_H |
| 6188 |
4U, // MIN_U_W |
6188 |
4U, // MIN_U_W |
| 6189 |
4U, // MOD |
6189 |
4U, // MOD |
| 6190 |
4U, // MODSUB |
6190 |
4U, // MODSUB |
| 6191 |
4U, // MODSUB_MM |
6191 |
4U, // MODSUB_MM |
| 6192 |
4U, // MODU |
6192 |
4U, // MODU |
| 6193 |
4U, // MODU_MMR6 |
6193 |
4U, // MODU_MMR6 |
| 6194 |
4U, // MOD_MMR6 |
6194 |
4U, // MOD_MMR6 |
| 6195 |
4U, // MOD_S_B |
6195 |
4U, // MOD_S_B |
| 6196 |
4U, // MOD_S_D |
6196 |
4U, // MOD_S_D |
| 6197 |
4U, // MOD_S_H |
6197 |
4U, // MOD_S_H |
| 6198 |
4U, // MOD_S_W |
6198 |
4U, // MOD_S_W |
| 6199 |
4U, // MOD_U_B |
6199 |
4U, // MOD_U_B |
| 6200 |
4U, // MOD_U_D |
6200 |
4U, // MOD_U_D |
| 6201 |
4U, // MOD_U_H |
6201 |
4U, // MOD_U_H |
| 6202 |
4U, // MOD_U_W |
6202 |
4U, // MOD_U_W |
| 6203 |
0U, // MOVE16_MM |
6203 |
0U, // MOVE16_MM |
| 6204 |
0U, // MOVE16_MMR6 |
6204 |
0U, // MOVE16_MMR6 |
| 6205 |
9348U, // MOVEP_MM |
6205 |
9348U, // MOVEP_MM |
| 6206 |
9348U, // MOVEP_MMR6 |
6206 |
9348U, // MOVEP_MMR6 |
| 6207 |
0U, // MOVE_V |
6207 |
0U, // MOVE_V |
| 6208 |
4U, // MOVF_D32 |
6208 |
4U, // MOVF_D32 |
| 6209 |
4U, // MOVF_D32_MM |
6209 |
4U, // MOVF_D32_MM |
| 6210 |
4U, // MOVF_D64 |
6210 |
4U, // MOVF_D64 |
| 6211 |
4U, // MOVF_I |
6211 |
4U, // MOVF_I |
| 6212 |
4U, // MOVF_I64 |
6212 |
4U, // MOVF_I64 |
| 6213 |
4U, // MOVF_I_MM |
6213 |
4U, // MOVF_I_MM |
| 6214 |
4U, // MOVF_S |
6214 |
4U, // MOVF_S |
| 6215 |
4U, // MOVF_S_MM |
6215 |
4U, // MOVF_S_MM |
| 6216 |
4U, // MOVN_I64_D64 |
6216 |
4U, // MOVN_I64_D64 |
| 6217 |
4U, // MOVN_I64_I |
6217 |
4U, // MOVN_I64_I |
| 6218 |
4U, // MOVN_I64_I64 |
6218 |
4U, // MOVN_I64_I64 |
| 6219 |
4U, // MOVN_I64_S |
6219 |
4U, // MOVN_I64_S |
| 6220 |
4U, // MOVN_I_D32 |
6220 |
4U, // MOVN_I_D32 |
| 6221 |
4U, // MOVN_I_D32_MM |
6221 |
4U, // MOVN_I_D32_MM |
| 6222 |
4U, // MOVN_I_D64 |
6222 |
4U, // MOVN_I_D64 |
| 6223 |
4U, // MOVN_I_I |
6223 |
4U, // MOVN_I_I |
| 6224 |
4U, // MOVN_I_I64 |
6224 |
4U, // MOVN_I_I64 |
| 6225 |
4U, // MOVN_I_MM |
6225 |
4U, // MOVN_I_MM |
| 6226 |
4U, // MOVN_I_S |
6226 |
4U, // MOVN_I_S |
| 6227 |
4U, // MOVN_I_S_MM |
6227 |
4U, // MOVN_I_S_MM |
| 6228 |
4U, // MOVT_D32 |
6228 |
4U, // MOVT_D32 |
| 6229 |
4U, // MOVT_D32_MM |
6229 |
4U, // MOVT_D32_MM |
| 6230 |
4U, // MOVT_D64 |
6230 |
4U, // MOVT_D64 |
| 6231 |
4U, // MOVT_I |
6231 |
4U, // MOVT_I |
| 6232 |
4U, // MOVT_I64 |
6232 |
4U, // MOVT_I64 |
| 6233 |
4U, // MOVT_I_MM |
6233 |
4U, // MOVT_I_MM |
| 6234 |
4U, // MOVT_S |
6234 |
4U, // MOVT_S |
| 6235 |
4U, // MOVT_S_MM |
6235 |
4U, // MOVT_S_MM |
| 6236 |
4U, // MOVZ_I64_D64 |
6236 |
4U, // MOVZ_I64_D64 |
| 6237 |
4U, // MOVZ_I64_I |
6237 |
4U, // MOVZ_I64_I |
| 6238 |
4U, // MOVZ_I64_I64 |
6238 |
4U, // MOVZ_I64_I64 |
| 6239 |
4U, // MOVZ_I64_S |
6239 |
4U, // MOVZ_I64_S |
| 6240 |
4U, // MOVZ_I_D32 |
6240 |
4U, // MOVZ_I_D32 |
| 6241 |
4U, // MOVZ_I_D32_MM |
6241 |
4U, // MOVZ_I_D32_MM |
| 6242 |
4U, // MOVZ_I_D64 |
6242 |
4U, // MOVZ_I_D64 |
| 6243 |
4U, // MOVZ_I_I |
6243 |
4U, // MOVZ_I_I |
| 6244 |
4U, // MOVZ_I_I64 |
6244 |
4U, // MOVZ_I_I64 |
| 6245 |
4U, // MOVZ_I_MM |
6245 |
4U, // MOVZ_I_MM |
| 6246 |
4U, // MOVZ_I_S |
6246 |
4U, // MOVZ_I_S |
| 6247 |
4U, // MOVZ_I_S_MM |
6247 |
4U, // MOVZ_I_S_MM |
| 6248 |
0U, // MSUB |
6248 |
0U, // MSUB |
| 6249 |
52U, // MSUBF_D |
6249 |
52U, // MSUBF_D |
| 6250 |
52U, // MSUBF_D_MMR6 |
6250 |
52U, // MSUBF_D_MMR6 |
| 6251 |
52U, // MSUBF_S |
6251 |
52U, // MSUBF_S |
| 6252 |
52U, // MSUBF_S_MMR6 |
6252 |
52U, // MSUBF_S_MMR6 |
| 6253 |
52U, // MSUBR_Q_H |
6253 |
52U, // MSUBR_Q_H |
| 6254 |
52U, // MSUBR_Q_W |
6254 |
52U, // MSUBR_Q_W |
| 6255 |
0U, // MSUBU |
6255 |
0U, // MSUBU |
| 6256 |
4U, // MSUBU_DSP |
6256 |
4U, // MSUBU_DSP |
| 6257 |
4U, // MSUBU_DSP_MM |
6257 |
4U, // MSUBU_DSP_MM |
| 6258 |
0U, // MSUBU_MM |
6258 |
0U, // MSUBU_MM |
| 6259 |
52U, // MSUBV_B |
6259 |
52U, // MSUBV_B |
| 6260 |
52U, // MSUBV_D |
6260 |
52U, // MSUBV_D |
| 6261 |
52U, // MSUBV_H |
6261 |
52U, // MSUBV_H |
| 6262 |
52U, // MSUBV_W |
6262 |
52U, // MSUBV_W |
| 6263 |
9348U, // MSUB_D32 |
6263 |
9348U, // MSUB_D32 |
| 6264 |
9348U, // MSUB_D32_MM |
6264 |
9348U, // MSUB_D32_MM |
| 6265 |
9348U, // MSUB_D64 |
6265 |
9348U, // MSUB_D64 |
| 6266 |
4U, // MSUB_DSP |
6266 |
4U, // MSUB_DSP |
| 6267 |
4U, // MSUB_DSP_MM |
6267 |
4U, // MSUB_DSP_MM |
| 6268 |
0U, // MSUB_MM |
6268 |
0U, // MSUB_MM |
| 6269 |
52U, // MSUB_Q_H |
6269 |
52U, // MSUB_Q_H |
| 6270 |
52U, // MSUB_Q_W |
6270 |
52U, // MSUB_Q_W |
| 6271 |
9348U, // MSUB_S |
6271 |
9348U, // MSUB_S |
| 6272 |
9348U, // MSUB_S_MM |
6272 |
9348U, // MSUB_S_MM |
| 6273 |
0U, // MTC0 |
6273 |
0U, // MTC0 |
| 6274 |
0U, // MTC0_MMR6 |
6274 |
0U, // MTC0_MMR6 |
| 6275 |
0U, // MTC1 |
6275 |
0U, // MTC1 |
| 6276 |
0U, // MTC1_D64 |
6276 |
0U, // MTC1_D64 |
| 6277 |
0U, // MTC1_D64_MM |
6277 |
0U, // MTC1_D64_MM |
| 6278 |
0U, // MTC1_MM |
6278 |
0U, // MTC1_MM |
| 6279 |
0U, // MTC1_MMR6 |
6279 |
0U, // MTC1_MMR6 |
| 6280 |
0U, // MTC2 |
6280 |
0U, // MTC2 |
| 6281 |
0U, // MTC2_MMR6 |
6281 |
0U, // MTC2_MMR6 |
| 6282 |
0U, // MTGC0 |
6282 |
0U, // MTGC0 |
| 6283 |
0U, // MTGC0_MM |
6283 |
0U, // MTGC0_MM |
| 6284 |
0U, // MTHC0_MMR6 |
6284 |
0U, // MTHC0_MMR6 |
| 6285 |
0U, // MTHC1_D32 |
6285 |
0U, // MTHC1_D32 |
| 6286 |
0U, // MTHC1_D32_MM |
6286 |
0U, // MTHC1_D32_MM |
| 6287 |
0U, // MTHC1_D64 |
6287 |
0U, // MTHC1_D64 |
| 6288 |
0U, // MTHC1_D64_MM |
6288 |
0U, // MTHC1_D64_MM |
| 6289 |
0U, // MTHC2_MMR6 |
6289 |
0U, // MTHC2_MMR6 |
| 6290 |
0U, // MTHGC0 |
6290 |
0U, // MTHGC0 |
| 6291 |
0U, // MTHGC0_MM |
6291 |
0U, // MTHGC0_MM |
| 6292 |
0U, // MTHI |
6292 |
0U, // MTHI |
| 6293 |
0U, // MTHI64 |
6293 |
0U, // MTHI64 |
| 6294 |
0U, // MTHI_DSP |
6294 |
0U, // MTHI_DSP |
| 6295 |
0U, // MTHI_DSP_MM |
6295 |
0U, // MTHI_DSP_MM |
| 6296 |
0U, // MTHI_MM |
6296 |
0U, // MTHI_MM |
| 6297 |
0U, // MTHLIP |
6297 |
0U, // MTHLIP |
| 6298 |
0U, // MTHLIP_MM |
6298 |
0U, // MTHLIP_MM |
| 6299 |
0U, // MTLO |
6299 |
0U, // MTLO |
| 6300 |
0U, // MTLO64 |
6300 |
0U, // MTLO64 |
| 6301 |
0U, // MTLO_DSP |
6301 |
0U, // MTLO_DSP |
| 6302 |
0U, // MTLO_DSP_MM |
6302 |
0U, // MTLO_DSP_MM |
| 6303 |
0U, // MTLO_MM |
6303 |
0U, // MTLO_MM |
| 6304 |
0U, // MTM0 |
6304 |
0U, // MTM0 |
| 6305 |
0U, // MTM1 |
6305 |
0U, // MTM1 |
| 6306 |
0U, // MTM2 |
6306 |
0U, // MTM2 |
| 6307 |
0U, // MTP0 |
6307 |
0U, // MTP0 |
| 6308 |
0U, // MTP1 |
6308 |
0U, // MTP1 |
| 6309 |
0U, // MTP2 |
6309 |
0U, // MTP2 |
| 6310 |
2U, // MTTR |
6310 |
2U, // MTTR |
| 6311 |
4U, // MUH |
6311 |
4U, // MUH |
| 6312 |
4U, // MUHU |
6312 |
4U, // MUHU |
| 6313 |
4U, // MUHU_MMR6 |
6313 |
4U, // MUHU_MMR6 |
| 6314 |
4U, // MUH_MMR6 |
6314 |
4U, // MUH_MMR6 |
| 6315 |
4U, // MUL |
6315 |
4U, // MUL |
| 6316 |
4U, // MULEQ_S_W_PHL |
6316 |
4U, // MULEQ_S_W_PHL |
| 6317 |
4U, // MULEQ_S_W_PHL_MM |
6317 |
4U, // MULEQ_S_W_PHL_MM |
| 6318 |
4U, // MULEQ_S_W_PHR |
6318 |
4U, // MULEQ_S_W_PHR |
| 6319 |
4U, // MULEQ_S_W_PHR_MM |
6319 |
4U, // MULEQ_S_W_PHR_MM |
| 6320 |
4U, // MULEU_S_PH_QBL |
6320 |
4U, // MULEU_S_PH_QBL |
| 6321 |
4U, // MULEU_S_PH_QBL_MM |
6321 |
4U, // MULEU_S_PH_QBL_MM |
| 6322 |
4U, // MULEU_S_PH_QBR |
6322 |
4U, // MULEU_S_PH_QBR |
| 6323 |
4U, // MULEU_S_PH_QBR_MM |
6323 |
4U, // MULEU_S_PH_QBR_MM |
| 6324 |
4U, // MULQ_RS_PH |
6324 |
4U, // MULQ_RS_PH |
| 6325 |
4U, // MULQ_RS_PH_MM |
6325 |
4U, // MULQ_RS_PH_MM |
| 6326 |
4U, // MULQ_RS_W |
6326 |
4U, // MULQ_RS_W |
| 6327 |
4U, // MULQ_RS_W_MMR2 |
6327 |
4U, // MULQ_RS_W_MMR2 |
| 6328 |
4U, // MULQ_S_PH |
6328 |
4U, // MULQ_S_PH |
| 6329 |
4U, // MULQ_S_PH_MMR2 |
6329 |
4U, // MULQ_S_PH_MMR2 |
| 6330 |
4U, // MULQ_S_W |
6330 |
4U, // MULQ_S_W |
| 6331 |
4U, // MULQ_S_W_MMR2 |
6331 |
4U, // MULQ_S_W_MMR2 |
| 6332 |
4U, // MULR_PS64 |
6332 |
4U, // MULR_PS64 |
| 6333 |
4U, // MULR_Q_H |
6333 |
4U, // MULR_Q_H |
| 6334 |
4U, // MULR_Q_W |
6334 |
4U, // MULR_Q_W |
| 6335 |
4U, // MULSAQ_S_W_PH |
6335 |
4U, // MULSAQ_S_W_PH |
| 6336 |
4U, // MULSAQ_S_W_PH_MM |
6336 |
4U, // MULSAQ_S_W_PH_MM |
| 6337 |
4U, // MULSA_W_PH |
6337 |
4U, // MULSA_W_PH |
| 6338 |
4U, // MULSA_W_PH_MMR2 |
6338 |
4U, // MULSA_W_PH_MMR2 |
| 6339 |
0U, // MULT |
6339 |
0U, // MULT |
| 6340 |
4U, // MULTU_DSP |
6340 |
4U, // MULTU_DSP |
| 6341 |
4U, // MULTU_DSP_MM |
6341 |
4U, // MULTU_DSP_MM |
| 6342 |
4U, // MULT_DSP |
6342 |
4U, // MULT_DSP |
| 6343 |
4U, // MULT_DSP_MM |
6343 |
4U, // MULT_DSP_MM |
| 6344 |
0U, // MULT_MM |
6344 |
0U, // MULT_MM |
| 6345 |
0U, // MULTu |
6345 |
0U, // MULTu |
| 6346 |
0U, // MULTu_MM |
6346 |
0U, // MULTu_MM |
| 6347 |
4U, // MULU |
6347 |
4U, // MULU |
| 6348 |
4U, // MULU_MMR6 |
6348 |
4U, // MULU_MMR6 |
| 6349 |
4U, // MULV_B |
6349 |
4U, // MULV_B |
| 6350 |
4U, // MULV_D |
6350 |
4U, // MULV_D |
| 6351 |
4U, // MULV_H |
6351 |
4U, // MULV_H |
| 6352 |
4U, // MULV_W |
6352 |
4U, // MULV_W |
| 6353 |
4U, // MUL_MM |
6353 |
4U, // MUL_MM |
| 6354 |
4U, // MUL_MMR6 |
6354 |
4U, // MUL_MMR6 |
| 6355 |
4U, // MUL_PH |
6355 |
4U, // MUL_PH |
| 6356 |
4U, // MUL_PH_MMR2 |
6356 |
4U, // MUL_PH_MMR2 |
| 6357 |
4U, // MUL_Q_H |
6357 |
4U, // MUL_Q_H |
| 6358 |
4U, // MUL_Q_W |
6358 |
4U, // MUL_Q_W |
| 6359 |
4U, // MUL_R6 |
6359 |
4U, // MUL_R6 |
| 6360 |
4U, // MUL_S_PH |
6360 |
4U, // MUL_S_PH |
| 6361 |
4U, // MUL_S_PH_MMR2 |
6361 |
4U, // MUL_S_PH_MMR2 |
| 6362 |
0U, // Mfhi16 |
6362 |
0U, // Mfhi16 |
| 6363 |
0U, // Mflo16 |
6363 |
0U, // Mflo16 |
| 6364 |
0U, // Move32R16 |
6364 |
0U, // Move32R16 |
| 6365 |
0U, // MoveR3216 |
6365 |
0U, // MoveR3216 |
| 6366 |
0U, // NLOC_B |
6366 |
0U, // NLOC_B |
| 6367 |
0U, // NLOC_D |
6367 |
0U, // NLOC_D |
| 6368 |
0U, // NLOC_H |
6368 |
0U, // NLOC_H |
| 6369 |
0U, // NLOC_W |
6369 |
0U, // NLOC_W |
| 6370 |
0U, // NLZC_B |
6370 |
0U, // NLZC_B |
| 6371 |
0U, // NLZC_D |
6371 |
0U, // NLZC_D |
| 6372 |
0U, // NLZC_H |
6372 |
0U, // NLZC_H |
| 6373 |
0U, // NLZC_W |
6373 |
0U, // NLZC_W |
| 6374 |
9348U, // NMADD_D32 |
6374 |
9348U, // NMADD_D32 |
| 6375 |
9348U, // NMADD_D32_MM |
6375 |
9348U, // NMADD_D32_MM |
| 6376 |
9348U, // NMADD_D64 |
6376 |
9348U, // NMADD_D64 |
| 6377 |
9348U, // NMADD_S |
6377 |
9348U, // NMADD_S |
| 6378 |
9348U, // NMADD_S_MM |
6378 |
9348U, // NMADD_S_MM |
| 6379 |
9348U, // NMSUB_D32 |
6379 |
9348U, // NMSUB_D32 |
| 6380 |
9348U, // NMSUB_D32_MM |
6380 |
9348U, // NMSUB_D32_MM |
| 6381 |
9348U, // NMSUB_D64 |
6381 |
9348U, // NMSUB_D64 |
| 6382 |
9348U, // NMSUB_S |
6382 |
9348U, // NMSUB_S |
| 6383 |
9348U, // NMSUB_S_MM |
6383 |
9348U, // NMSUB_S_MM |
| 6384 |
4U, // NOR |
6384 |
4U, // NOR |
| 6385 |
4U, // NOR64 |
6385 |
4U, // NOR64 |
| 6386 |
16U, // NORI_B |
6386 |
16U, // NORI_B |
| 6387 |
4U, // NOR_MM |
6387 |
4U, // NOR_MM |
| 6388 |
4U, // NOR_MMR6 |
6388 |
4U, // NOR_MMR6 |
| 6389 |
4U, // NOR_V |
6389 |
4U, // NOR_V |
| 6390 |
0U, // NOT16_MM |
6390 |
0U, // NOT16_MM |
| 6391 |
0U, // NOT16_MMR6 |
6391 |
0U, // NOT16_MMR6 |
| 6392 |
0U, // NegRxRy16 |
6392 |
0U, // NegRxRy16 |
| 6393 |
0U, // NotRxRy16 |
6393 |
0U, // NotRxRy16 |
| 6394 |
4U, // OR |
6394 |
4U, // OR |
| 6395 |
0U, // OR16_MM |
6395 |
0U, // OR16_MM |
| 6396 |
0U, // OR16_MMR6 |
6396 |
0U, // OR16_MMR6 |
| 6397 |
4U, // OR64 |
6397 |
4U, // OR64 |
| 6398 |
16U, // ORI_B |
6398 |
16U, // ORI_B |
| 6399 |
20U, // ORI_MMR6 |
6399 |
20U, // ORI_MMR6 |
| 6400 |
4U, // OR_MM |
6400 |
4U, // OR_MM |
| 6401 |
4U, // OR_MMR6 |
6401 |
4U, // OR_MMR6 |
| 6402 |
4U, // OR_V |
6402 |
4U, // OR_V |
| 6403 |
20U, // ORi |
6403 |
20U, // ORi |
| 6404 |
20U, // ORi64 |
6404 |
20U, // ORi64 |
| 6405 |
20U, // ORi_MM |
6405 |
20U, // ORi_MM |
| 6406 |
0U, // OrRxRxRy16 |
6406 |
0U, // OrRxRxRy16 |
| 6407 |
4U, // PACKRL_PH |
6407 |
4U, // PACKRL_PH |
| 6408 |
4U, // PACKRL_PH_MM |
6408 |
4U, // PACKRL_PH_MM |
| 6409 |
0U, // PAUSE |
6409 |
0U, // PAUSE |
| 6410 |
0U, // PAUSE_MM |
6410 |
0U, // PAUSE_MM |
| 6411 |
0U, // PAUSE_MMR6 |
6411 |
0U, // PAUSE_MMR6 |
| 6412 |
4U, // PCKEV_B |
6412 |
4U, // PCKEV_B |
| 6413 |
4U, // PCKEV_D |
6413 |
4U, // PCKEV_D |
| 6414 |
4U, // PCKEV_H |
6414 |
4U, // PCKEV_H |
| 6415 |
4U, // PCKEV_W |
6415 |
4U, // PCKEV_W |
| 6416 |
4U, // PCKOD_B |
6416 |
4U, // PCKOD_B |
| 6417 |
4U, // PCKOD_D |
6417 |
4U, // PCKOD_D |
| 6418 |
4U, // PCKOD_H |
6418 |
4U, // PCKOD_H |
| 6419 |
4U, // PCKOD_W |
6419 |
4U, // PCKOD_W |
| 6420 |
0U, // PCNT_B |
6420 |
0U, // PCNT_B |
| 6421 |
0U, // PCNT_D |
6421 |
0U, // PCNT_D |
| 6422 |
0U, // PCNT_H |
6422 |
0U, // PCNT_H |
| 6423 |
0U, // PCNT_W |
6423 |
0U, // PCNT_W |
| 6424 |
4U, // PICK_PH |
6424 |
4U, // PICK_PH |
| 6425 |
4U, // PICK_PH_MM |
6425 |
4U, // PICK_PH_MM |
| 6426 |
4U, // PICK_QB |
6426 |
4U, // PICK_QB |
| 6427 |
4U, // PICK_QB_MM |
6427 |
4U, // PICK_QB_MM |
| 6428 |
4U, // PLL_PS64 |
6428 |
4U, // PLL_PS64 |
| 6429 |
4U, // PLU_PS64 |
6429 |
4U, // PLU_PS64 |
| 6430 |
0U, // POP |
6430 |
0U, // POP |
| 6431 |
0U, // PRECEQU_PH_QBL |
6431 |
0U, // PRECEQU_PH_QBL |
| 6432 |
0U, // PRECEQU_PH_QBLA |
6432 |
0U, // PRECEQU_PH_QBLA |
| 6433 |
0U, // PRECEQU_PH_QBLA_MM |
6433 |
0U, // PRECEQU_PH_QBLA_MM |
| 6434 |
0U, // PRECEQU_PH_QBL_MM |
6434 |
0U, // PRECEQU_PH_QBL_MM |
| 6435 |
0U, // PRECEQU_PH_QBR |
6435 |
0U, // PRECEQU_PH_QBR |
| 6436 |
0U, // PRECEQU_PH_QBRA |
6436 |
0U, // PRECEQU_PH_QBRA |
| 6437 |
0U, // PRECEQU_PH_QBRA_MM |
6437 |
0U, // PRECEQU_PH_QBRA_MM |
| 6438 |
0U, // PRECEQU_PH_QBR_MM |
6438 |
0U, // PRECEQU_PH_QBR_MM |
| 6439 |
0U, // PRECEQ_W_PHL |
6439 |
0U, // PRECEQ_W_PHL |
| 6440 |
0U, // PRECEQ_W_PHL_MM |
6440 |
0U, // PRECEQ_W_PHL_MM |
| 6441 |
0U, // PRECEQ_W_PHR |
6441 |
0U, // PRECEQ_W_PHR |
| 6442 |
0U, // PRECEQ_W_PHR_MM |
6442 |
0U, // PRECEQ_W_PHR_MM |
| 6443 |
0U, // PRECEU_PH_QBL |
6443 |
0U, // PRECEU_PH_QBL |
| 6444 |
0U, // PRECEU_PH_QBLA |
6444 |
0U, // PRECEU_PH_QBLA |
| 6445 |
0U, // PRECEU_PH_QBLA_MM |
6445 |
0U, // PRECEU_PH_QBLA_MM |
| 6446 |
0U, // PRECEU_PH_QBL_MM |
6446 |
0U, // PRECEU_PH_QBL_MM |
| 6447 |
0U, // PRECEU_PH_QBR |
6447 |
0U, // PRECEU_PH_QBR |
| 6448 |
0U, // PRECEU_PH_QBRA |
6448 |
0U, // PRECEU_PH_QBRA |
| 6449 |
0U, // PRECEU_PH_QBRA_MM |
6449 |
0U, // PRECEU_PH_QBRA_MM |
| 6450 |
0U, // PRECEU_PH_QBR_MM |
6450 |
0U, // PRECEU_PH_QBR_MM |
| 6451 |
4U, // PRECRQU_S_QB_PH |
6451 |
4U, // PRECRQU_S_QB_PH |
| 6452 |
4U, // PRECRQU_S_QB_PH_MM |
6452 |
4U, // PRECRQU_S_QB_PH_MM |
| 6453 |
4U, // PRECRQ_PH_W |
6453 |
4U, // PRECRQ_PH_W |
| 6454 |
4U, // PRECRQ_PH_W_MM |
6454 |
4U, // PRECRQ_PH_W_MM |
| 6455 |
4U, // PRECRQ_QB_PH |
6455 |
4U, // PRECRQ_QB_PH |
| 6456 |
4U, // PRECRQ_QB_PH_MM |
6456 |
4U, // PRECRQ_QB_PH_MM |
| 6457 |
4U, // PRECRQ_RS_PH_W |
6457 |
4U, // PRECRQ_RS_PH_W |
| 6458 |
4U, // PRECRQ_RS_PH_W_MM |
6458 |
4U, // PRECRQ_RS_PH_W_MM |
| 6459 |
4U, // PRECR_QB_PH |
6459 |
4U, // PRECR_QB_PH |
| 6460 |
4U, // PRECR_QB_PH_MMR2 |
6460 |
4U, // PRECR_QB_PH_MMR2 |
| 6461 |
12U, // PRECR_SRA_PH_W |
6461 |
12U, // PRECR_SRA_PH_W |
| 6462 |
12U, // PRECR_SRA_PH_W_MMR2 |
6462 |
12U, // PRECR_SRA_PH_W_MMR2 |
| 6463 |
12U, // PRECR_SRA_R_PH_W |
6463 |
12U, // PRECR_SRA_R_PH_W |
| 6464 |
12U, // PRECR_SRA_R_PH_W_MMR2 |
6464 |
12U, // PRECR_SRA_R_PH_W_MMR2 |
| 6465 |
0U, // PREF |
6465 |
0U, // PREF |
| 6466 |
0U, // PREFE |
6466 |
0U, // PREFE |
| 6467 |
0U, // PREFE_MM |
6467 |
0U, // PREFE_MM |
| 6468 |
0U, // PREFX_MM |
6468 |
0U, // PREFX_MM |
| 6469 |
0U, // PREF_MM |
6469 |
0U, // PREF_MM |
| 6470 |
0U, // PREF_MMR6 |
6470 |
0U, // PREF_MMR6 |
| 6471 |
0U, // PREF_R6 |
6471 |
0U, // PREF_R6 |
| 6472 |
12U, // PREPEND |
6472 |
12U, // PREPEND |
| 6473 |
12U, // PREPEND_MMR2 |
6473 |
12U, // PREPEND_MMR2 |
| 6474 |
4U, // PUL_PS64 |
6474 |
4U, // PUL_PS64 |
| 6475 |
4U, // PUU_PS64 |
6475 |
4U, // PUU_PS64 |
| 6476 |
0U, // RADDU_W_QB |
6476 |
0U, // RADDU_W_QB |
| 6477 |
0U, // RADDU_W_QB_MM |
6477 |
0U, // RADDU_W_QB_MM |
| 6478 |
0U, // RDDSP |
6478 |
0U, // RDDSP |
| 6479 |
0U, // RDDSP_MM |
6479 |
0U, // RDDSP_MM |
| 6480 |
16U, // RDHWR |
6480 |
16U, // RDHWR |
| 6481 |
16U, // RDHWR64 |
6481 |
16U, // RDHWR64 |
| 6482 |
16U, // RDHWR_MM |
6482 |
16U, // RDHWR_MM |
| 6483 |
8U, // RDHWR_MMR6 |
6483 |
8U, // RDHWR_MMR6 |
| 6484 |
0U, // RDPGPR_MMR6 |
6484 |
0U, // RDPGPR_MMR6 |
| 6485 |
0U, // RECIP_D32 |
6485 |
0U, // RECIP_D32 |
| 6486 |
0U, // RECIP_D32_MM |
6486 |
0U, // RECIP_D32_MM |
| 6487 |
0U, // RECIP_D64 |
6487 |
0U, // RECIP_D64 |
| 6488 |
0U, // RECIP_D64_MM |
6488 |
0U, // RECIP_D64_MM |
| 6489 |
0U, // RECIP_S |
6489 |
0U, // RECIP_S |
| 6490 |
0U, // RECIP_S_MM |
6490 |
0U, // RECIP_S_MM |
| 6491 |
0U, // REPLV_PH |
6491 |
0U, // REPLV_PH |
| 6492 |
0U, // REPLV_PH_MM |
6492 |
0U, // REPLV_PH_MM |
| 6493 |
0U, // REPLV_QB |
6493 |
0U, // REPLV_QB |
| 6494 |
0U, // REPLV_QB_MM |
6494 |
0U, // REPLV_QB_MM |
| 6495 |
0U, // REPL_PH |
6495 |
0U, // REPL_PH |
| 6496 |
0U, // REPL_PH_MM |
6496 |
0U, // REPL_PH_MM |
| 6497 |
0U, // REPL_QB |
6497 |
0U, // REPL_QB |
| 6498 |
0U, // REPL_QB_MM |
6498 |
0U, // REPL_QB_MM |
| 6499 |
0U, // RINT_D |
6499 |
0U, // RINT_D |
| 6500 |
0U, // RINT_D_MMR6 |
6500 |
0U, // RINT_D_MMR6 |
| 6501 |
0U, // RINT_S |
6501 |
0U, // RINT_S |
| 6502 |
0U, // RINT_S_MMR6 |
6502 |
0U, // RINT_S_MMR6 |
| 6503 |
12U, // ROTR |
6503 |
12U, // ROTR |
| 6504 |
4U, // ROTRV |
6504 |
4U, // ROTRV |
| 6505 |
4U, // ROTRV_MM |
6505 |
4U, // ROTRV_MM |
| 6506 |
12U, // ROTR_MM |
6506 |
12U, // ROTR_MM |
| 6507 |
0U, // ROUND_L_D64 |
6507 |
0U, // ROUND_L_D64 |
| 6508 |
0U, // ROUND_L_D_MMR6 |
6508 |
0U, // ROUND_L_D_MMR6 |
| 6509 |
0U, // ROUND_L_S |
6509 |
0U, // ROUND_L_S |
| 6510 |
0U, // ROUND_L_S_MMR6 |
6510 |
0U, // ROUND_L_S_MMR6 |
| 6511 |
0U, // ROUND_W_D32 |
6511 |
0U, // ROUND_W_D32 |
| 6512 |
0U, // ROUND_W_D64 |
6512 |
0U, // ROUND_W_D64 |
| 6513 |
0U, // ROUND_W_D_MMR6 |
6513 |
0U, // ROUND_W_D_MMR6 |
| 6514 |
0U, // ROUND_W_MM |
6514 |
0U, // ROUND_W_MM |
| 6515 |
0U, // ROUND_W_S |
6515 |
0U, // ROUND_W_S |
| 6516 |
0U, // ROUND_W_S_MM |
6516 |
0U, // ROUND_W_S_MM |
| 6517 |
0U, // ROUND_W_S_MMR6 |
6517 |
0U, // ROUND_W_S_MMR6 |
| 6518 |
0U, // RSQRT_D32 |
6518 |
0U, // RSQRT_D32 |
| 6519 |
0U, // RSQRT_D32_MM |
6519 |
0U, // RSQRT_D32_MM |
| 6520 |
0U, // RSQRT_D64 |
6520 |
0U, // RSQRT_D64 |
| 6521 |
0U, // RSQRT_D64_MM |
6521 |
0U, // RSQRT_D64_MM |
| 6522 |
0U, // RSQRT_S |
6522 |
0U, // RSQRT_S |
| 6523 |
0U, // RSQRT_S_MM |
6523 |
0U, // RSQRT_S_MM |
| 6524 |
0U, // Restore16 |
6524 |
0U, // Restore16 |
| 6525 |
0U, // RestoreX16 |
6525 |
0U, // RestoreX16 |
| 6526 |
0U, // SAA |
6526 |
0U, // SAA |
| 6527 |
0U, // SAAD |
6527 |
0U, // SAAD |
| 6528 |
8U, // SAT_S_B |
6528 |
8U, // SAT_S_B |
| 6529 |
28U, // SAT_S_D |
6529 |
28U, // SAT_S_D |
| 6530 |
32U, // SAT_S_H |
6530 |
32U, // SAT_S_H |
| 6531 |
12U, // SAT_S_W |
6531 |
12U, // SAT_S_W |
| 6532 |
8U, // SAT_U_B |
6532 |
8U, // SAT_U_B |
| 6533 |
28U, // SAT_U_D |
6533 |
28U, // SAT_U_D |
| 6534 |
32U, // SAT_U_H |
6534 |
32U, // SAT_U_H |
| 6535 |
12U, // SAT_U_W |
6535 |
12U, // SAT_U_W |
| 6536 |
0U, // SB |
6536 |
0U, // SB |
| 6537 |
0U, // SB16_MM |
6537 |
0U, // SB16_MM |
| 6538 |
0U, // SB16_MMR6 |
6538 |
0U, // SB16_MMR6 |
| 6539 |
0U, // SB64 |
6539 |
0U, // SB64 |
| 6540 |
0U, // SBE |
6540 |
0U, // SBE |
| 6541 |
0U, // SBE_MM |
6541 |
0U, // SBE_MM |
| 6542 |
0U, // SB_MM |
6542 |
0U, // SB_MM |
| 6543 |
0U, // SB_MMR6 |
6543 |
0U, // SB_MMR6 |
| 6544 |
0U, // SC |
6544 |
0U, // SC |
| 6545 |
0U, // SC64 |
6545 |
0U, // SC64 |
| 6546 |
0U, // SC64_R6 |
6546 |
0U, // SC64_R6 |
| 6547 |
0U, // SCD |
6547 |
0U, // SCD |
| 6548 |
0U, // SCD_R6 |
6548 |
0U, // SCD_R6 |
| 6549 |
0U, // SCE |
6549 |
0U, // SCE |
| 6550 |
0U, // SCE_MM |
6550 |
0U, // SCE_MM |
| 6551 |
0U, // SC_MM |
6551 |
0U, // SC_MM |
| 6552 |
0U, // SC_MMR6 |
6552 |
0U, // SC_MMR6 |
| 6553 |
0U, // SC_R6 |
6553 |
0U, // SC_R6 |
| 6554 |
0U, // SD |
6554 |
0U, // SD |
| 6555 |
0U, // SDBBP |
6555 |
0U, // SDBBP |
| 6556 |
0U, // SDBBP16_MM |
6556 |
0U, // SDBBP16_MM |
| 6557 |
0U, // SDBBP16_MMR6 |
6557 |
0U, // SDBBP16_MMR6 |
| 6558 |
0U, // SDBBP_MM |
6558 |
0U, // SDBBP_MM |
| 6559 |
0U, // SDBBP_MMR6 |
6559 |
0U, // SDBBP_MMR6 |
| 6560 |
0U, // SDBBP_R6 |
6560 |
0U, // SDBBP_R6 |
| 6561 |
0U, // SDC1 |
6561 |
0U, // SDC1 |
| 6562 |
0U, // SDC164 |
6562 |
0U, // SDC164 |
| 6563 |
0U, // SDC1_D64_MMR6 |
6563 |
0U, // SDC1_D64_MMR6 |
| 6564 |
0U, // SDC1_MM_D32 |
6564 |
0U, // SDC1_MM_D32 |
| 6565 |
0U, // SDC1_MM_D64 |
6565 |
0U, // SDC1_MM_D64 |
| 6566 |
0U, // SDC2 |
6566 |
0U, // SDC2 |
| 6567 |
0U, // SDC2_MMR6 |
6567 |
0U, // SDC2_MMR6 |
| 6568 |
0U, // SDC2_R6 |
6568 |
0U, // SDC2_R6 |
| 6569 |
0U, // SDC3 |
6569 |
0U, // SDC3 |
| 6570 |
0U, // SDIV |
6570 |
0U, // SDIV |
| 6571 |
0U, // SDIV_MM |
6571 |
0U, // SDIV_MM |
| 6572 |
0U, // SDL |
6572 |
0U, // SDL |
| 6573 |
0U, // SDR |
6573 |
0U, // SDR |
| 6574 |
1U, // SDXC1 |
6574 |
1U, // SDXC1 |
| 6575 |
1U, // SDXC164 |
6575 |
1U, // SDXC164 |
| 6576 |
0U, // SEB |
6576 |
0U, // SEB |
| 6577 |
0U, // SEB64 |
6577 |
0U, // SEB64 |
| 6578 |
0U, // SEB_MM |
6578 |
0U, // SEB_MM |
| 6579 |
0U, // SEH |
6579 |
0U, // SEH |
| 6580 |
0U, // SEH64 |
6580 |
0U, // SEH64 |
| 6581 |
0U, // SEH_MM |
6581 |
0U, // SEH_MM |
| 6582 |
4U, // SELEQZ |
6582 |
4U, // SELEQZ |
| 6583 |
4U, // SELEQZ64 |
6583 |
4U, // SELEQZ64 |
| 6584 |
4U, // SELEQZ_D |
6584 |
4U, // SELEQZ_D |
| 6585 |
4U, // SELEQZ_D_MMR6 |
6585 |
4U, // SELEQZ_D_MMR6 |
| 6586 |
4U, // SELEQZ_MMR6 |
6586 |
4U, // SELEQZ_MMR6 |
| 6587 |
4U, // SELEQZ_S |
6587 |
4U, // SELEQZ_S |
| 6588 |
4U, // SELEQZ_S_MMR6 |
6588 |
4U, // SELEQZ_S_MMR6 |
| 6589 |
4U, // SELNEZ |
6589 |
4U, // SELNEZ |
| 6590 |
4U, // SELNEZ64 |
6590 |
4U, // SELNEZ64 |
| 6591 |
4U, // SELNEZ_D |
6591 |
4U, // SELNEZ_D |
| 6592 |
4U, // SELNEZ_D_MMR6 |
6592 |
4U, // SELNEZ_D_MMR6 |
| 6593 |
4U, // SELNEZ_MMR6 |
6593 |
4U, // SELNEZ_MMR6 |
| 6594 |
4U, // SELNEZ_S |
6594 |
4U, // SELNEZ_S |
| 6595 |
4U, // SELNEZ_S_MMR6 |
6595 |
4U, // SELNEZ_S_MMR6 |
| 6596 |
52U, // SEL_D |
6596 |
52U, // SEL_D |
| 6597 |
52U, // SEL_D_MMR6 |
6597 |
52U, // SEL_D_MMR6 |
| 6598 |
52U, // SEL_S |
6598 |
52U, // SEL_S |
| 6599 |
52U, // SEL_S_MMR6 |
6599 |
52U, // SEL_S_MMR6 |
| 6600 |
4U, // SEQ |
6600 |
4U, // SEQ |
| 6601 |
4U, // SEQi |
6601 |
4U, // SEQi |
| 6602 |
0U, // SH |
6602 |
0U, // SH |
| 6603 |
0U, // SH16_MM |
6603 |
0U, // SH16_MM |
| 6604 |
0U, // SH16_MMR6 |
6604 |
0U, // SH16_MMR6 |
| 6605 |
0U, // SH64 |
6605 |
0U, // SH64 |
| 6606 |
0U, // SHE |
6606 |
0U, // SHE |
| 6607 |
0U, // SHE_MM |
6607 |
0U, // SHE_MM |
| 6608 |
16U, // SHF_B |
6608 |
16U, // SHF_B |
| 6609 |
16U, // SHF_H |
6609 |
16U, // SHF_H |
| 6610 |
16U, // SHF_W |
6610 |
16U, // SHF_W |
| 6611 |
0U, // SHILO |
6611 |
0U, // SHILO |
| 6612 |
0U, // SHILOV |
6612 |
0U, // SHILOV |
| 6613 |
0U, // SHILOV_MM |
6613 |
0U, // SHILOV_MM |
| 6614 |
0U, // SHILO_MM |
6614 |
0U, // SHILO_MM |
| 6615 |
4U, // SHLLV_PH |
6615 |
4U, // SHLLV_PH |
| 6616 |
4U, // SHLLV_PH_MM |
6616 |
4U, // SHLLV_PH_MM |
| 6617 |
4U, // SHLLV_QB |
6617 |
4U, // SHLLV_QB |
| 6618 |
4U, // SHLLV_QB_MM |
6618 |
4U, // SHLLV_QB_MM |
| 6619 |
4U, // SHLLV_S_PH |
6619 |
4U, // SHLLV_S_PH |
| 6620 |
4U, // SHLLV_S_PH_MM |
6620 |
4U, // SHLLV_S_PH_MM |
| 6621 |
4U, // SHLLV_S_W |
6621 |
4U, // SHLLV_S_W |
| 6622 |
4U, // SHLLV_S_W_MM |
6622 |
4U, // SHLLV_S_W_MM |
| 6623 |
32U, // SHLL_PH |
6623 |
32U, // SHLL_PH |
| 6624 |
32U, // SHLL_PH_MM |
6624 |
32U, // SHLL_PH_MM |
| 6625 |
8U, // SHLL_QB |
6625 |
8U, // SHLL_QB |
| 6626 |
8U, // SHLL_QB_MM |
6626 |
8U, // SHLL_QB_MM |
| 6627 |
32U, // SHLL_S_PH |
6627 |
32U, // SHLL_S_PH |
| 6628 |
32U, // SHLL_S_PH_MM |
6628 |
32U, // SHLL_S_PH_MM |
| 6629 |
12U, // SHLL_S_W |
6629 |
12U, // SHLL_S_W |
| 6630 |
12U, // SHLL_S_W_MM |
6630 |
12U, // SHLL_S_W_MM |
| 6631 |
4U, // SHRAV_PH |
6631 |
4U, // SHRAV_PH |
| 6632 |
4U, // SHRAV_PH_MM |
6632 |
4U, // SHRAV_PH_MM |
| 6633 |
4U, // SHRAV_QB |
6633 |
4U, // SHRAV_QB |
| 6634 |
4U, // SHRAV_QB_MMR2 |
6634 |
4U, // SHRAV_QB_MMR2 |
| 6635 |
4U, // SHRAV_R_PH |
6635 |
4U, // SHRAV_R_PH |
| 6636 |
4U, // SHRAV_R_PH_MM |
6636 |
4U, // SHRAV_R_PH_MM |
| 6637 |
4U, // SHRAV_R_QB |
6637 |
4U, // SHRAV_R_QB |
| 6638 |
4U, // SHRAV_R_QB_MMR2 |
6638 |
4U, // SHRAV_R_QB_MMR2 |
| 6639 |
4U, // SHRAV_R_W |
6639 |
4U, // SHRAV_R_W |
| 6640 |
4U, // SHRAV_R_W_MM |
6640 |
4U, // SHRAV_R_W_MM |
| 6641 |
32U, // SHRA_PH |
6641 |
32U, // SHRA_PH |
| 6642 |
32U, // SHRA_PH_MM |
6642 |
32U, // SHRA_PH_MM |
| 6643 |
8U, // SHRA_QB |
6643 |
8U, // SHRA_QB |
| 6644 |
8U, // SHRA_QB_MMR2 |
6644 |
8U, // SHRA_QB_MMR2 |
| 6645 |
32U, // SHRA_R_PH |
6645 |
32U, // SHRA_R_PH |
| 6646 |
32U, // SHRA_R_PH_MM |
6646 |
32U, // SHRA_R_PH_MM |
| 6647 |
8U, // SHRA_R_QB |
6647 |
8U, // SHRA_R_QB |
| 6648 |
8U, // SHRA_R_QB_MMR2 |
6648 |
8U, // SHRA_R_QB_MMR2 |
| 6649 |
12U, // SHRA_R_W |
6649 |
12U, // SHRA_R_W |
| 6650 |
12U, // SHRA_R_W_MM |
6650 |
12U, // SHRA_R_W_MM |
| 6651 |
4U, // SHRLV_PH |
6651 |
4U, // SHRLV_PH |
| 6652 |
4U, // SHRLV_PH_MMR2 |
6652 |
4U, // SHRLV_PH_MMR2 |
| 6653 |
4U, // SHRLV_QB |
6653 |
4U, // SHRLV_QB |
| 6654 |
4U, // SHRLV_QB_MM |
6654 |
4U, // SHRLV_QB_MM |
| 6655 |
32U, // SHRL_PH |
6655 |
32U, // SHRL_PH |
| 6656 |
32U, // SHRL_PH_MMR2 |
6656 |
32U, // SHRL_PH_MMR2 |
| 6657 |
8U, // SHRL_QB |
6657 |
8U, // SHRL_QB |
| 6658 |
8U, // SHRL_QB_MM |
6658 |
8U, // SHRL_QB_MM |
| 6659 |
0U, // SH_MM |
6659 |
0U, // SH_MM |
| 6660 |
0U, // SH_MMR6 |
6660 |
0U, // SH_MMR6 |
| 6661 |
0U, // SIGRIE |
6661 |
0U, // SIGRIE |
| 6662 |
0U, // SIGRIE_MMR6 |
6662 |
0U, // SIGRIE_MMR6 |
| 6663 |
301U, // SLDI_B |
6663 |
301U, // SLDI_B |
| 6664 |
73U, // SLDI_D |
6664 |
73U, // SLDI_D |
| 6665 |
293U, // SLDI_H |
6665 |
293U, // SLDI_H |
| 6666 |
77U, // SLDI_W |
6666 |
77U, // SLDI_W |
| 6667 |
309U, // SLD_B |
6667 |
309U, // SLD_B |
| 6668 |
309U, // SLD_D |
6668 |
309U, // SLD_D |
| 6669 |
309U, // SLD_H |
6669 |
309U, // SLD_H |
| 6670 |
309U, // SLD_W |
6670 |
309U, // SLD_W |
| 6671 |
12U, // SLL |
6671 |
12U, // SLL |
| 6672 |
4U, // SLL16_MM |
6672 |
4U, // SLL16_MM |
| 6673 |
4U, // SLL16_MMR6 |
6673 |
4U, // SLL16_MMR6 |
| 6674 |
2U, // SLL64_32 |
6674 |
2U, // SLL64_32 |
| 6675 |
2U, // SLL64_64 |
6675 |
2U, // SLL64_64 |
| 6676 |
8U, // SLLI_B |
6676 |
8U, // SLLI_B |
| 6677 |
28U, // SLLI_D |
6677 |
28U, // SLLI_D |
| 6678 |
32U, // SLLI_H |
6678 |
32U, // SLLI_H |
| 6679 |
12U, // SLLI_W |
6679 |
12U, // SLLI_W |
| 6680 |
4U, // SLLV |
6680 |
4U, // SLLV |
| 6681 |
4U, // SLLV_MM |
6681 |
4U, // SLLV_MM |
| 6682 |
4U, // SLL_B |
6682 |
4U, // SLL_B |
| 6683 |
4U, // SLL_D |
6683 |
4U, // SLL_D |
| 6684 |
4U, // SLL_H |
6684 |
4U, // SLL_H |
| 6685 |
12U, // SLL_MM |
6685 |
12U, // SLL_MM |
| 6686 |
12U, // SLL_MMR6 |
6686 |
12U, // SLL_MMR6 |
| 6687 |
4U, // SLL_W |
6687 |
4U, // SLL_W |
| 6688 |
4U, // SLT |
6688 |
4U, // SLT |
| 6689 |
4U, // SLT64 |
6689 |
4U, // SLT64 |
| 6690 |
4U, // SLT_MM |
6690 |
4U, // SLT_MM |
| 6691 |
4U, // SLTi |
6691 |
4U, // SLTi |
| 6692 |
4U, // SLTi64 |
6692 |
4U, // SLTi64 |
| 6693 |
4U, // SLTi_MM |
6693 |
4U, // SLTi_MM |
| 6694 |
4U, // SLTiu |
6694 |
4U, // SLTiu |
| 6695 |
4U, // SLTiu64 |
6695 |
4U, // SLTiu64 |
| 6696 |
4U, // SLTiu_MM |
6696 |
4U, // SLTiu_MM |
| 6697 |
4U, // SLTu |
6697 |
4U, // SLTu |
| 6698 |
4U, // SLTu64 |
6698 |
4U, // SLTu64 |
| 6699 |
4U, // SLTu_MM |
6699 |
4U, // SLTu_MM |
| 6700 |
4U, // SNE |
6700 |
4U, // SNE |
| 6701 |
4U, // SNEi |
6701 |
4U, // SNEi |
| 6702 |
289U, // SPLATI_B |
6702 |
289U, // SPLATI_B |
| 6703 |
317U, // SPLATI_D |
6703 |
317U, // SPLATI_D |
| 6704 |
265U, // SPLATI_H |
6704 |
265U, // SPLATI_H |
| 6705 |
281U, // SPLATI_W |
6705 |
281U, // SPLATI_W |
| 6706 |
261U, // SPLAT_B |
6706 |
261U, // SPLAT_B |
| 6707 |
261U, // SPLAT_D |
6707 |
261U, // SPLAT_D |
| 6708 |
261U, // SPLAT_H |
6708 |
261U, // SPLAT_H |
| 6709 |
261U, // SPLAT_W |
6709 |
261U, // SPLAT_W |
| 6710 |
12U, // SRA |
6710 |
12U, // SRA |
| 6711 |
8U, // SRAI_B |
6711 |
8U, // SRAI_B |
| 6712 |
28U, // SRAI_D |
6712 |
28U, // SRAI_D |
| 6713 |
32U, // SRAI_H |
6713 |
32U, // SRAI_H |
| 6714 |
12U, // SRAI_W |
6714 |
12U, // SRAI_W |
| 6715 |
8U, // SRARI_B |
6715 |
8U, // SRARI_B |
| 6716 |
28U, // SRARI_D |
6716 |
28U, // SRARI_D |
| 6717 |
32U, // SRARI_H |
6717 |
32U, // SRARI_H |
| 6718 |
12U, // SRARI_W |
6718 |
12U, // SRARI_W |
| 6719 |
4U, // SRAR_B |
6719 |
4U, // SRAR_B |
| 6720 |
4U, // SRAR_D |
6720 |
4U, // SRAR_D |
| 6721 |
4U, // SRAR_H |
6721 |
4U, // SRAR_H |
| 6722 |
4U, // SRAR_W |
6722 |
4U, // SRAR_W |
| 6723 |
4U, // SRAV |
6723 |
4U, // SRAV |
| 6724 |
4U, // SRAV_MM |
6724 |
4U, // SRAV_MM |
| 6725 |
4U, // SRA_B |
6725 |
4U, // SRA_B |
| 6726 |
4U, // SRA_D |
6726 |
4U, // SRA_D |
| 6727 |
4U, // SRA_H |
6727 |
4U, // SRA_H |
| 6728 |
12U, // SRA_MM |
6728 |
12U, // SRA_MM |
| 6729 |
4U, // SRA_W |
6729 |
4U, // SRA_W |
| 6730 |
12U, // SRL |
6730 |
12U, // SRL |
| 6731 |
4U, // SRL16_MM |
6731 |
4U, // SRL16_MM |
| 6732 |
4U, // SRL16_MMR6 |
6732 |
4U, // SRL16_MMR6 |
| 6733 |
8U, // SRLI_B |
6733 |
8U, // SRLI_B |
| 6734 |
28U, // SRLI_D |
6734 |
28U, // SRLI_D |
| 6735 |
32U, // SRLI_H |
6735 |
32U, // SRLI_H |
| 6736 |
12U, // SRLI_W |
6736 |
12U, // SRLI_W |
| 6737 |
8U, // SRLRI_B |
6737 |
8U, // SRLRI_B |
| 6738 |
28U, // SRLRI_D |
6738 |
28U, // SRLRI_D |
| 6739 |
32U, // SRLRI_H |
6739 |
32U, // SRLRI_H |
| 6740 |
12U, // SRLRI_W |
6740 |
12U, // SRLRI_W |
| 6741 |
4U, // SRLR_B |
6741 |
4U, // SRLR_B |
| 6742 |
4U, // SRLR_D |
6742 |
4U, // SRLR_D |
| 6743 |
4U, // SRLR_H |
6743 |
4U, // SRLR_H |
| 6744 |
4U, // SRLR_W |
6744 |
4U, // SRLR_W |
| 6745 |
4U, // SRLV |
6745 |
4U, // SRLV |
| 6746 |
4U, // SRLV_MM |
6746 |
4U, // SRLV_MM |
| 6747 |
4U, // SRL_B |
6747 |
4U, // SRL_B |
| 6748 |
4U, // SRL_D |
6748 |
4U, // SRL_D |
| 6749 |
4U, // SRL_H |
6749 |
4U, // SRL_H |
| 6750 |
12U, // SRL_MM |
6750 |
12U, // SRL_MM |
| 6751 |
4U, // SRL_W |
6751 |
4U, // SRL_W |
| 6752 |
0U, // SSNOP |
6752 |
0U, // SSNOP |
| 6753 |
0U, // SSNOP_MM |
6753 |
0U, // SSNOP_MM |
| 6754 |
0U, // SSNOP_MMR6 |
6754 |
0U, // SSNOP_MMR6 |
| 6755 |
0U, // ST_B |
6755 |
0U, // ST_B |
| 6756 |
0U, // ST_D |
6756 |
0U, // ST_D |
| 6757 |
0U, // ST_H |
6757 |
0U, // ST_H |
| 6758 |
0U, // ST_W |
6758 |
0U, // ST_W |
| 6759 |
4U, // SUB |
6759 |
4U, // SUB |
| 6760 |
4U, // SUBQH_PH |
6760 |
4U, // SUBQH_PH |
| 6761 |
4U, // SUBQH_PH_MMR2 |
6761 |
4U, // SUBQH_PH_MMR2 |
| 6762 |
4U, // SUBQH_R_PH |
6762 |
4U, // SUBQH_R_PH |
| 6763 |
4U, // SUBQH_R_PH_MMR2 |
6763 |
4U, // SUBQH_R_PH_MMR2 |
| 6764 |
4U, // SUBQH_R_W |
6764 |
4U, // SUBQH_R_W |
| 6765 |
4U, // SUBQH_R_W_MMR2 |
6765 |
4U, // SUBQH_R_W_MMR2 |
| 6766 |
4U, // SUBQH_W |
6766 |
4U, // SUBQH_W |
| 6767 |
4U, // SUBQH_W_MMR2 |
6767 |
4U, // SUBQH_W_MMR2 |
| 6768 |
4U, // SUBQ_PH |
6768 |
4U, // SUBQ_PH |
| 6769 |
4U, // SUBQ_PH_MM |
6769 |
4U, // SUBQ_PH_MM |
| 6770 |
4U, // SUBQ_S_PH |
6770 |
4U, // SUBQ_S_PH |
| 6771 |
4U, // SUBQ_S_PH_MM |
6771 |
4U, // SUBQ_S_PH_MM |
| 6772 |
4U, // SUBQ_S_W |
6772 |
4U, // SUBQ_S_W |
| 6773 |
4U, // SUBQ_S_W_MM |
6773 |
4U, // SUBQ_S_W_MM |
| 6774 |
4U, // SUBSUS_U_B |
6774 |
4U, // SUBSUS_U_B |
| 6775 |
4U, // SUBSUS_U_D |
6775 |
4U, // SUBSUS_U_D |
| 6776 |
4U, // SUBSUS_U_H |
6776 |
4U, // SUBSUS_U_H |
| 6777 |
4U, // SUBSUS_U_W |
6777 |
4U, // SUBSUS_U_W |
| 6778 |
4U, // SUBSUU_S_B |
6778 |
4U, // SUBSUU_S_B |
| 6779 |
4U, // SUBSUU_S_D |
6779 |
4U, // SUBSUU_S_D |
| 6780 |
4U, // SUBSUU_S_H |
6780 |
4U, // SUBSUU_S_H |
| 6781 |
4U, // SUBSUU_S_W |
6781 |
4U, // SUBSUU_S_W |
| 6782 |
4U, // SUBS_S_B |
6782 |
4U, // SUBS_S_B |
| 6783 |
4U, // SUBS_S_D |
6783 |
4U, // SUBS_S_D |
| 6784 |
4U, // SUBS_S_H |
6784 |
4U, // SUBS_S_H |
| 6785 |
4U, // SUBS_S_W |
6785 |
4U, // SUBS_S_W |
| 6786 |
4U, // SUBS_U_B |
6786 |
4U, // SUBS_U_B |
| 6787 |
4U, // SUBS_U_D |
6787 |
4U, // SUBS_U_D |
| 6788 |
4U, // SUBS_U_H |
6788 |
4U, // SUBS_U_H |
| 6789 |
4U, // SUBS_U_W |
6789 |
4U, // SUBS_U_W |
| 6790 |
4U, // SUBU16_MM |
6790 |
4U, // SUBU16_MM |
| 6791 |
4U, // SUBU16_MMR6 |
6791 |
4U, // SUBU16_MMR6 |
| 6792 |
4U, // SUBUH_QB |
6792 |
4U, // SUBUH_QB |
| 6793 |
4U, // SUBUH_QB_MMR2 |
6793 |
4U, // SUBUH_QB_MMR2 |
| 6794 |
4U, // SUBUH_R_QB |
6794 |
4U, // SUBUH_R_QB |
| 6795 |
4U, // SUBUH_R_QB_MMR2 |
6795 |
4U, // SUBUH_R_QB_MMR2 |
| 6796 |
4U, // SUBU_MMR6 |
6796 |
4U, // SUBU_MMR6 |
| 6797 |
4U, // SUBU_PH |
6797 |
4U, // SUBU_PH |
| 6798 |
4U, // SUBU_PH_MMR2 |
6798 |
4U, // SUBU_PH_MMR2 |
| 6799 |
4U, // SUBU_QB |
6799 |
4U, // SUBU_QB |
| 6800 |
4U, // SUBU_QB_MM |
6800 |
4U, // SUBU_QB_MM |
| 6801 |
4U, // SUBU_S_PH |
6801 |
4U, // SUBU_S_PH |
| 6802 |
4U, // SUBU_S_PH_MMR2 |
6802 |
4U, // SUBU_S_PH_MMR2 |
| 6803 |
4U, // SUBU_S_QB |
6803 |
4U, // SUBU_S_QB |
| 6804 |
4U, // SUBU_S_QB_MM |
6804 |
4U, // SUBU_S_QB_MM |
| 6805 |
12U, // SUBVI_B |
6805 |
12U, // SUBVI_B |
| 6806 |
12U, // SUBVI_D |
6806 |
12U, // SUBVI_D |
| 6807 |
12U, // SUBVI_H |
6807 |
12U, // SUBVI_H |
| 6808 |
12U, // SUBVI_W |
6808 |
12U, // SUBVI_W |
| 6809 |
4U, // SUBV_B |
6809 |
4U, // SUBV_B |
| 6810 |
4U, // SUBV_D |
6810 |
4U, // SUBV_D |
| 6811 |
4U, // SUBV_H |
6811 |
4U, // SUBV_H |
| 6812 |
4U, // SUBV_W |
6812 |
4U, // SUBV_W |
| 6813 |
4U, // SUB_MM |
6813 |
4U, // SUB_MM |
| 6814 |
4U, // SUB_MMR6 |
6814 |
4U, // SUB_MMR6 |
| 6815 |
4U, // SUBu |
6815 |
4U, // SUBu |
| 6816 |
4U, // SUBu_MM |
6816 |
4U, // SUBu_MM |
| 6817 |
1U, // SUXC1 |
6817 |
1U, // SUXC1 |
| 6818 |
1U, // SUXC164 |
6818 |
1U, // SUXC164 |
| 6819 |
1U, // SUXC1_MM |
6819 |
1U, // SUXC1_MM |
| 6820 |
0U, // SW |
6820 |
0U, // SW |
| 6821 |
0U, // SW16_MM |
6821 |
0U, // SW16_MM |
| 6822 |
0U, // SW16_MMR6 |
6822 |
0U, // SW16_MMR6 |
| 6823 |
0U, // SW64 |
6823 |
0U, // SW64 |
| 6824 |
0U, // SWC1 |
6824 |
0U, // SWC1 |
| 6825 |
0U, // SWC1_MM |
6825 |
0U, // SWC1_MM |
| 6826 |
0U, // SWC2 |
6826 |
0U, // SWC2 |
| 6827 |
0U, // SWC2_MMR6 |
6827 |
0U, // SWC2_MMR6 |
| 6828 |
0U, // SWC2_R6 |
6828 |
0U, // SWC2_R6 |
| 6829 |
0U, // SWC3 |
6829 |
0U, // SWC3 |
| 6830 |
0U, // SWDSP |
6830 |
0U, // SWDSP |
| 6831 |
0U, // SWDSP_MM |
6831 |
0U, // SWDSP_MM |
| 6832 |
0U, // SWE |
6832 |
0U, // SWE |
| 6833 |
0U, // SWE_MM |
6833 |
0U, // SWE_MM |
| 6834 |
0U, // SWL |
6834 |
0U, // SWL |
| 6835 |
0U, // SWL64 |
6835 |
0U, // SWL64 |
| 6836 |
0U, // SWLE |
6836 |
0U, // SWLE |
| 6837 |
0U, // SWLE_MM |
6837 |
0U, // SWLE_MM |
| 6838 |
0U, // SWL_MM |
6838 |
0U, // SWL_MM |
| 6839 |
0U, // SWM16_MM |
6839 |
0U, // SWM16_MM |
| 6840 |
0U, // SWM16_MMR6 |
6840 |
0U, // SWM16_MMR6 |
| 6841 |
0U, // SWM32_MM |
6841 |
0U, // SWM32_MM |
| 6842 |
0U, // SWP_MM |
6842 |
0U, // SWP_MM |
| 6843 |
0U, // SWR |
6843 |
0U, // SWR |
| 6844 |
0U, // SWR64 |
6844 |
0U, // SWR64 |
| 6845 |
0U, // SWRE |
6845 |
0U, // SWRE |
| 6846 |
0U, // SWRE_MM |
6846 |
0U, // SWRE_MM |
| 6847 |
0U, // SWR_MM |
6847 |
0U, // SWR_MM |
| 6848 |
0U, // SWSP_MM |
6848 |
0U, // SWSP_MM |
| 6849 |
0U, // SWSP_MMR6 |
6849 |
0U, // SWSP_MMR6 |
| 6850 |
1U, // SWXC1 |
6850 |
1U, // SWXC1 |
| 6851 |
1U, // SWXC1_MM |
6851 |
1U, // SWXC1_MM |
| 6852 |
0U, // SW_MM |
6852 |
0U, // SW_MM |
| 6853 |
0U, // SW_MMR6 |
6853 |
0U, // SW_MMR6 |
| 6854 |
0U, // SYNC |
6854 |
0U, // SYNC |
| 6855 |
0U, // SYNCI |
6855 |
0U, // SYNCI |
| 6856 |
0U, // SYNCI_MM |
6856 |
0U, // SYNCI_MM |
| 6857 |
0U, // SYNCI_MMR6 |
6857 |
0U, // SYNCI_MMR6 |
| 6858 |
0U, // SYNC_MM |
6858 |
0U, // SYNC_MM |
| 6859 |
0U, // SYNC_MMR6 |
6859 |
0U, // SYNC_MMR6 |
| 6860 |
0U, // SYSCALL |
6860 |
0U, // SYSCALL |
| 6861 |
0U, // SYSCALL_MM |
6861 |
0U, // SYSCALL_MM |
| 6862 |
0U, // Save16 |
6862 |
0U, // Save16 |
| 6863 |
0U, // SaveX16 |
6863 |
0U, // SaveX16 |
| 6864 |
0U, // SbRxRyOffMemX16 |
6864 |
0U, // SbRxRyOffMemX16 |
| 6865 |
0U, // SebRx16 |
6865 |
0U, // SebRx16 |
| 6866 |
0U, // SehRx16 |
6866 |
0U, // SehRx16 |
| 6867 |
0U, // ShRxRyOffMemX16 |
6867 |
0U, // ShRxRyOffMemX16 |
| 6868 |
12U, // SllX16 |
6868 |
12U, // SllX16 |
| 6869 |
0U, // SllvRxRy16 |
6869 |
0U, // SllvRxRy16 |
| 6870 |
0U, // SltRxRy16 |
6870 |
0U, // SltRxRy16 |
| 6871 |
1U, // SltiRxImm16 |
6871 |
1U, // SltiRxImm16 |
| 6872 |
0U, // SltiRxImmX16 |
6872 |
0U, // SltiRxImmX16 |
| 6873 |
1U, // SltiuRxImm16 |
6873 |
1U, // SltiuRxImm16 |
| 6874 |
0U, // SltiuRxImmX16 |
6874 |
0U, // SltiuRxImmX16 |
| 6875 |
0U, // SltuRxRy16 |
6875 |
0U, // SltuRxRy16 |
| 6876 |
12U, // SraX16 |
6876 |
12U, // SraX16 |
| 6877 |
0U, // SravRxRy16 |
6877 |
0U, // SravRxRy16 |
| 6878 |
12U, // SrlX16 |
6878 |
12U, // SrlX16 |
| 6879 |
0U, // SrlvRxRy16 |
6879 |
0U, // SrlvRxRy16 |
| 6880 |
4U, // SubuRxRyRz16 |
6880 |
4U, // SubuRxRyRz16 |
| 6881 |
0U, // SwRxRyOffMemX16 |
6881 |
0U, // SwRxRyOffMemX16 |
| 6882 |
0U, // SwRxSpImmX16 |
6882 |
0U, // SwRxSpImmX16 |
| 6883 |
80U, // TEQ |
6883 |
80U, // TEQ |
| 6884 |
0U, // TEQI |
6884 |
0U, // TEQI |
| 6885 |
0U, // TEQI_MM |
6885 |
0U, // TEQI_MM |
| 6886 |
32U, // TEQ_MM |
6886 |
32U, // TEQ_MM |
| 6887 |
80U, // TGE |
6887 |
80U, // TGE |
| 6888 |
0U, // TGEI |
6888 |
0U, // TGEI |
| 6889 |
0U, // TGEIU |
6889 |
0U, // TGEIU |
| 6890 |
0U, // TGEIU_MM |
6890 |
0U, // TGEIU_MM |
| 6891 |
0U, // TGEI_MM |
6891 |
0U, // TGEI_MM |
| 6892 |
80U, // TGEU |
6892 |
80U, // TGEU |
| 6893 |
32U, // TGEU_MM |
6893 |
32U, // TGEU_MM |
| 6894 |
32U, // TGE_MM |
6894 |
32U, // TGE_MM |
| 6895 |
0U, // TLBGINV |
6895 |
0U, // TLBGINV |
| 6896 |
0U, // TLBGINVF |
6896 |
0U, // TLBGINVF |
| 6897 |
0U, // TLBGINVF_MM |
6897 |
0U, // TLBGINVF_MM |
| 6898 |
0U, // TLBGINV_MM |
6898 |
0U, // TLBGINV_MM |
| 6899 |
0U, // TLBGP |
6899 |
0U, // TLBGP |
| 6900 |
0U, // TLBGP_MM |
6900 |
0U, // TLBGP_MM |
| 6901 |
0U, // TLBGR |
6901 |
0U, // TLBGR |
| 6902 |
0U, // TLBGR_MM |
6902 |
0U, // TLBGR_MM |
| 6903 |
0U, // TLBGWI |
6903 |
0U, // TLBGWI |
| 6904 |
0U, // TLBGWI_MM |
6904 |
0U, // TLBGWI_MM |
| 6905 |
0U, // TLBGWR |
6905 |
0U, // TLBGWR |
| 6906 |
0U, // TLBGWR_MM |
6906 |
0U, // TLBGWR_MM |
| 6907 |
0U, // TLBINV |
6907 |
0U, // TLBINV |
| 6908 |
0U, // TLBINVF |
6908 |
0U, // TLBINVF |
| 6909 |
0U, // TLBINVF_MMR6 |
6909 |
0U, // TLBINVF_MMR6 |
| 6910 |
0U, // TLBINV_MMR6 |
6910 |
0U, // TLBINV_MMR6 |
| 6911 |
0U, // TLBP |
6911 |
0U, // TLBP |
| 6912 |
0U, // TLBP_MM |
6912 |
0U, // TLBP_MM |
| 6913 |
0U, // TLBR |
6913 |
0U, // TLBR |
| 6914 |
0U, // TLBR_MM |
6914 |
0U, // TLBR_MM |
| 6915 |
0U, // TLBWI |
6915 |
0U, // TLBWI |
| 6916 |
0U, // TLBWI_MM |
6916 |
0U, // TLBWI_MM |
| 6917 |
0U, // TLBWR |
6917 |
0U, // TLBWR |
| 6918 |
0U, // TLBWR_MM |
6918 |
0U, // TLBWR_MM |
| 6919 |
80U, // TLT |
6919 |
80U, // TLT |
| 6920 |
0U, // TLTI |
6920 |
0U, // TLTI |
| 6921 |
0U, // TLTIU_MM |
6921 |
0U, // TLTIU_MM |
| 6922 |
0U, // TLTI_MM |
6922 |
0U, // TLTI_MM |
| 6923 |
80U, // TLTU |
6923 |
80U, // TLTU |
| 6924 |
32U, // TLTU_MM |
6924 |
32U, // TLTU_MM |
| 6925 |
32U, // TLT_MM |
6925 |
32U, // TLT_MM |
| 6926 |
80U, // TNE |
6926 |
80U, // TNE |
| 6927 |
0U, // TNEI |
6927 |
0U, // TNEI |
| 6928 |
0U, // TNEI_MM |
6928 |
0U, // TNEI_MM |
| 6929 |
32U, // TNE_MM |
6929 |
32U, // TNE_MM |
| 6930 |
0U, // TRUNC_L_D64 |
6930 |
0U, // TRUNC_L_D64 |
| 6931 |
0U, // TRUNC_L_D_MMR6 |
6931 |
0U, // TRUNC_L_D_MMR6 |
| 6932 |
0U, // TRUNC_L_S |
6932 |
0U, // TRUNC_L_S |
| 6933 |
0U, // TRUNC_L_S_MMR6 |
6933 |
0U, // TRUNC_L_S_MMR6 |
| 6934 |
0U, // TRUNC_W_D32 |
6934 |
0U, // TRUNC_W_D32 |
| 6935 |
0U, // TRUNC_W_D64 |
6935 |
0U, // TRUNC_W_D64 |
| 6936 |
0U, // TRUNC_W_D_MMR6 |
6936 |
0U, // TRUNC_W_D_MMR6 |
| 6937 |
0U, // TRUNC_W_MM |
6937 |
0U, // TRUNC_W_MM |
| 6938 |
0U, // TRUNC_W_S |
6938 |
0U, // TRUNC_W_S |
| 6939 |
0U, // TRUNC_W_S_MM |
6939 |
0U, // TRUNC_W_S_MM |
| 6940 |
0U, // TRUNC_W_S_MMR6 |
6940 |
0U, // TRUNC_W_S_MMR6 |
| 6941 |
0U, // TTLTIU |
6941 |
0U, // TTLTIU |
| 6942 |
0U, // UDIV |
6942 |
0U, // UDIV |
| 6943 |
0U, // UDIV_MM |
6943 |
0U, // UDIV_MM |
| 6944 |
4U, // V3MULU |
6944 |
4U, // V3MULU |
| 6945 |
4U, // VMM0 |
6945 |
4U, // VMM0 |
| 6946 |
4U, // VMULU |
6946 |
4U, // VMULU |
| 6947 |
52U, // VSHF_B |
6947 |
52U, // VSHF_B |
| 6948 |
52U, // VSHF_D |
6948 |
52U, // VSHF_D |
| 6949 |
52U, // VSHF_H |
6949 |
52U, // VSHF_H |
| 6950 |
52U, // VSHF_W |
6950 |
52U, // VSHF_W |
| 6951 |
0U, // WAIT |
6951 |
0U, // WAIT |
| 6952 |
0U, // WAIT_MM |
6952 |
0U, // WAIT_MM |
| 6953 |
0U, // WAIT_MMR6 |
6953 |
0U, // WAIT_MMR6 |
| 6954 |
0U, // WRDSP |
6954 |
0U, // WRDSP |
| 6955 |
0U, // WRDSP_MM |
6955 |
0U, // WRDSP_MM |
| 6956 |
0U, // WRPGPR_MMR6 |
6956 |
0U, // WRPGPR_MMR6 |
| 6957 |
0U, // WSBH |
6957 |
0U, // WSBH |
| 6958 |
0U, // WSBH_MM |
6958 |
0U, // WSBH_MM |
| 6959 |
0U, // WSBH_MMR6 |
6959 |
0U, // WSBH_MMR6 |
| 6960 |
4U, // XOR |
6960 |
4U, // XOR |
| 6961 |
0U, // XOR16_MM |
6961 |
0U, // XOR16_MM |
| 6962 |
0U, // XOR16_MMR6 |
6962 |
0U, // XOR16_MMR6 |
| 6963 |
4U, // XOR64 |
6963 |
4U, // XOR64 |
| 6964 |
16U, // XORI_B |
6964 |
16U, // XORI_B |
| 6965 |
20U, // XORI_MMR6 |
6965 |
20U, // XORI_MMR6 |
| 6966 |
4U, // XOR_MM |
6966 |
4U, // XOR_MM |
| 6967 |
4U, // XOR_MMR6 |
6967 |
4U, // XOR_MMR6 |
| 6968 |
4U, // XOR_V |
6968 |
4U, // XOR_V |
| 6969 |
20U, // XORi |
6969 |
20U, // XORi |
| 6970 |
20U, // XORi64 |
6970 |
20U, // XORi64 |
| 6971 |
20U, // XORi_MM |
6971 |
20U, // XORi_MM |
| 6972 |
0U, // XorRxRxRy16 |
6972 |
0U, // XorRxRxRy16 |
| 6973 |
0U, // YIELD |
6973 |
0U, // YIELD |
| 6974 |
}; |
6974 |
}; |
| 6975 |
|
6975 |
|
| 6976 |
// Emit the opcode for the instruction. |
6976 |
// Emit the opcode for the instruction. |
| 6977 |
uint64_t Bits = 0; |
6977 |
uint64_t Bits = 0; |
| 6978 |
Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0; |
6978 |
Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0; |
| 6979 |
Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32; |
6979 |
Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32; |
| 6980 |
return {AsmStrs+(Bits & 16383)-1, Bits}; |
6980 |
return {AsmStrs+(Bits & 16383)-1, Bits}; |
| 6981 |
|
6981 |
|
| 6982 |
} |
6982 |
} |
| 6983 |
/// printInstruction - This method is automatically generated by tablegen |
6983 |
/// printInstruction - This method is automatically generated by tablegen |
| 6984 |
/// from the instruction set description. |
6984 |
/// from the instruction set description. |
| 6985 |
LLVM_NO_PROFILE_INSTRUMENT_FUNCTION |
6985 |
LLVM_NO_PROFILE_INSTRUMENT_FUNCTION |
| 6986 |
void MipsInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) { |
6986 |
void MipsInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) { |
| 6987 |
O << "\t"; |
6987 |
O << "\t"; |
| 6988 |
|
6988 |
|
| 6989 |
auto MnemonicInfo = getMnemonic(MI); |
6989 |
auto MnemonicInfo = getMnemonic(MI); |
| 6990 |
|
6990 |
|
| 6991 |
O << MnemonicInfo.first; |
6991 |
O << MnemonicInfo.first; |
| 6992 |
|
6992 |
|
| 6993 |
uint64_t Bits = MnemonicInfo.second; |
6993 |
uint64_t Bits = MnemonicInfo.second; |
| 6994 |
assert(Bits != 0 && "Cannot print this instruction."); |
6994 |
assert(Bits != 0 && "Cannot print this instruction."); |
| 6995 |
|
6995 |
|
| 6996 |
// Fragment 0 encoded into 5 bits for 17 unique commands. |
6996 |
// Fragment 0 encoded into 5 bits for 17 unique commands. |
| 6997 |
switch ((Bits >> 14) & 31) { |
6997 |
switch ((Bits >> 14) & 31) { |
| 6998 |
default: llvm_unreachable("Invalid command number."); |
6998 |
default: llvm_unreachable("Invalid command number."); |
| 6999 |
case 0: |
6999 |
case 0: |
| 7000 |
// DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... |
7000 |
// DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... |
| 7001 |
return; |
7001 |
return; |
| 7002 |
break; |
7002 |
break; |
| 7003 |
case 1: |
7003 |
case 1: |
| 7004 |
// ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... |
7004 |
// ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... |
| 7005 |
printOperand(MI, 0, STI, O); |
7005 |
printOperand(MI, 0, STI, O); |
| 7006 |
break; |
7006 |
break; |
| 7007 |
case 2: |
7007 |
case 2: |
| 7008 |
// B_MMR6_Pseudo, B_MM_Pseudo, B16_MM, BAL, BALC, BALC_MMR6, BC, BC16_MMR... |
7008 |
// B_MMR6_Pseudo, B_MM_Pseudo, B16_MM, BAL, BALC, BALC_MMR6, BC, BC16_MMR... |
| 7009 |
printBranchOperand(MI, Address, 0, STI, O); |
7009 |
printBranchOperand(MI, Address, 0, STI, O); |
| 7010 |
break; |
7010 |
break; |
| 7011 |
case 3: |
7011 |
case 3: |
| 7012 |
// CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, MultRxRyRz1... |
7012 |
// CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, MultRxRyRz1... |
| 7013 |
printOperand(MI, 1, STI, O); |
7013 |
printOperand(MI, 1, STI, O); |
| 7014 |
O << ", "; |
7014 |
O << ", "; |
| 7015 |
break; |
7015 |
break; |
| 7016 |
case 4: |
7016 |
case 4: |
| 7017 |
// LWM_MM, SWM_MM, LWM16_MM, LWM16_MMR6, LWM32_MM, SWM16_MM, SWM16_MMR6, ... |
7017 |
// LWM_MM, SWM_MM, LWM16_MM, LWM16_MMR6, LWM32_MM, SWM16_MM, SWM16_MMR6, ... |
| 7018 |
printRegisterList(MI, 0, STI, O); |
7018 |
printRegisterList(MI, 0, STI, O); |
| 7019 |
O << ", "; |
7019 |
O << ", "; |
| 7020 |
printMemOperand(MI, 1, STI, O); |
7020 |
printMemOperand(MI, 1, STI, O); |
| 7021 |
return; |
7021 |
return; |
| 7022 |
break; |
7022 |
break; |
| 7023 |
case 5: |
7023 |
case 5: |
| 7024 |
// SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ... |
7024 |
// SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ... |
| 7025 |
printOperand(MI, 3, STI, O); |
7025 |
printOperand(MI, 3, STI, O); |
| 7026 |
break; |
7026 |
break; |
| 7027 |
case 6: |
7027 |
case 6: |
| 7028 |
// AND16_MM, AND16_MMR6, LSA_MMR6, MTHC1_D32, MTHC1_D32_MM, MTHC1_D64, MT... |
7028 |
// AND16_MM, AND16_MMR6, LSA_MMR6, MTHC1_D32, MTHC1_D32_MM, MTHC1_D64, MT... |
| 7029 |
printOperand(MI, 2, STI, O); |
7029 |
printOperand(MI, 2, STI, O); |
| 7030 |
O << ", "; |
7030 |
O << ", "; |
| 7031 |
break; |
7031 |
break; |
| 7032 |
case 7: |
7032 |
case 7: |
| 7033 |
// BREAK, BREAK_MM, BREAK_MMR6, HYPCALL, HYPCALL_MM, SDBBP_MM, SYSCALL_MM... |
7033 |
// BREAK, BREAK_MM, BREAK_MMR6, HYPCALL, HYPCALL_MM, SDBBP_MM, SYSCALL_MM... |
| 7034 |
printUImm<10>(MI, 0, STI, O); |
7034 |
printUImm<10>(MI, 0, STI, O); |
| 7035 |
break; |
7035 |
break; |
| 7036 |
case 8: |
7036 |
case 8: |
| 7037 |
// BREAK16_MM, BREAK16_MMR6, SDBBP16_MM, SDBBP16_MMR6 |
7037 |
// BREAK16_MM, BREAK16_MMR6, SDBBP16_MM, SDBBP16_MMR6 |
| 7038 |
printUImm<4>(MI, 0, STI, O); |
7038 |
printUImm<4>(MI, 0, STI, O); |
| 7039 |
return; |
7039 |
return; |
| 7040 |
break; |
7040 |
break; |
| 7041 |
case 9: |
7041 |
case 9: |
| 7042 |
// CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,... |
7042 |
// CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,... |
| 7043 |
printUImm<5>(MI, 2, STI, O); |
7043 |
printUImm<5>(MI, 2, STI, O); |
| 7044 |
O << ", "; |
7044 |
O << ", "; |
| 7045 |
break; |
7045 |
break; |
| 7046 |
case 10: |
7046 |
case 10: |
| 7047 |
// FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM |
7047 |
// FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM |
| 7048 |
printFCCOperand(MI, 2, STI, O); |
7048 |
printFCCOperand(MI, 2, STI, O); |
| 7049 |
break; |
7049 |
break; |
| 7050 |
case 11: |
7050 |
case 11: |
| 7051 |
// J, JAL, JALS_MM, JALX, JALX_MM, JAL_MM, J_MM |
7051 |
// J, JAL, JALS_MM, JALX, JALX_MM, JAL_MM, J_MM |
| 7052 |
printJumpOperand(MI, 0, STI, O); |
7052 |
printJumpOperand(MI, 0, STI, O); |
| 7053 |
return; |
7053 |
return; |
| 7054 |
break; |
7054 |
break; |
| 7055 |
case 12: |
7055 |
case 12: |
| 7056 |
// Jal16, JalB16 |
7056 |
// Jal16, JalB16 |
| 7057 |
printUImm<26>(MI, 0, STI, O); |
7057 |
printUImm<26>(MI, 0, STI, O); |
| 7058 |
break; |
7058 |
break; |
| 7059 |
case 13: |
7059 |
case 13: |
| 7060 |
// SDBBP, SDBBP_MMR6, SDBBP_R6, SYSCALL |
7060 |
// SDBBP, SDBBP_MMR6, SDBBP_R6, SYSCALL |
| 7061 |
printUImm<20>(MI, 0, STI, O); |
7061 |
printUImm<20>(MI, 0, STI, O); |
| 7062 |
return; |
7062 |
return; |
| 7063 |
break; |
7063 |
break; |
| 7064 |
case 14: |
7064 |
case 14: |
| 7065 |
// SIGRIE, SIGRIE_MMR6 |
7065 |
// SIGRIE, SIGRIE_MMR6 |
| 7066 |
printUImm<16>(MI, 0, STI, O); |
7066 |
printUImm<16>(MI, 0, STI, O); |
| 7067 |
return; |
7067 |
return; |
| 7068 |
break; |
7068 |
break; |
| 7069 |
case 15: |
7069 |
case 15: |
| 7070 |
// SYNC, SYNC_MM, SYNC_MMR6 |
7070 |
// SYNC, SYNC_MM, SYNC_MMR6 |
| 7071 |
printUImm<5>(MI, 0, STI, O); |
7071 |
printUImm<5>(MI, 0, STI, O); |
| 7072 |
return; |
7072 |
return; |
| 7073 |
break; |
7073 |
break; |
| 7074 |
case 16: |
7074 |
case 16: |
| 7075 |
// SYNCI, SYNCI_MM, SYNCI_MMR6 |
7075 |
// SYNCI, SYNCI_MM, SYNCI_MMR6 |
| 7076 |
printMemOperand(MI, 0, STI, O); |
7076 |
printMemOperand(MI, 0, STI, O); |
| 7077 |
return; |
7077 |
return; |
| 7078 |
break; |
7078 |
break; |
| 7079 |
} |
7079 |
} |
| 7080 |
|
7080 |
|
| 7081 |
|
7081 |
|
| 7082 |
// Fragment 1 encoded into 5 bits for 18 unique commands. |
7082 |
// Fragment 1 encoded into 5 bits for 18 unique commands. |
| 7083 |
switch ((Bits >> 19) & 31) { |
7083 |
switch ((Bits >> 19) & 31) { |
| 7084 |
default: llvm_unreachable("Invalid command number."); |
7084 |
default: llvm_unreachable("Invalid command number."); |
| 7085 |
case 0: |
7085 |
case 0: |
| 7086 |
// ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... |
7086 |
// ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... |
| 7087 |
O << ", "; |
7087 |
O << ", "; |
| 7088 |
break; |
7088 |
break; |
| 7089 |
case 1: |
7089 |
case 1: |
| 7090 |
// B_MMR6_Pseudo, B_MM_Pseudo, Constant32, JalOneReg, MFTDSP, MTTDSP, ADD... |
7090 |
// B_MMR6_Pseudo, B_MM_Pseudo, Constant32, JalOneReg, MFTDSP, MTTDSP, ADD... |
| 7091 |
return; |
7091 |
return; |
| 7092 |
break; |
7092 |
break; |
| 7093 |
case 2: |
7093 |
case 2: |
| 7094 |
// CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, CTC1, CTC1_... |
7094 |
// CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, CTC1, CTC1_... |
| 7095 |
printOperand(MI, 0, STI, O); |
7095 |
printOperand(MI, 0, STI, O); |
| 7096 |
break; |
7096 |
break; |
| 7097 |
case 3: |
7097 |
case 3: |
| 7098 |
// LwConstant32 |
7098 |
// LwConstant32 |
| 7099 |
O << ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"; |
7099 |
O << ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"; |
| 7100 |
printOperand(MI, 1, STI, O); |
7100 |
printOperand(MI, 1, STI, O); |
| 7101 |
O << "\n2:"; |
7101 |
O << "\n2:"; |
| 7102 |
return; |
7102 |
return; |
| 7103 |
break; |
7103 |
break; |
| 7104 |
case 4: |
7104 |
case 4: |
| 7105 |
// MultRxRyRz16, MultuRxRyRz16, SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImm... |
7105 |
// MultRxRyRz16, MultuRxRyRz16, SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImm... |
| 7106 |
printOperand(MI, 2, STI, O); |
7106 |
printOperand(MI, 2, STI, O); |
| 7107 |
break; |
7107 |
break; |
| 7108 |
case 5: |
7108 |
case 5: |
| 7109 |
// SelBeqZ, SelBneZ |
7109 |
// SelBeqZ, SelBneZ |
| 7110 |
O << ", .+4\n\t\n\tmove "; |
7110 |
O << ", .+4\n\t\n\tmove "; |
| 7111 |
printOperand(MI, 1, STI, O); |
7111 |
printOperand(MI, 1, STI, O); |
| 7112 |
O << ", "; |
7112 |
O << ", "; |
| 7113 |
printOperand(MI, 2, STI, O); |
7113 |
printOperand(MI, 2, STI, O); |
| 7114 |
return; |
7114 |
return; |
| 7115 |
break; |
7115 |
break; |
| 7116 |
case 6: |
7116 |
case 6: |
| 7117 |
// AND16_MM, AND16_MMR6, LSA_MMR6, OR16_MM, OR16_MMR6, PREFX_MM, XOR16_MM... |
7117 |
// AND16_MM, AND16_MMR6, LSA_MMR6, OR16_MM, OR16_MMR6, PREFX_MM, XOR16_MM... |
| 7118 |
printOperand(MI, 1, STI, O); |
7118 |
printOperand(MI, 1, STI, O); |
| 7119 |
break; |
7119 |
break; |
| 7120 |
case 7: |
7120 |
case 7: |
| 7121 |
// AddiuRxPcImmX16 |
7121 |
// AddiuRxPcImmX16 |
| 7122 |
O << ", $pc, "; |
7122 |
O << ", $pc, "; |
| 7123 |
printOperand(MI, 1, STI, O); |
7123 |
printOperand(MI, 1, STI, O); |
| 7124 |
return; |
7124 |
return; |
| 7125 |
break; |
7125 |
break; |
| 7126 |
case 8: |
7126 |
case 8: |
| 7127 |
// AddiuSpImm16, Bimm16 |
7127 |
// AddiuSpImm16, Bimm16 |
| 7128 |
O << " # 16 bit inst"; |
7128 |
O << " # 16 bit inst"; |
| 7129 |
return; |
7129 |
return; |
| 7130 |
break; |
7130 |
break; |
| 7131 |
case 9: |
7131 |
case 9: |
| 7132 |
// Bteqz16, Btnez16 |
7132 |
// Bteqz16, Btnez16 |
| 7133 |
O << " # 16 bit inst"; |
7133 |
O << " # 16 bit inst"; |
| 7134 |
return; |
7134 |
return; |
| 7135 |
break; |
7135 |
break; |
| 7136 |
case 10: |
7136 |
case 10: |
| 7137 |
// CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,... |
7137 |
// CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,... |
| 7138 |
printMemOperand(MI, 0, STI, O); |
7138 |
printMemOperand(MI, 0, STI, O); |
| 7139 |
return; |
7139 |
return; |
| 7140 |
break; |
7140 |
break; |
| 7141 |
case 11: |
7141 |
case 11: |
| 7142 |
// FCMP_D32, FCMP_D32_MM, FCMP_D64 |
7142 |
// FCMP_D32, FCMP_D32_MM, FCMP_D64 |
| 7143 |
O << ".d\t"; |
7143 |
O << ".d\t"; |
| 7144 |
printOperand(MI, 0, STI, O); |
7144 |
printOperand(MI, 0, STI, O); |
| 7145 |
O << ", "; |
7145 |
O << ", "; |
| 7146 |
printOperand(MI, 1, STI, O); |
7146 |
printOperand(MI, 1, STI, O); |
| 7147 |
return; |
7147 |
return; |
| 7148 |
break; |
7148 |
break; |
| 7149 |
case 12: |
7149 |
case 12: |
| 7150 |
// FCMP_S32, FCMP_S32_MM |
7150 |
// FCMP_S32, FCMP_S32_MM |
| 7151 |
O << ".s\t"; |
7151 |
O << ".s\t"; |
| 7152 |
printOperand(MI, 0, STI, O); |
7152 |
printOperand(MI, 0, STI, O); |
| 7153 |
O << ", "; |
7153 |
O << ", "; |
| 7154 |
printOperand(MI, 1, STI, O); |
7154 |
printOperand(MI, 1, STI, O); |
| 7155 |
return; |
7155 |
return; |
| 7156 |
break; |
7156 |
break; |
| 7157 |
case 13: |
7157 |
case 13: |
| 7158 |
// INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS... |
7158 |
// INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS... |
| 7159 |
O << '['; |
7159 |
O << '['; |
| 7160 |
break; |
7160 |
break; |
| 7161 |
case 14: |
7161 |
case 14: |
| 7162 |
// Jal16 |
7162 |
// Jal16 |
| 7163 |
O << "\n\tnop"; |
7163 |
O << "\n\tnop"; |
| 7164 |
return; |
7164 |
return; |
| 7165 |
break; |
7165 |
break; |
| 7166 |
case 15: |
7166 |
case 15: |
| 7167 |
// JalB16 |
7167 |
// JalB16 |
| 7168 |
O << "\t# branch\n\tnop"; |
7168 |
O << "\t# branch\n\tnop"; |
| 7169 |
return; |
7169 |
return; |
| 7170 |
break; |
7170 |
break; |
| 7171 |
case 16: |
7171 |
case 16: |
| 7172 |
// SAA, SAAD |
7172 |
// SAA, SAAD |
| 7173 |
O << ", ("; |
7173 |
O << ", ("; |
| 7174 |
printOperand(MI, 1, STI, O); |
7174 |
printOperand(MI, 1, STI, O); |
| 7175 |
O << ')'; |
7175 |
O << ')'; |
| 7176 |
return; |
7176 |
return; |
| 7177 |
break; |
7177 |
break; |
| 7178 |
case 17: |
7178 |
case 17: |
| 7179 |
// SC, SC64, SC64_R6, SCD, SCD_R6, SCE, SCE_MM, SC_MM, SC_MMR6, SC_R6 |
7179 |
// SC, SC64, SC64_R6, SCD, SCD_R6, SCE, SCE_MM, SC_MM, SC_MMR6, SC_R6 |
| 7180 |
printMemOperand(MI, 2, STI, O); |
7180 |
printMemOperand(MI, 2, STI, O); |
| 7181 |
return; |
7181 |
return; |
| 7182 |
break; |
7182 |
break; |
| 7183 |
} |
7183 |
} |
| 7184 |
|
7184 |
|
| 7185 |
|
7185 |
|
| 7186 |
// Fragment 2 encoded into 5 bits for 26 unique commands. |
7186 |
// Fragment 2 encoded into 5 bits for 26 unique commands. |
| 7187 |
switch ((Bits >> 24) & 31) { |
7187 |
switch ((Bits >> 24) & 31) { |
| 7188 |
default: llvm_unreachable("Invalid command number."); |
7188 |
default: llvm_unreachable("Invalid command number."); |
| 7189 |
case 0: |
7189 |
case 0: |
| 7190 |
// ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... |
7190 |
// ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... |
| 7191 |
printOperand(MI, 1, STI, O); |
7191 |
printOperand(MI, 1, STI, O); |
| 7192 |
break; |
7192 |
break; |
| 7193 |
case 1: |
7193 |
case 1: |
| 7194 |
// CTTC1, MTTACX, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, ADDIUS5_MM, AND16_... |
7194 |
// CTTC1, MTTACX, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, ADDIUS5_MM, AND16_... |
| 7195 |
return; |
7195 |
return; |
| 7196 |
break; |
7196 |
break; |
| 7197 |
case 2: |
7197 |
case 2: |
| 7198 |
// GotPrologue16, AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B,... |
7198 |
// GotPrologue16, AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B,... |
| 7199 |
printOperand(MI, 2, STI, O); |
7199 |
printOperand(MI, 2, STI, O); |
| 7200 |
break; |
7200 |
break; |
| 7201 |
case 3: |
7201 |
case 3: |
| 7202 |
// LDMacro, LOAD_ACC128, LOAD_ACC64, LOAD_ACC64DSP, LOAD_CCOND_DSP, LoadA... |
7202 |
// LDMacro, LOAD_ACC128, LOAD_ACC64, LOAD_ACC64DSP, LOAD_CCOND_DSP, LoadA... |
| 7203 |
printMemOperand(MI, 1, STI, O); |
7203 |
printMemOperand(MI, 1, STI, O); |
| 7204 |
return; |
7204 |
return; |
| 7205 |
break; |
7205 |
break; |
| 7206 |
case 4: |
7206 |
case 4: |
| 7207 |
// MTTC0, DMTC0, DMTC2, DMTGC0, FORK, LSA_MMR6, MTC0, MTC0_MMR6, MTC2, MT... |
7207 |
// MTTC0, DMTC0, DMTC2, DMTGC0, FORK, LSA_MMR6, MTC0, MTC0_MMR6, MTC2, MT... |
| 7208 |
O << ", "; |
7208 |
O << ", "; |
| 7209 |
break; |
7209 |
break; |
| 7210 |
case 5: |
7210 |
case 5: |
| 7211 |
// MultRxRyRz16, MultuRxRyRz16 |
7211 |
// MultRxRyRz16, MultuRxRyRz16 |
| 7212 |
O << "\n\tmflo\t"; |
7212 |
O << "\n\tmflo\t"; |
| 7213 |
printOperand(MI, 0, STI, O); |
7213 |
printOperand(MI, 0, STI, O); |
| 7214 |
return; |
7214 |
return; |
| 7215 |
break; |
7215 |
break; |
| 7216 |
case 6: |
7216 |
case 6: |
| 7217 |
// SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... |
7217 |
// SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... |
| 7218 |
printOperand(MI, 4, STI, O); |
7218 |
printOperand(MI, 4, STI, O); |
| 7219 |
break; |
7219 |
break; |
| 7220 |
case 7: |
7220 |
case 7: |
| 7221 |
// SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz... |
7221 |
// SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz... |
| 7222 |
O << "\n\tmove\t"; |
7222 |
O << "\n\tmove\t"; |
| 7223 |
printOperand(MI, 0, STI, O); |
7223 |
printOperand(MI, 0, STI, O); |
| 7224 |
O << ", $t8"; |
7224 |
O << ", $t8"; |
| 7225 |
return; |
7225 |
return; |
| 7226 |
break; |
7226 |
break; |
| 7227 |
case 8: |
7227 |
case 8: |
| 7228 |
// AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM |
7228 |
// AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM |
| 7229 |
printMemOperandEA(MI, 1, STI, O); |
7229 |
printMemOperandEA(MI, 1, STI, O); |
| 7230 |
return; |
7230 |
return; |
| 7231 |
break; |
7231 |
break; |
| 7232 |
case 9: |
7232 |
case 9: |
| 7233 |
// BBIT0, BBIT032, BBIT1, BBIT132 |
7233 |
// BBIT0, BBIT032, BBIT1, BBIT132 |
| 7234 |
printUImm<5>(MI, 1, STI, O); |
7234 |
printUImm<5>(MI, 1, STI, O); |
| 7235 |
O << ", "; |
7235 |
O << ", "; |
| 7236 |
printBranchOperand(MI, Address, 2, STI, O); |
7236 |
printBranchOperand(MI, Address, 2, STI, O); |
| 7237 |
return; |
7237 |
return; |
| 7238 |
break; |
7238 |
break; |
| 7239 |
case 10: |
7239 |
case 10: |
| 7240 |
// BC1EQZ, BC1EQZC_MMR6, BC1F, BC1FL, BC1F_MM, BC1NEZ, BC1NEZC_MMR6, BC1T... |
7240 |
// BC1EQZ, BC1EQZC_MMR6, BC1F, BC1FL, BC1F_MM, BC1NEZ, BC1NEZC_MMR6, BC1T... |
| 7241 |
printBranchOperand(MI, Address, 1, STI, O); |
7241 |
printBranchOperand(MI, Address, 1, STI, O); |
| 7242 |
break; |
7242 |
break; |
| 7243 |
case 11: |
7243 |
case 11: |
| 7244 |
// BREAK, BREAK_MM, BREAK_MMR6, RDDSP, WRDSP |
7244 |
// BREAK, BREAK_MM, BREAK_MMR6, RDDSP, WRDSP |
| 7245 |
printUImm<10>(MI, 1, STI, O); |
7245 |
printUImm<10>(MI, 1, STI, O); |
| 7246 |
return; |
7246 |
return; |
| 7247 |
break; |
7247 |
break; |
| 7248 |
case 12: |
7248 |
case 12: |
| 7249 |
// DMFC2_OCTEON, DMTC2_OCTEON, LUI_MMR6, LUi, LUi64, LUi_MM |
7249 |
// DMFC2_OCTEON, DMTC2_OCTEON, LUI_MMR6, LUi, LUi64, LUi_MM |
| 7250 |
printUImm<16>(MI, 1, STI, O); |
7250 |
printUImm<16>(MI, 1, STI, O); |
| 7251 |
return; |
7251 |
return; |
| 7252 |
break; |
7252 |
break; |
| 7253 |
case 13: |
7253 |
case 13: |
| 7254 |
// GINVT, GINVT_MMR6 |
7254 |
// GINVT, GINVT_MMR6 |
| 7255 |
printUImm<2>(MI, 1, STI, O); |
7255 |
printUImm<2>(MI, 1, STI, O); |
| 7256 |
return; |
7256 |
return; |
| 7257 |
break; |
7257 |
break; |
| 7258 |
case 14: |
7258 |
case 14: |
| 7259 |
// INSERT_B |
7259 |
// INSERT_B |
| 7260 |
printUImm<4>(MI, 3, STI, O); |
7260 |
printUImm<4>(MI, 3, STI, O); |
| 7261 |
O << "], "; |
7261 |
O << "], "; |
| 7262 |
printOperand(MI, 2, STI, O); |
7262 |
printOperand(MI, 2, STI, O); |
| 7263 |
return; |
7263 |
return; |
| 7264 |
break; |
7264 |
break; |
| 7265 |
case 15: |
7265 |
case 15: |
| 7266 |
// INSERT_D |
7266 |
// INSERT_D |
| 7267 |
printUImm<1>(MI, 3, STI, O); |
7267 |
printUImm<1>(MI, 3, STI, O); |
| 7268 |
O << "], "; |
7268 |
O << "], "; |
| 7269 |
printOperand(MI, 2, STI, O); |
7269 |
printOperand(MI, 2, STI, O); |
| 7270 |
return; |
7270 |
return; |
| 7271 |
break; |
7271 |
break; |
| 7272 |
case 16: |
7272 |
case 16: |
| 7273 |
// INSERT_H |
7273 |
// INSERT_H |
| 7274 |
printUImm<3>(MI, 3, STI, O); |
7274 |
printUImm<3>(MI, 3, STI, O); |
| 7275 |
O << "], "; |
7275 |
O << "], "; |
| 7276 |
printOperand(MI, 2, STI, O); |
7276 |
printOperand(MI, 2, STI, O); |
| 7277 |
return; |
7277 |
return; |
| 7278 |
break; |
7278 |
break; |
| 7279 |
case 17: |
7279 |
case 17: |
| 7280 |
// INSERT_W |
7280 |
// INSERT_W |
| 7281 |
printUImm<2>(MI, 3, STI, O); |
7281 |
printUImm<2>(MI, 3, STI, O); |
| 7282 |
O << "], "; |
7282 |
O << "], "; |
| 7283 |
printOperand(MI, 2, STI, O); |
7283 |
printOperand(MI, 2, STI, O); |
| 7284 |
return; |
7284 |
return; |
| 7285 |
break; |
7285 |
break; |
| 7286 |
case 18: |
7286 |
case 18: |
| 7287 |
// INSVE_B |
7287 |
// INSVE_B |
| 7288 |
printUImm<4>(MI, 2, STI, O); |
7288 |
printUImm<4>(MI, 2, STI, O); |
| 7289 |
O << "], "; |
7289 |
O << "], "; |
| 7290 |
printOperand(MI, 3, STI, O); |
7290 |
printOperand(MI, 3, STI, O); |
| 7291 |
O << '['; |
7291 |
O << '['; |
| 7292 |
printUImm<0>(MI, 4, STI, O); |
7292 |
printUImm<0>(MI, 4, STI, O); |
| 7293 |
O << ']'; |
7293 |
O << ']'; |
| 7294 |
return; |
7294 |
return; |
| 7295 |
break; |
7295 |
break; |
| 7296 |
case 19: |
7296 |
case 19: |
| 7297 |
// INSVE_D |
7297 |
// INSVE_D |
| 7298 |
printUImm<1>(MI, 2, STI, O); |
7298 |
printUImm<1>(MI, 2, STI, O); |
| 7299 |
O << "], "; |
7299 |
O << "], "; |
| 7300 |
printOperand(MI, 3, STI, O); |
7300 |
printOperand(MI, 3, STI, O); |
| 7301 |
O << '['; |
7301 |
O << '['; |
| 7302 |
printUImm<0>(MI, 4, STI, O); |
7302 |
printUImm<0>(MI, 4, STI, O); |
| 7303 |
O << ']'; |
7303 |
O << ']'; |
| 7304 |
return; |
7304 |
return; |
| 7305 |
break; |
7305 |
break; |
| 7306 |
case 20: |
7306 |
case 20: |
| 7307 |
// INSVE_H |
7307 |
// INSVE_H |
| 7308 |
printUImm<3>(MI, 2, STI, O); |
7308 |
printUImm<3>(MI, 2, STI, O); |
| 7309 |
O << "], "; |
7309 |
O << "], "; |
| 7310 |
printOperand(MI, 3, STI, O); |
7310 |
printOperand(MI, 3, STI, O); |
| 7311 |
O << '['; |
7311 |
O << '['; |
| 7312 |
printUImm<0>(MI, 4, STI, O); |
7312 |
printUImm<0>(MI, 4, STI, O); |
| 7313 |
O << ']'; |
7313 |
O << ']'; |
| 7314 |
return; |
7314 |
return; |
| 7315 |
break; |
7315 |
break; |
| 7316 |
case 21: |
7316 |
case 21: |
| 7317 |
// INSVE_W |
7317 |
// INSVE_W |
| 7318 |
printUImm<2>(MI, 2, STI, O); |
7318 |
printUImm<2>(MI, 2, STI, O); |
| 7319 |
O << "], "; |
7319 |
O << "], "; |
| 7320 |
printOperand(MI, 3, STI, O); |
7320 |
printOperand(MI, 3, STI, O); |
| 7321 |
O << '['; |
7321 |
O << '['; |
| 7322 |
printUImm<0>(MI, 4, STI, O); |
7322 |
printUImm<0>(MI, 4, STI, O); |
| 7323 |
O << ']'; |
7323 |
O << ']'; |
| 7324 |
return; |
7324 |
return; |
| 7325 |
break; |
7325 |
break; |
| 7326 |
case 22: |
7326 |
case 22: |
| 7327 |
// LWP_MM, SWP_MM |
7327 |
// LWP_MM, SWP_MM |
| 7328 |
printMemOperand(MI, 2, STI, O); |
7328 |
printMemOperand(MI, 2, STI, O); |
| 7329 |
return; |
7329 |
return; |
| 7330 |
break; |
7330 |
break; |
| 7331 |
case 23: |
7331 |
case 23: |
| 7332 |
// PREFX_MM |
7332 |
// PREFX_MM |
| 7333 |
O << '('; |
7333 |
O << '('; |
| 7334 |
printOperand(MI, 0, STI, O); |
7334 |
printOperand(MI, 0, STI, O); |
| 7335 |
O << ')'; |
7335 |
O << ')'; |
| 7336 |
return; |
7336 |
return; |
| 7337 |
break; |
7337 |
break; |
| 7338 |
case 24: |
7338 |
case 24: |
| 7339 |
// RDDSP_MM, WRDSP_MM |
7339 |
// RDDSP_MM, WRDSP_MM |
| 7340 |
printUImm<7>(MI, 1, STI, O); |
7340 |
printUImm<7>(MI, 1, STI, O); |
| 7341 |
return; |
7341 |
return; |
| 7342 |
break; |
7342 |
break; |
| 7343 |
case 25: |
7343 |
case 25: |
| 7344 |
// REPL_QB, REPL_QB_MM |
7344 |
// REPL_QB, REPL_QB_MM |
| 7345 |
printUImm<8>(MI, 1, STI, O); |
7345 |
printUImm<8>(MI, 1, STI, O); |
| 7346 |
return; |
7346 |
return; |
| 7347 |
break; |
7347 |
break; |
| 7348 |
} |
7348 |
} |
| 7349 |
|
7349 |
|
| 7350 |
|
7350 |
|
| 7351 |
// Fragment 3 encoded into 5 bits for 18 unique commands. |
7351 |
// Fragment 3 encoded into 5 bits for 18 unique commands. |
| 7352 |
switch ((Bits >> 29) & 31) { |
7352 |
switch ((Bits >> 29) & 31) { |
| 7353 |
default: llvm_unreachable("Invalid command number."); |
7353 |
default: llvm_unreachable("Invalid command number."); |
| 7354 |
case 0: |
7354 |
case 0: |
| 7355 |
// ABSMacro, CFTC1, JalTwoReg, LoadAddrImm32, LoadAddrImm64, LoadImm32, L... |
7355 |
// ABSMacro, CFTC1, JalTwoReg, LoadAddrImm32, LoadAddrImm64, LoadImm32, L... |
| 7356 |
return; |
7356 |
return; |
| 7357 |
break; |
7357 |
break; |
| 7358 |
case 1: |
7358 |
case 1: |
| 7359 |
// BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro... |
7359 |
// BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro... |
| 7360 |
O << ", "; |
7360 |
O << ", "; |
| 7361 |
break; |
7361 |
break; |
| 7362 |
case 2: |
7362 |
case 2: |
| 7363 |
// BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S... |
7363 |
// BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S... |
| 7364 |
O << "\n\tbteqz\t"; |
7364 |
O << "\n\tbteqz\t"; |
| 7365 |
printBranchOperand(MI, Address, 2, STI, O); |
7365 |
printBranchOperand(MI, Address, 2, STI, O); |
| 7366 |
return; |
7366 |
return; |
| 7367 |
break; |
7367 |
break; |
| 7368 |
case 3: |
7368 |
case 3: |
| 7369 |
// BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S... |
7369 |
// BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S... |
| 7370 |
O << "\n\tbtnez\t"; |
7370 |
O << "\n\tbtnez\t"; |
| 7371 |
printBranchOperand(MI, Address, 2, STI, O); |
7371 |
printBranchOperand(MI, Address, 2, STI, O); |
| 7372 |
return; |
7372 |
return; |
| 7373 |
break; |
7373 |
break; |
| 7374 |
case 4: |
7374 |
case 4: |
| 7375 |
// GotPrologue16 |
7375 |
// GotPrologue16 |
| 7376 |
O << "\n\taddiu\t"; |
7376 |
O << "\n\taddiu\t"; |
| 7377 |
printOperand(MI, 1, STI, O); |
7377 |
printOperand(MI, 1, STI, O); |
| 7378 |
O << ", $pc, "; |
7378 |
O << ", $pc, "; |
| 7379 |
printOperand(MI, 3, STI, O); |
7379 |
printOperand(MI, 3, STI, O); |
| 7380 |
O << "\n "; |
7380 |
O << "\n "; |
| 7381 |
return; |
7381 |
return; |
| 7382 |
break; |
7382 |
break; |
| 7383 |
case 5: |
7383 |
case 5: |
| 7384 |
// MTTC0, DMTC0, DMTC2, DMTGC0, MTC0, MTC0_MMR6, MTC2, MTGC0, MTGC0_MM, M... |
7384 |
// MTTC0, DMTC0, DMTC2, DMTGC0, MTC0, MTC0_MMR6, MTC2, MTGC0, MTGC0_MM, M... |
| 7385 |
printUImm<3>(MI, 2, STI, O); |
7385 |
printUImm<3>(MI, 2, STI, O); |
| 7386 |
return; |
7386 |
return; |
| 7387 |
break; |
7387 |
break; |
| 7388 |
case 6: |
7388 |
case 6: |
| 7389 |
// SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... |
7389 |
// SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... |
| 7390 |
O << "\n\tbteqz\t.+4\n\tmove "; |
7390 |
O << "\n\tbteqz\t.+4\n\tmove "; |
| 7391 |
printOperand(MI, 1, STI, O); |
7391 |
printOperand(MI, 1, STI, O); |
| 7392 |
O << ", "; |
7392 |
O << ", "; |
| 7393 |
printOperand(MI, 2, STI, O); |
7393 |
printOperand(MI, 2, STI, O); |
| 7394 |
return; |
7394 |
return; |
| 7395 |
break; |
7395 |
break; |
| 7396 |
case 7: |
7396 |
case 7: |
| 7397 |
// SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt... |
7397 |
// SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt... |
| 7398 |
O << "\n\tbtnez\t.+4\n\tmove "; |
7398 |
O << "\n\tbtnez\t.+4\n\tmove "; |
| 7399 |
printOperand(MI, 1, STI, O); |
7399 |
printOperand(MI, 1, STI, O); |
| 7400 |
O << ", "; |
7400 |
O << ", "; |
| 7401 |
printOperand(MI, 2, STI, O); |
7401 |
printOperand(MI, 2, STI, O); |
| 7402 |
return; |
7402 |
return; |
| 7403 |
break; |
7403 |
break; |
| 7404 |
case 8: |
7404 |
case 8: |
| 7405 |
// AddiuRxRxImm16, LwRxPcTcp16 |
7405 |
// AddiuRxRxImm16, LwRxPcTcp16 |
| 7406 |
O << "\t# 16 bit inst"; |
7406 |
O << "\t# 16 bit inst"; |
| 7407 |
return; |
7407 |
return; |
| 7408 |
break; |
7408 |
break; |
| 7409 |
case 9: |
7409 |
case 9: |
| 7410 |
// BeqzRxImm16, BnezRxImm16 |
7410 |
// BeqzRxImm16, BnezRxImm16 |
| 7411 |
O << " # 16 bit inst"; |
7411 |
O << " # 16 bit inst"; |
| 7412 |
return; |
7412 |
return; |
| 7413 |
break; |
7413 |
break; |
| 7414 |
case 10: |
7414 |
case 10: |
| 7415 |
// COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ... |
7415 |
// COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ... |
| 7416 |
O << '['; |
7416 |
O << '['; |
| 7417 |
break; |
7417 |
break; |
| 7418 |
case 11: |
7418 |
case 11: |
| 7419 |
// CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16 |
7419 |
// CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16 |
| 7420 |
O << " \t# 16 bit inst"; |
7420 |
O << " \t# 16 bit inst"; |
| 7421 |
return; |
7421 |
return; |
| 7422 |
break; |
7422 |
break; |
| 7423 |
case 12: |
7423 |
case 12: |
| 7424 |
// DSLL64_32 |
7424 |
// DSLL64_32 |
| 7425 |
O << ", 32"; |
7425 |
O << ", 32"; |
| 7426 |
return; |
7426 |
return; |
| 7427 |
break; |
7427 |
break; |
| 7428 |
case 13: |
7428 |
case 13: |
| 7429 |
// FORK |
7429 |
// FORK |
| 7430 |
printOperand(MI, 2, STI, O); |
7430 |
printOperand(MI, 2, STI, O); |
| 7431 |
return; |
7431 |
return; |
| 7432 |
break; |
7432 |
break; |
| 7433 |
case 14: |
7433 |
case 14: |
| 7434 |
// LBUX, LBUX_MM, LDXC1, LDXC164, LHX, LHX_MM, LUXC1, LUXC164, LUXC1_MM, ... |
7434 |
// LBUX, LBUX_MM, LDXC1, LDXC164, LHX, LHX_MM, LUXC1, LUXC164, LUXC1_MM, ... |
| 7435 |
O << '('; |
7435 |
O << '('; |
| 7436 |
printOperand(MI, 1, STI, O); |
7436 |
printOperand(MI, 1, STI, O); |
| 7437 |
O << ')'; |
7437 |
O << ')'; |
| 7438 |
return; |
7438 |
return; |
| 7439 |
break; |
7439 |
break; |
| 7440 |
case 15: |
7440 |
case 15: |
| 7441 |
// LSA_MMR6 |
7441 |
// LSA_MMR6 |
| 7442 |
printOperand(MI, 0, STI, O); |
7442 |
printOperand(MI, 0, STI, O); |
| 7443 |
O << ", "; |
7443 |
O << ", "; |
| 7444 |
printUImm<2, 1>(MI, 3, STI, O); |
7444 |
printUImm<2, 1>(MI, 3, STI, O); |
| 7445 |
return; |
7445 |
return; |
| 7446 |
break; |
7446 |
break; |
| 7447 |
case 16: |
7447 |
case 16: |
| 7448 |
// MTTR |
7448 |
// MTTR |
| 7449 |
printUImm<1>(MI, 2, STI, O); |
7449 |
printUImm<1>(MI, 2, STI, O); |
| 7450 |
O << ", "; |
7450 |
O << ", "; |
| 7451 |
printUImm<3>(MI, 3, STI, O); |
7451 |
printUImm<3>(MI, 3, STI, O); |
| 7452 |
O << ", "; |
7452 |
O << ", "; |
| 7453 |
printUImm<1>(MI, 4, STI, O); |
7453 |
printUImm<1>(MI, 4, STI, O); |
| 7454 |
return; |
7454 |
return; |
| 7455 |
break; |
7455 |
break; |
| 7456 |
case 17: |
7456 |
case 17: |
| 7457 |
// SLL64_32, SLL64_64 |
7457 |
// SLL64_32, SLL64_64 |
| 7458 |
O << ", 0"; |
7458 |
O << ", 0"; |
| 7459 |
return; |
7459 |
return; |
| 7460 |
break; |
7460 |
break; |
| 7461 |
} |
7461 |
} |
| 7462 |
|
7462 |
|
| 7463 |
|
7463 |
|
| 7464 |
// Fragment 4 encoded into 5 bits for 21 unique commands. |
7464 |
// Fragment 4 encoded into 5 bits for 21 unique commands. |
| 7465 |
switch ((Bits >> 34) & 31) { |
7465 |
switch ((Bits >> 34) & 31) { |
| 7466 |
default: llvm_unreachable("Invalid command number."); |
7466 |
default: llvm_unreachable("Invalid command number."); |
| 7467 |
case 0: |
7467 |
case 0: |
| 7468 |
// BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro... |
7468 |
// BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro... |
| 7469 |
printBranchOperand(MI, Address, 2, STI, O); |
7469 |
printBranchOperand(MI, Address, 2, STI, O); |
| 7470 |
return; |
7470 |
return; |
| 7471 |
break; |
7471 |
break; |
| 7472 |
case 1: |
7472 |
case 1: |
| 7473 |
// DMULImmMacro, DMULMacro, DMULOMacro, DMULOUMacro, DROL, DROLImm, DROR,... |
7473 |
// DMULImmMacro, DMULMacro, DMULOMacro, DMULOUMacro, DROL, DROLImm, DROR,... |
| 7474 |
printOperand(MI, 2, STI, O); |
7474 |
printOperand(MI, 2, STI, O); |
| 7475 |
break; |
7475 |
break; |
| 7476 |
case 2: |
7476 |
case 2: |
| 7477 |
// MFTC0, BCLRI_B, BNEGI_B, BSETI_B, COPY_S_H, COPY_U_H, DMFC0, DMFC2, DM... |
7477 |
// MFTC0, BCLRI_B, BNEGI_B, BSETI_B, COPY_S_H, COPY_U_H, DMFC0, DMFC2, DM... |
| 7478 |
printUImm<3>(MI, 2, STI, O); |
7478 |
printUImm<3>(MI, 2, STI, O); |
| 7479 |
break; |
7479 |
break; |
| 7480 |
case 3: |
7480 |
case 3: |
| 7481 |
// ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, APPEND, APPEND_MMR2, BCLRI_W, BNEG... |
7481 |
// ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, APPEND, APPEND_MMR2, BCLRI_W, BNEG... |
| 7482 |
printUImm<5>(MI, 2, STI, O); |
7482 |
printUImm<5>(MI, 2, STI, O); |
| 7483 |
break; |
7483 |
break; |
| 7484 |
case 4: |
7484 |
case 4: |
| 7485 |
// ANDI_B, NORI_B, ORI_B, RDHWR, RDHWR64, RDHWR_MM, SHF_B, SHF_H, SHF_W, ... |
7485 |
// ANDI_B, NORI_B, ORI_B, RDHWR, RDHWR64, RDHWR_MM, SHF_B, SHF_H, SHF_W, ... |
| 7486 |
printUImm<8>(MI, 2, STI, O); |
7486 |
printUImm<8>(MI, 2, STI, O); |
| 7487 |
return; |
7487 |
return; |
| 7488 |
break; |
7488 |
break; |
| 7489 |
case 5: |
7489 |
case 5: |
| 7490 |
// ANDI_MMR6, ANDi, ANDi64, ANDi_MM, AUI, AUI_MMR6, DAHI, DATI, DAUI, ORI... |
7490 |
// ANDI_MMR6, ANDi, ANDi64, ANDi_MM, AUI, AUI_MMR6, DAHI, DATI, DAUI, ORI... |
| 7491 |
printUImm<16>(MI, 2, STI, O); |
7491 |
printUImm<16>(MI, 2, STI, O); |
| 7492 |
return; |
7492 |
return; |
| 7493 |
break; |
7493 |
break; |
| 7494 |
case 6: |
7494 |
case 6: |
| 7495 |
// BALIGN, BALIGN_MMR2, COPY_S_W, COPY_U_W, SPLATI_W |
7495 |
// BALIGN, BALIGN_MMR2, COPY_S_W, COPY_U_W, SPLATI_W |
| 7496 |
printUImm<2>(MI, 2, STI, O); |
7496 |
printUImm<2>(MI, 2, STI, O); |
| 7497 |
break; |
7497 |
break; |
| 7498 |
case 7: |
7498 |
case 7: |
| 7499 |
// BCLRI_D, BNEGI_D, BSETI_D, DEXT, DEXT64_32, DINS, DROTR, DSLL, DSRA, D... |
7499 |
// BCLRI_D, BNEGI_D, BSETI_D, DEXT, DEXT64_32, DINS, DROTR, DSLL, DSRA, D... |
| 7500 |
printUImm<6>(MI, 2, STI, O); |
7500 |
printUImm<6>(MI, 2, STI, O); |
| 7501 |
break; |
7501 |
break; |
| 7502 |
case 8: |
7502 |
case 8: |
| 7503 |
// BCLRI_H, BNEGI_H, BSETI_H, COPY_S_B, COPY_U_B, SAT_S_H, SAT_U_H, SHLL_... |
7503 |
// BCLRI_H, BNEGI_H, BSETI_H, COPY_S_B, COPY_U_B, SAT_S_H, SAT_U_H, SHLL_... |
| 7504 |
printUImm<4>(MI, 2, STI, O); |
7504 |
printUImm<4>(MI, 2, STI, O); |
| 7505 |
break; |
7505 |
break; |
| 7506 |
case 9: |
7506 |
case 9: |
| 7507 |
// BINSLI_B, BINSRI_B, SLDI_H |
7507 |
// BINSLI_B, BINSRI_B, SLDI_H |
| 7508 |
printUImm<3>(MI, 3, STI, O); |
7508 |
printUImm<3>(MI, 3, STI, O); |
| 7509 |
break; |
7509 |
break; |
| 7510 |
case 10: |
7510 |
case 10: |
| 7511 |
// BINSLI_D, BINSRI_D |
7511 |
// BINSLI_D, BINSRI_D |
| 7512 |
printUImm<6>(MI, 3, STI, O); |
7512 |
printUImm<6>(MI, 3, STI, O); |
| 7513 |
return; |
7513 |
return; |
| 7514 |
break; |
7514 |
break; |
| 7515 |
case 11: |
7515 |
case 11: |
| 7516 |
// BINSLI_H, BINSRI_H, SLDI_B |
7516 |
// BINSLI_H, BINSRI_H, SLDI_B |
| 7517 |
printUImm<4>(MI, 3, STI, O); |
7517 |
printUImm<4>(MI, 3, STI, O); |
| 7518 |
break; |
7518 |
break; |
| 7519 |
case 12: |
7519 |
case 12: |
| 7520 |
// BINSLI_W, BINSRI_W |
7520 |
// BINSLI_W, BINSRI_W |
| 7521 |
printUImm<5>(MI, 3, STI, O); |
7521 |
printUImm<5>(MI, 3, STI, O); |
| 7522 |
return; |
7522 |
return; |
| 7523 |
break; |
7523 |
break; |
| 7524 |
case 13: |
7524 |
case 13: |
| 7525 |
// BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W... |
7525 |
// BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W... |
| 7526 |
printOperand(MI, 3, STI, O); |
7526 |
printOperand(MI, 3, STI, O); |
| 7527 |
break; |
7527 |
break; |
| 7528 |
case 14: |
7528 |
case 14: |
| 7529 |
// BMNZI_B, BMZI_B, BSELI_B |
7529 |
// BMNZI_B, BMZI_B, BSELI_B |
| 7530 |
printUImm<8>(MI, 3, STI, O); |
7530 |
printUImm<8>(MI, 3, STI, O); |
| 7531 |
return; |
7531 |
return; |
| 7532 |
break; |
7532 |
break; |
| 7533 |
case 15: |
7533 |
case 15: |
| 7534 |
// COPY_S_D, MFTR, SPLATI_D |
7534 |
// COPY_S_D, MFTR, SPLATI_D |
| 7535 |
printUImm<1>(MI, 2, STI, O); |
7535 |
printUImm<1>(MI, 2, STI, O); |
| 7536 |
break; |
7536 |
break; |
| 7537 |
case 16: |
7537 |
case 16: |
| 7538 |
// DEXTU, DINSU |
7538 |
// DEXTU, DINSU |
| 7539 |
printUImm<5, 32>(MI, 2, STI, O); |
7539 |
printUImm<5, 32>(MI, 2, STI, O); |
| 7540 |
O << ", "; |
7540 |
O << ", "; |
| 7541 |
break; |
7541 |
break; |
| 7542 |
case 17: |
7542 |
case 17: |
| 7543 |
// FADD_S_MMR6, FDIV_S_MMR6, FMUL_S_MMR6, FSUB_S_MMR6 |
7543 |
// FADD_S_MMR6, FDIV_S_MMR6, FMUL_S_MMR6, FSUB_S_MMR6 |
| 7544 |
printOperand(MI, 1, STI, O); |
7544 |
printOperand(MI, 1, STI, O); |
| 7545 |
return; |
7545 |
return; |
| 7546 |
break; |
7546 |
break; |
| 7547 |
case 18: |
7547 |
case 18: |
| 7548 |
// SLDI_D |
7548 |
// SLDI_D |
| 7549 |
printUImm<1>(MI, 3, STI, O); |
7549 |
printUImm<1>(MI, 3, STI, O); |
| 7550 |
O << ']'; |
7550 |
O << ']'; |
| 7551 |
return; |
7551 |
return; |
| 7552 |
break; |
7552 |
break; |
| 7553 |
case 19: |
7553 |
case 19: |
| 7554 |
// SLDI_W |
7554 |
// SLDI_W |
| 7555 |
printUImm<2>(MI, 3, STI, O); |
7555 |
printUImm<2>(MI, 3, STI, O); |
| 7556 |
O << ']'; |
7556 |
O << ']'; |
| 7557 |
return; |
7557 |
return; |
| 7558 |
break; |
7558 |
break; |
| 7559 |
case 20: |
7559 |
case 20: |
| 7560 |
// TEQ, TGE, TGEU, TLT, TLTU, TNE |
7560 |
// TEQ, TGE, TGEU, TLT, TLTU, TNE |
| 7561 |
printUImm<10>(MI, 2, STI, O); |
7561 |
printUImm<10>(MI, 2, STI, O); |
| 7562 |
return; |
7562 |
return; |
| 7563 |
break; |
7563 |
break; |
| 7564 |
} |
7564 |
} |
| 7565 |
|
7565 |
|
| 7566 |
|
7566 |
|
| 7567 |
// Fragment 5 encoded into 3 bits for 5 unique commands. |
7567 |
// Fragment 5 encoded into 3 bits for 5 unique commands. |
| 7568 |
switch ((Bits >> 39) & 7) { |
7568 |
switch ((Bits >> 39) & 7) { |
| 7569 |
default: llvm_unreachable("Invalid command number."); |
7569 |
default: llvm_unreachable("Invalid command number."); |
| 7570 |
case 0: |
7570 |
case 0: |
| 7571 |
// DMULImmMacro, DMULMacro, DMULOMacro, DMULOUMacro, DROL, DROLImm, DROR,... |
7571 |
// DMULImmMacro, DMULMacro, DMULOMacro, DMULOUMacro, DROL, DROLImm, DROR,... |
| 7572 |
return; |
7572 |
return; |
| 7573 |
break; |
7573 |
break; |
| 7574 |
case 1: |
7574 |
case 1: |
| 7575 |
// ALIGN, ALIGN_MMR6, CINS, CINS32, CINS64_32, CINS_i32, DALIGN, DEXT, DE... |
7575 |
// ALIGN, ALIGN_MMR6, CINS, CINS32, CINS64_32, CINS_i32, DALIGN, DEXT, DE... |
| 7576 |
O << ", "; |
7576 |
O << ", "; |
| 7577 |
break; |
7577 |
break; |
| 7578 |
case 2: |
7578 |
case 2: |
| 7579 |
// COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ... |
7579 |
// COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ... |
| 7580 |
O << ']'; |
7580 |
O << ']'; |
| 7581 |
return; |
7581 |
return; |
| 7582 |
break; |
7582 |
break; |
| 7583 |
case 3: |
7583 |
case 3: |
| 7584 |
// DEXTU |
7584 |
// DEXTU |
| 7585 |
printUImm<5, 1>(MI, 3, STI, O); |
7585 |
printUImm<5, 1>(MI, 3, STI, O); |
| 7586 |
return; |
7586 |
return; |
| 7587 |
break; |
7587 |
break; |
| 7588 |
case 4: |
7588 |
case 4: |
| 7589 |
// DINSU |
7589 |
// DINSU |
| 7590 |
printUImm<6>(MI, 3, STI, O); |
7590 |
printUImm<6>(MI, 3, STI, O); |
| 7591 |
return; |
7591 |
return; |
| 7592 |
break; |
7592 |
break; |
| 7593 |
} |
7593 |
} |
| 7594 |
|
7594 |
|
| 7595 |
|
7595 |
|
| 7596 |
// Fragment 6 encoded into 4 bits for 10 unique commands. |
7596 |
// Fragment 6 encoded into 4 bits for 10 unique commands. |
| 7597 |
switch ((Bits >> 42) & 15) { |
7597 |
switch ((Bits >> 42) & 15) { |
| 7598 |
default: llvm_unreachable("Invalid command number."); |
7598 |
default: llvm_unreachable("Invalid command number."); |
| 7599 |
case 0: |
7599 |
case 0: |
| 7600 |
// ALIGN, ALIGN_MMR6 |
7600 |
// ALIGN, ALIGN_MMR6 |
| 7601 |
printUImm<2>(MI, 3, STI, O); |
7601 |
printUImm<2>(MI, 3, STI, O); |
| 7602 |
return; |
7602 |
return; |
| 7603 |
break; |
7603 |
break; |
| 7604 |
case 1: |
7604 |
case 1: |
| 7605 |
// CINS, CINS32, CINS64_32, CINS_i32, EXTS, EXTS32 |
7605 |
// CINS, CINS32, CINS64_32, CINS_i32, EXTS, EXTS32 |
| 7606 |
printUImm<5>(MI, 3, STI, O); |
7606 |
printUImm<5>(MI, 3, STI, O); |
| 7607 |
return; |
7607 |
return; |
| 7608 |
break; |
7608 |
break; |
| 7609 |
case 2: |
7609 |
case 2: |
| 7610 |
// DALIGN, MFTR |
7610 |
// DALIGN, MFTR |
| 7611 |
printUImm<3>(MI, 3, STI, O); |
7611 |
printUImm<3>(MI, 3, STI, O); |
| 7612 |
break; |
7612 |
break; |
| 7613 |
case 3: |
7613 |
case 3: |
| 7614 |
// DEXT |
7614 |
// DEXT |
| 7615 |
printUImm<6, 1>(MI, 3, STI, O); |
7615 |
printUImm<6, 1>(MI, 3, STI, O); |
| 7616 |
return; |
7616 |
return; |
| 7617 |
break; |
7617 |
break; |
| 7618 |
case 4: |
7618 |
case 4: |
| 7619 |
// DEXT64_32, EXT, EXT_MM, EXT_MMR6 |
7619 |
// DEXT64_32, EXT, EXT_MM, EXT_MMR6 |
| 7620 |
printUImm<5, 1>(MI, 3, STI, O); |
7620 |
printUImm<5, 1>(MI, 3, STI, O); |
| 7621 |
return; |
7621 |
return; |
| 7622 |
break; |
7622 |
break; |
| 7623 |
case 5: |
7623 |
case 5: |
| 7624 |
// DEXTM |
7624 |
// DEXTM |
| 7625 |
printUImm<5, 33>(MI, 3, STI, O); |
7625 |
printUImm<5, 33>(MI, 3, STI, O); |
| 7626 |
return; |
7626 |
return; |
| 7627 |
break; |
7627 |
break; |
| 7628 |
case 6: |
7628 |
case 6: |
| 7629 |
// DINS, INS, INS_MM, INS_MMR6 |
7629 |
// DINS, INS, INS_MM, INS_MMR6 |
| 7630 |
printUImm<6>(MI, 3, STI, O); |
7630 |
printUImm<6>(MI, 3, STI, O); |
| 7631 |
return; |
7631 |
return; |
| 7632 |
break; |
7632 |
break; |
| 7633 |
case 7: |
7633 |
case 7: |
| 7634 |
// DINSM |
7634 |
// DINSM |
| 7635 |
printUImm<6, 2>(MI, 3, STI, O); |
7635 |
printUImm<6, 2>(MI, 3, STI, O); |
| 7636 |
return; |
7636 |
return; |
| 7637 |
break; |
7637 |
break; |
| 7638 |
case 8: |
7638 |
case 8: |
| 7639 |
// DLSA, DLSA_R6, LSA, LSA_R6 |
7639 |
// DLSA, DLSA_R6, LSA, LSA_R6 |
| 7640 |
printUImm<2, 1>(MI, 3, STI, O); |
7640 |
printUImm<2, 1>(MI, 3, STI, O); |
| 7641 |
return; |
7641 |
return; |
| 7642 |
break; |
7642 |
break; |
| 7643 |
case 9: |
7643 |
case 9: |
| 7644 |
// MADD_D32, MADD_D32_MM, MADD_D64, MADD_S, MADD_S_MM, MOVEP_MM, MOVEP_MM... |
7644 |
// MADD_D32, MADD_D32_MM, MADD_D64, MADD_S, MADD_S_MM, MOVEP_MM, MOVEP_MM... |
| 7645 |
printOperand(MI, 3, STI, O); |
7645 |
printOperand(MI, 3, STI, O); |
| 7646 |
return; |
7646 |
return; |
| 7647 |
break; |
7647 |
break; |
| 7648 |
} |
7648 |
} |
| 7649 |
|
7649 |
|
| 7650 |
|
7650 |
|
| 7651 |
// Fragment 7 encoded into 1 bits for 2 unique commands. |
7651 |
// Fragment 7 encoded into 1 bits for 2 unique commands. |
| 7652 |
if ((Bits >> 46) & 1) { |
7652 |
if ((Bits >> 46) & 1) { |
| 7653 |
// MFTR |
7653 |
// MFTR |
| 7654 |
O << ", "; |
7654 |
O << ", "; |
| 7655 |
printUImm<1>(MI, 4, STI, O); |
7655 |
printUImm<1>(MI, 4, STI, O); |
| 7656 |
return; |
7656 |
return; |
| 7657 |
} else { |
7657 |
} else { |
| 7658 |
// DALIGN |
7658 |
// DALIGN |
| 7659 |
return; |
7659 |
return; |
| 7660 |
} |
7660 |
} |
| 7661 |
|
7661 |
|
| 7662 |
} |
7662 |
} |
| 7663 |
|
7663 |
|
| 7664 |
|
7664 |
|
| 7665 |
/// getRegisterName - This method is automatically generated by tblgen |
7665 |
/// getRegisterName - This method is automatically generated by tblgen |
| 7666 |
/// from the register set description. This returns the assembler name |
7666 |
/// from the register set description. This returns the assembler name |
| 7667 |
/// for the specified register. |
7667 |
/// for the specified register. |
| 7668 |
const char *MipsInstPrinter::getRegisterName(MCRegister Reg) { |
7668 |
const char *MipsInstPrinter::getRegisterName(MCRegister Reg) { |
| 7669 |
unsigned RegNo = Reg.id(); |
7669 |
unsigned RegNo = Reg.id(); |
| 7670 |
assert(RegNo && RegNo < 442 && "Invalid register number!"); |
7670 |
assert(RegNo && RegNo < 442 && "Invalid register number!"); |
| 7671 |
|
7671 |
|
| 7672 |
|
7672 |
|
| 7673 |
#ifdef __GNUC__ |
7673 |
#ifdef __GNUC__ |
| 7674 |
#pragma GCC diagnostic push |
7674 |
#pragma GCC diagnostic push |
| 7675 |
#pragma GCC diagnostic ignored "-Woverlength-strings" |
7675 |
#pragma GCC diagnostic ignored "-Woverlength-strings" |
| 7676 |
#endif |
7676 |
#endif |
| 7677 |
static const char AsmStrs[] = { |
7677 |
static const char AsmStrs[] = { |
| 7678 |
/* 0 */ "f10\0" |
7678 |
/* 0 */ "f10\0" |
| 7679 |
/* 4 */ "w10\0" |
7679 |
/* 4 */ "w10\0" |
| 7680 |
/* 8 */ "f20\0" |
7680 |
/* 8 */ "f20\0" |
| 7681 |
/* 12 */ "DSPOutFlag20\0" |
7681 |
/* 12 */ "DSPOutFlag20\0" |
| 7682 |
/* 25 */ "w20\0" |
7682 |
/* 25 */ "w20\0" |
| 7683 |
/* 29 */ "f30\0" |
7683 |
/* 29 */ "f30\0" |
| 7684 |
/* 33 */ "w30\0" |
7684 |
/* 33 */ "w30\0" |
| 7685 |
/* 37 */ "ac0\0" |
7685 |
/* 37 */ "ac0\0" |
| 7686 |
/* 41 */ "fcc0\0" |
7686 |
/* 41 */ "fcc0\0" |
| 7687 |
/* 46 */ "f0\0" |
7687 |
/* 46 */ "f0\0" |
| 7688 |
/* 49 */ "mpl0\0" |
7688 |
/* 49 */ "mpl0\0" |
| 7689 |
/* 54 */ "p0\0" |
7689 |
/* 54 */ "p0\0" |
| 7690 |
/* 57 */ "w0\0" |
7690 |
/* 57 */ "w0\0" |
| 7691 |
/* 60 */ "f11\0" |
7691 |
/* 60 */ "f11\0" |
| 7692 |
/* 64 */ "w11\0" |
7692 |
/* 64 */ "w11\0" |
| 7693 |
/* 68 */ "f21\0" |
7693 |
/* 68 */ "f21\0" |
| 7694 |
/* 72 */ "DSPOutFlag21\0" |
7694 |
/* 72 */ "DSPOutFlag21\0" |
| 7695 |
/* 85 */ "w21\0" |
7695 |
/* 85 */ "w21\0" |
| 7696 |
/* 89 */ "f31\0" |
7696 |
/* 89 */ "f31\0" |
| 7697 |
/* 93 */ "w31\0" |
7697 |
/* 93 */ "w31\0" |
| 7698 |
/* 97 */ "ac1\0" |
7698 |
/* 97 */ "ac1\0" |
| 7699 |
/* 101 */ "fcc1\0" |
7699 |
/* 101 */ "fcc1\0" |
| 7700 |
/* 106 */ "f1\0" |
7700 |
/* 106 */ "f1\0" |
| 7701 |
/* 109 */ "mpl1\0" |
7701 |
/* 109 */ "mpl1\0" |
| 7702 |
/* 114 */ "p1\0" |
7702 |
/* 114 */ "p1\0" |
| 7703 |
/* 117 */ "w1\0" |
7703 |
/* 117 */ "w1\0" |
| 7704 |
/* 120 */ "f12\0" |
7704 |
/* 120 */ "f12\0" |
| 7705 |
/* 124 */ "w12\0" |
7705 |
/* 124 */ "w12\0" |
| 7706 |
/* 128 */ "f22\0" |
7706 |
/* 128 */ "f22\0" |
| 7707 |
/* 132 */ "DSPOutFlag22\0" |
7707 |
/* 132 */ "DSPOutFlag22\0" |
| 7708 |
/* 145 */ "w22\0" |
7708 |
/* 145 */ "w22\0" |
| 7709 |
/* 149 */ "ac2\0" |
7709 |
/* 149 */ "ac2\0" |
| 7710 |
/* 153 */ "fcc2\0" |
7710 |
/* 153 */ "fcc2\0" |
| 7711 |
/* 158 */ "f2\0" |
7711 |
/* 158 */ "f2\0" |
| 7712 |
/* 161 */ "mpl2\0" |
7712 |
/* 161 */ "mpl2\0" |
| 7713 |
/* 166 */ "p2\0" |
7713 |
/* 166 */ "p2\0" |
| 7714 |
/* 169 */ "w2\0" |
7714 |
/* 169 */ "w2\0" |
| 7715 |
/* 172 */ "f13\0" |
7715 |
/* 172 */ "f13\0" |
| 7716 |
/* 176 */ "w13\0" |
7716 |
/* 176 */ "w13\0" |
| 7717 |
/* 180 */ "f23\0" |
7717 |
/* 180 */ "f23\0" |
| 7718 |
/* 184 */ "DSPOutFlag23\0" |
7718 |
/* 184 */ "DSPOutFlag23\0" |
| 7719 |
/* 197 */ "w23\0" |
7719 |
/* 197 */ "w23\0" |
| 7720 |
/* 201 */ "ac3\0" |
7720 |
/* 201 */ "ac3\0" |
| 7721 |
/* 205 */ "fcc3\0" |
7721 |
/* 205 */ "fcc3\0" |
| 7722 |
/* 210 */ "f3\0" |
7722 |
/* 210 */ "f3\0" |
| 7723 |
/* 213 */ "w3\0" |
7723 |
/* 213 */ "w3\0" |
| 7724 |
/* 216 */ "f14\0" |
7724 |
/* 216 */ "f14\0" |
| 7725 |
/* 220 */ "w14\0" |
7725 |
/* 220 */ "w14\0" |
| 7726 |
/* 224 */ "f24\0" |
7726 |
/* 224 */ "f24\0" |
| 7727 |
/* 228 */ "w24\0" |
7727 |
/* 228 */ "w24\0" |
| 7728 |
/* 232 */ "fcc4\0" |
7728 |
/* 232 */ "fcc4\0" |
| 7729 |
/* 237 */ "f4\0" |
7729 |
/* 237 */ "f4\0" |
| 7730 |
/* 240 */ "w4\0" |
7730 |
/* 240 */ "w4\0" |
| 7731 |
/* 243 */ "f15\0" |
7731 |
/* 243 */ "f15\0" |
| 7732 |
/* 247 */ "w15\0" |
7732 |
/* 247 */ "w15\0" |
| 7733 |
/* 251 */ "f25\0" |
7733 |
/* 251 */ "f25\0" |
| 7734 |
/* 255 */ "w25\0" |
7734 |
/* 255 */ "w25\0" |
| 7735 |
/* 259 */ "fcc5\0" |
7735 |
/* 259 */ "fcc5\0" |
| 7736 |
/* 264 */ "f5\0" |
7736 |
/* 264 */ "f5\0" |
| 7737 |
/* 267 */ "w5\0" |
7737 |
/* 267 */ "w5\0" |
| 7738 |
/* 270 */ "f16\0" |
7738 |
/* 270 */ "f16\0" |
| 7739 |
/* 274 */ "w16\0" |
7739 |
/* 274 */ "w16\0" |
| 7740 |
/* 278 */ "f26\0" |
7740 |
/* 278 */ "f26\0" |
| 7741 |
/* 282 */ "w26\0" |
7741 |
/* 282 */ "w26\0" |
| 7742 |
/* 286 */ "fcc6\0" |
7742 |
/* 286 */ "fcc6\0" |
| 7743 |
/* 291 */ "f6\0" |
7743 |
/* 291 */ "f6\0" |
| 7744 |
/* 294 */ "w6\0" |
7744 |
/* 294 */ "w6\0" |
| 7745 |
/* 297 */ "f17\0" |
7745 |
/* 297 */ "f17\0" |
| 7746 |
/* 301 */ "w17\0" |
7746 |
/* 301 */ "w17\0" |
| 7747 |
/* 305 */ "f27\0" |
7747 |
/* 305 */ "f27\0" |
| 7748 |
/* 309 */ "w27\0" |
7748 |
/* 309 */ "w27\0" |
| 7749 |
/* 313 */ "fcc7\0" |
7749 |
/* 313 */ "fcc7\0" |
| 7750 |
/* 318 */ "f7\0" |
7750 |
/* 318 */ "f7\0" |
| 7751 |
/* 321 */ "w7\0" |
7751 |
/* 321 */ "w7\0" |
| 7752 |
/* 324 */ "f18\0" |
7752 |
/* 324 */ "f18\0" |
| 7753 |
/* 328 */ "w18\0" |
7753 |
/* 328 */ "w18\0" |
| 7754 |
/* 332 */ "f28\0" |
7754 |
/* 332 */ "f28\0" |
| 7755 |
/* 336 */ "w28\0" |
7755 |
/* 336 */ "w28\0" |
| 7756 |
/* 340 */ "f8\0" |
7756 |
/* 340 */ "f8\0" |
| 7757 |
/* 343 */ "w8\0" |
7757 |
/* 343 */ "w8\0" |
| 7758 |
/* 346 */ "DSPOutFlag16_19\0" |
7758 |
/* 346 */ "DSPOutFlag16_19\0" |
| 7759 |
/* 362 */ "f19\0" |
7759 |
/* 362 */ "f19\0" |
| 7760 |
/* 366 */ "w19\0" |
7760 |
/* 366 */ "w19\0" |
| 7761 |
/* 370 */ "f29\0" |
7761 |
/* 370 */ "f29\0" |
| 7762 |
/* 374 */ "w29\0" |
7762 |
/* 374 */ "w29\0" |
| 7763 |
/* 378 */ "f9\0" |
7763 |
/* 378 */ "f9\0" |
| 7764 |
/* 381 */ "w9\0" |
7764 |
/* 381 */ "w9\0" |
| 7765 |
/* 384 */ "DSPEFI\0" |
7765 |
/* 384 */ "DSPEFI\0" |
| 7766 |
/* 391 */ "ra\0" |
7766 |
/* 391 */ "ra\0" |
| 7767 |
/* 394 */ "hwr_cc\0" |
7767 |
/* 394 */ "hwr_cc\0" |
| 7768 |
/* 401 */ "pc\0" |
7768 |
/* 401 */ "pc\0" |
| 7769 |
/* 404 */ "DSPCCond\0" |
7769 |
/* 404 */ "DSPCCond\0" |
| 7770 |
/* 413 */ "DSPOutFlag\0" |
7770 |
/* 413 */ "DSPOutFlag\0" |
| 7771 |
/* 424 */ "hi\0" |
7771 |
/* 424 */ "hi\0" |
| 7772 |
/* 427 */ "hwr_cpunum\0" |
7772 |
/* 427 */ "hwr_cpunum\0" |
| 7773 |
/* 438 */ "lo\0" |
7773 |
/* 438 */ "lo\0" |
| 7774 |
/* 441 */ "zero\0" |
7774 |
/* 441 */ "zero\0" |
| 7775 |
/* 446 */ "hwr_synci_step\0" |
7775 |
/* 446 */ "hwr_synci_step\0" |
| 7776 |
/* 461 */ "fp\0" |
7776 |
/* 461 */ "fp\0" |
| 7777 |
/* 464 */ "gp\0" |
7777 |
/* 464 */ "gp\0" |
| 7778 |
/* 467 */ "sp\0" |
7778 |
/* 467 */ "sp\0" |
| 7779 |
/* 470 */ "hwr_ccres\0" |
7779 |
/* 470 */ "hwr_ccres\0" |
| 7780 |
/* 480 */ "DSPPos\0" |
7780 |
/* 480 */ "DSPPos\0" |
| 7781 |
/* 487 */ "DSPSCount\0" |
7781 |
/* 487 */ "DSPSCount\0" |
| 7782 |
/* 497 */ "DSPCarry\0" |
7782 |
/* 497 */ "DSPCarry\0" |
| 7783 |
}; |
7783 |
}; |
| 7784 |
#ifdef __GNUC__ |
7784 |
#ifdef __GNUC__ |
| 7785 |
#pragma GCC diagnostic pop |
7785 |
#pragma GCC diagnostic pop |
| 7786 |
#endif |
7786 |
#endif |
| 7787 |
|
7787 |
|
| 7788 |
static const uint16_t RegAsmOffset[] = { |
7788 |
static const uint16_t RegAsmOffset[] = { |
| 7789 |
62, 404, 497, 384, 413, 480, 487, 461, 464, 122, 62, 2, 272, 218, |
7789 |
62, 404, 497, 384, 413, 480, 487, 461, 464, 122, 62, 2, 272, 218, |
| 7790 |
245, 174, 299, 401, 391, 467, 441, 218, 245, 272, 299, 37, 97, 149, |
7790 |
245, 174, 299, 401, 391, 467, 441, 218, 245, 272, 299, 37, 97, 149, |
| 7791 |
201, 62, 2, 62, 122, 174, 218, 245, 272, 299, 326, 360, 2, 62, |
7791 |
201, 62, 2, 62, 122, 174, 218, 245, 272, 299, 326, 360, 2, 62, |
| 7792 |
122, 174, 218, 245, 272, 299, 326, 360, 2, 62, 122, 174, 218, 245, |
7792 |
122, 174, 218, 245, 272, 299, 326, 360, 2, 62, 122, 174, 218, 245, |
| 7793 |
272, 299, 326, 360, 1, 61, 121, 173, 217, 244, 271, 298, 325, 359, |
7793 |
272, 299, 326, 360, 1, 61, 121, 173, 217, 244, 271, 298, 325, 359, |
| 7794 |
9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, 1, 61, |
7794 |
9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, 1, 61, |
| 7795 |
121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 225, 252, |
7795 |
121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 225, 252, |
| 7796 |
279, 306, 333, 371, 30, 90, 1, 61, 121, 173, 217, 244, 271, 298, |
7796 |
279, 306, 333, 371, 30, 90, 1, 61, 121, 173, 217, 244, 271, 298, |
| 7797 |
325, 359, 9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, |
7797 |
325, 359, 9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, |
| 7798 |
46, 158, 237, 291, 340, 0, 120, 216, 270, 324, 8, 128, 224, 278, |
7798 |
46, 158, 237, 291, 340, 0, 120, 216, 270, 324, 8, 128, 224, 278, |
| 7799 |
332, 29, 12, 72, 132, 184, 46, 106, 158, 210, 237, 264, 291, 318, |
7799 |
332, 29, 12, 72, 132, 184, 46, 106, 158, 210, 237, 264, 291, 318, |
| 7800 |
340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 362, 8, 68, |
7800 |
340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 362, 8, 68, |
| 7801 |
128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 41, 101, 153, 205, |
7801 |
128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 41, 101, 153, 205, |
| 7802 |
232, 259, 286, 313, 2, 62, 122, 174, 218, 245, 272, 299, 326, 360, |
7802 |
232, 259, 286, 313, 2, 62, 122, 174, 218, 245, 272, 299, 326, 360, |
| 7803 |
1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, |
7803 |
1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, |
| 7804 |
225, 252, 279, 306, 333, 371, 30, 90, 461, 46, 106, 158, 210, 237, |
7804 |
225, 252, 279, 306, 333, 371, 30, 90, 461, 46, 106, 158, 210, 237, |
| 7805 |
264, 291, 318, 340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, |
7805 |
264, 291, 318, 340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, |
| 7806 |
362, 8, 68, 128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 464, |
7806 |
362, 8, 68, 128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 464, |
| 7807 |
37, 97, 149, 201, 427, 446, 394, 470, 218, 245, 272, 299, 326, 360, |
7807 |
37, 97, 149, 201, 427, 446, 394, 470, 218, 245, 272, 299, 326, 360, |
| 7808 |
1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, |
7808 |
1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, |
| 7809 |
225, 252, 279, 306, 333, 371, 30, 90, 279, 306, 37, 97, 149, 201, |
7809 |
225, 252, 279, 306, 333, 371, 30, 90, 279, 306, 37, 97, 149, 201, |
| 7810 |
49, 109, 161, 326, 360, 1, 61, 121, 173, 217, 244, 271, 298, 325, |
7810 |
49, 109, 161, 326, 360, 1, 61, 121, 173, 217, 244, 271, 298, 325, |
| 7811 |
359, 9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, 54, |
7811 |
359, 9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, 54, |
| 7812 |
114, 166, 391, 271, 298, 325, 359, 9, 69, 129, 181, 467, 326, 360, |
7812 |
114, 166, 391, 271, 298, 325, 359, 9, 69, 129, 181, 467, 326, 360, |
| 7813 |
1, 61, 121, 173, 217, 244, 225, 252, 122, 174, 57, 117, 169, 213, |
7813 |
1, 61, 121, 173, 217, 244, 225, 252, 122, 174, 57, 117, 169, 213, |
| 7814 |
240, 267, 294, 321, 343, 381, 4, 64, 124, 176, 220, 247, 274, 301, |
7814 |
240, 267, 294, 321, 343, 381, 4, 64, 124, 176, 220, 247, 274, 301, |
| 7815 |
328, 366, 25, 85, 145, 197, 228, 255, 282, 309, 336, 374, 33, 93, |
7815 |
328, 366, 25, 85, 145, 197, 228, 255, 282, 309, 336, 374, 33, 93, |
| 7816 |
441, 218, 245, 272, 299, 37, 46, 106, 158, 210, 237, 264, 291, 318, |
7816 |
441, 218, 245, 272, 299, 37, 46, 106, 158, 210, 237, 264, 291, 318, |
| 7817 |
340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 362, 8, 68, |
7817 |
340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 362, 8, 68, |
| 7818 |
128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 346, 424, 279, 306, |
7818 |
128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 346, 424, 279, 306, |
| 7819 |
438, 271, 298, 325, 359, 9, 69, 129, 181, 326, 360, 1, 61, 121, |
7819 |
438, 271, 298, 325, 359, 9, 69, 129, 181, 326, 360, 1, 61, 121, |
| 7820 |
173, 217, 244, 225, 252, 122, 174, |
7820 |
173, 217, 244, 225, 252, 122, 174, |
| 7821 |
}; |
7821 |
}; |
| 7822 |
|
7822 |
|
| 7823 |
assert (*(AsmStrs+RegAsmOffset[RegNo-1]) && |
7823 |
assert (*(AsmStrs+RegAsmOffset[RegNo-1]) && |
| 7824 |
"Invalid alt name index for register!"); |
7824 |
"Invalid alt name index for register!"); |
| 7825 |
return AsmStrs+RegAsmOffset[RegNo-1]; |
7825 |
return AsmStrs+RegAsmOffset[RegNo-1]; |
| 7826 |
} |
7826 |
} |
| 7827 |
|
7827 |
|
| 7828 |
#ifdef PRINT_ALIAS_INSTR |
7828 |
#ifdef PRINT_ALIAS_INSTR |
| 7829 |
#undef PRINT_ALIAS_INSTR |
7829 |
#undef PRINT_ALIAS_INSTR |
| 7830 |
|
7830 |
|
| 7831 |
bool MipsInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) { |
7831 |
bool MipsInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) { |
| 7832 |
static const PatternsForOpcode OpToPatterns[] = { |
7832 |
static const PatternsForOpcode OpToPatterns[] = { |
| 7833 |
{Mips::MFTACX, 0, 1 }, |
7833 |
{Mips::MFTACX, 0, 1 }, |
| 7834 |
{Mips::MFTC0, 1, 1 }, |
7834 |
{Mips::MFTC0, 1, 1 }, |
| 7835 |
{Mips::MFTHI, 2, 1 }, |
7835 |
{Mips::MFTHI, 2, 1 }, |
| 7836 |
{Mips::MFTLO, 3, 1 }, |
7836 |
{Mips::MFTLO, 3, 1 }, |
| 7837 |
{Mips::MTTACX, 4, 1 }, |
7837 |
{Mips::MTTACX, 4, 1 }, |
| 7838 |
{Mips::MTTC0, 5, 1 }, |
7838 |
{Mips::MTTC0, 5, 1 }, |
| 7839 |
{Mips::MTTHI, 6, 1 }, |
7839 |
{Mips::MTTHI, 6, 1 }, |
| 7840 |
{Mips::MTTLO, 7, 1 }, |
7840 |
{Mips::MTTLO, 7, 1 }, |
| 7841 |
{Mips::NORImm, 8, 1 }, |
7841 |
{Mips::NORImm, 8, 1 }, |
| 7842 |
{Mips::NORImm64, 9, 1 }, |
7842 |
{Mips::NORImm64, 9, 1 }, |
| 7843 |
{Mips::SLTImm64, 10, 1 }, |
7843 |
{Mips::SLTImm64, 10, 1 }, |
| 7844 |
{Mips::SLTUImm64, 11, 1 }, |
7844 |
{Mips::SLTUImm64, 11, 1 }, |
| 7845 |
{Mips::ADDIUPC, 12, 1 }, |
7845 |
{Mips::ADDIUPC, 12, 1 }, |
| 7846 |
{Mips::ADDIUPC_MMR6, 13, 1 }, |
7846 |
{Mips::ADDIUPC_MMR6, 13, 1 }, |
| 7847 |
{Mips::ADDu, 14, 1 }, |
7847 |
{Mips::ADDu, 14, 1 }, |
| 7848 |
{Mips::BC1F, 15, 1 }, |
7848 |
{Mips::BC1F, 15, 1 }, |
| 7849 |
{Mips::BC1FL, 16, 1 }, |
7849 |
{Mips::BC1FL, 16, 1 }, |
| 7850 |
{Mips::BC1F_MM, 17, 1 }, |
7850 |
{Mips::BC1F_MM, 17, 1 }, |
| 7851 |
{Mips::BC1T, 18, 1 }, |
7851 |
{Mips::BC1T, 18, 1 }, |
| 7852 |
{Mips::BC1TL, 19, 1 }, |
7852 |
{Mips::BC1TL, 19, 1 }, |
| 7853 |
{Mips::BC1T_MM, 20, 1 }, |
7853 |
{Mips::BC1T_MM, 20, 1 }, |
| 7854 |
{Mips::BEQL, 21, 1 }, |
7854 |
{Mips::BEQL, 21, 1 }, |
| 7855 |
{Mips::BGEZAL, 22, 1 }, |
7855 |
{Mips::BGEZAL, 22, 1 }, |
| 7856 |
{Mips::BGEZAL_MM, 23, 1 }, |
7856 |
{Mips::BGEZAL_MM, 23, 1 }, |
| 7857 |
{Mips::BNEL, 24, 1 }, |
7857 |
{Mips::BNEL, 24, 1 }, |
| 7858 |
{Mips::BREAK, 25, 2 }, |
7858 |
{Mips::BREAK, 25, 2 }, |
| 7859 |
{Mips::BREAK_MM, 27, 2 }, |
7859 |
{Mips::BREAK_MM, 27, 2 }, |
| 7860 |
{Mips::C_EQ_D32, 29, 1 }, |
7860 |
{Mips::C_EQ_D32, 29, 1 }, |
| 7861 |
{Mips::C_EQ_D32_MM, 30, 1 }, |
7861 |
{Mips::C_EQ_D32_MM, 30, 1 }, |
| 7862 |
{Mips::C_EQ_D64, 31, 1 }, |
7862 |
{Mips::C_EQ_D64, 31, 1 }, |
| 7863 |
{Mips::C_EQ_D64_MM, 32, 1 }, |
7863 |
{Mips::C_EQ_D64_MM, 32, 1 }, |
| 7864 |
{Mips::C_EQ_S, 33, 1 }, |
7864 |
{Mips::C_EQ_S, 33, 1 }, |
| 7865 |
{Mips::C_EQ_S_MM, 34, 1 }, |
7865 |
{Mips::C_EQ_S_MM, 34, 1 }, |
| 7866 |
{Mips::C_F_D32, 35, 1 }, |
7866 |
{Mips::C_F_D32, 35, 1 }, |
| 7867 |
{Mips::C_F_D32_MM, 36, 1 }, |
7867 |
{Mips::C_F_D32_MM, 36, 1 }, |
| 7868 |
{Mips::C_F_D64, 37, 1 }, |
7868 |
{Mips::C_F_D64, 37, 1 }, |
| 7869 |
{Mips::C_F_D64_MM, 38, 1 }, |
7869 |
{Mips::C_F_D64_MM, 38, 1 }, |
| 7870 |
{Mips::C_F_S, 39, 1 }, |
7870 |
{Mips::C_F_S, 39, 1 }, |
| 7871 |
{Mips::C_F_S_MM, 40, 1 }, |
7871 |
{Mips::C_F_S_MM, 40, 1 }, |
| 7872 |
{Mips::C_LE_D32, 41, 1 }, |
7872 |
{Mips::C_LE_D32, 41, 1 }, |
| 7873 |
{Mips::C_LE_D32_MM, 42, 1 }, |
7873 |
{Mips::C_LE_D32_MM, 42, 1 }, |
| 7874 |
{Mips::C_LE_D64, 43, 1 }, |
7874 |
{Mips::C_LE_D64, 43, 1 }, |
| 7875 |
{Mips::C_LE_D64_MM, 44, 1 }, |
7875 |
{Mips::C_LE_D64_MM, 44, 1 }, |
| 7876 |
{Mips::C_LE_S, 45, 1 }, |
7876 |
{Mips::C_LE_S, 45, 1 }, |
| 7877 |
{Mips::C_LE_S_MM, 46, 1 }, |
7877 |
{Mips::C_LE_S_MM, 46, 1 }, |
| 7878 |
{Mips::C_LT_D32, 47, 1 }, |
7878 |
{Mips::C_LT_D32, 47, 1 }, |
| 7879 |
{Mips::C_LT_D32_MM, 48, 1 }, |
7879 |
{Mips::C_LT_D32_MM, 48, 1 }, |
| 7880 |
{Mips::C_LT_D64, 49, 1 }, |
7880 |
{Mips::C_LT_D64, 49, 1 }, |
| 7881 |
{Mips::C_LT_D64_MM, 50, 1 }, |
7881 |
{Mips::C_LT_D64_MM, 50, 1 }, |
| 7882 |
{Mips::C_LT_S, 51, 1 }, |
7882 |
{Mips::C_LT_S, 51, 1 }, |
| 7883 |
{Mips::C_LT_S_MM, 52, 1 }, |
7883 |
{Mips::C_LT_S_MM, 52, 1 }, |
| 7884 |
{Mips::C_NGE_D32, 53, 1 }, |
7884 |
{Mips::C_NGE_D32, 53, 1 }, |
| 7885 |
{Mips::C_NGE_D32_MM, 54, 1 }, |
7885 |
{Mips::C_NGE_D32_MM, 54, 1 }, |
| 7886 |
{Mips::C_NGE_D64, 55, 1 }, |
7886 |
{Mips::C_NGE_D64, 55, 1 }, |
| 7887 |
{Mips::C_NGE_D64_MM, 56, 1 }, |
7887 |
{Mips::C_NGE_D64_MM, 56, 1 }, |
| 7888 |
{Mips::C_NGE_S, 57, 1 }, |
7888 |
{Mips::C_NGE_S, 57, 1 }, |
| 7889 |
{Mips::C_NGE_S_MM, 58, 1 }, |
7889 |
{Mips::C_NGE_S_MM, 58, 1 }, |
| 7890 |
{Mips::C_NGLE_D32, 59, 1 }, |
7890 |
{Mips::C_NGLE_D32, 59, 1 }, |
| 7891 |
{Mips::C_NGLE_D32_MM, 60, 1 }, |
7891 |
{Mips::C_NGLE_D32_MM, 60, 1 }, |
| 7892 |
{Mips::C_NGLE_D64, 61, 1 }, |
7892 |
{Mips::C_NGLE_D64, 61, 1 }, |
| 7893 |
{Mips::C_NGLE_D64_MM, 62, 1 }, |
7893 |
{Mips::C_NGLE_D64_MM, 62, 1 }, |
| 7894 |
{Mips::C_NGLE_S, 63, 1 }, |
7894 |
{Mips::C_NGLE_S, 63, 1 }, |
| 7895 |
{Mips::C_NGLE_S_MM, 64, 1 }, |
7895 |
{Mips::C_NGLE_S_MM, 64, 1 }, |
| 7896 |
{Mips::C_NGL_D32, 65, 1 }, |
7896 |
{Mips::C_NGL_D32, 65, 1 }, |
| 7897 |
{Mips::C_NGL_D32_MM, 66, 1 }, |
7897 |
{Mips::C_NGL_D32_MM, 66, 1 }, |
| 7898 |
{Mips::C_NGL_D64, 67, 1 }, |
7898 |
{Mips::C_NGL_D64, 67, 1 }, |
| 7899 |
{Mips::C_NGL_D64_MM, 68, 1 }, |
7899 |
{Mips::C_NGL_D64_MM, 68, 1 }, |
| 7900 |
{Mips::C_NGL_S, 69, 1 }, |
7900 |
{Mips::C_NGL_S, 69, 1 }, |
| 7901 |
{Mips::C_NGL_S_MM, 70, 1 }, |
7901 |
{Mips::C_NGL_S_MM, 70, 1 }, |
| 7902 |
{Mips::C_NGT_D32, 71, 1 }, |
7902 |
{Mips::C_NGT_D32, 71, 1 }, |
| 7903 |
{Mips::C_NGT_D32_MM, 72, 1 }, |
7903 |
{Mips::C_NGT_D32_MM, 72, 1 }, |
| 7904 |
{Mips::C_NGT_D64, 73, 1 }, |
7904 |
{Mips::C_NGT_D64, 73, 1 }, |
| 7905 |
{Mips::C_NGT_D64_MM, 74, 1 }, |
7905 |
{Mips::C_NGT_D64_MM, 74, 1 }, |
| 7906 |
{Mips::C_NGT_S, 75, 1 }, |
7906 |
{Mips::C_NGT_S, 75, 1 }, |
| 7907 |
{Mips::C_NGT_S_MM, 76, 1 }, |
7907 |
{Mips::C_NGT_S_MM, 76, 1 }, |
| 7908 |
{Mips::C_OLE_D32, 77, 1 }, |
7908 |
{Mips::C_OLE_D32, 77, 1 }, |
| 7909 |
{Mips::C_OLE_D32_MM, 78, 1 }, |
7909 |
{Mips::C_OLE_D32_MM, 78, 1 }, |
| 7910 |
{Mips::C_OLE_D64, 79, 1 }, |
7910 |
{Mips::C_OLE_D64, 79, 1 }, |
| 7911 |
{Mips::C_OLE_D64_MM, 80, 1 }, |
7911 |
{Mips::C_OLE_D64_MM, 80, 1 }, |
| 7912 |
{Mips::C_OLE_S, 81, 1 }, |
7912 |
{Mips::C_OLE_S, 81, 1 }, |
| 7913 |
{Mips::C_OLE_S_MM, 82, 1 }, |
7913 |
{Mips::C_OLE_S_MM, 82, 1 }, |
| 7914 |
{Mips::C_OLT_D32, 83, 1 }, |
7914 |
{Mips::C_OLT_D32, 83, 1 }, |
| 7915 |
{Mips::C_OLT_D32_MM, 84, 1 }, |
7915 |
{Mips::C_OLT_D32_MM, 84, 1 }, |
| 7916 |
{Mips::C_OLT_D64, 85, 1 }, |
7916 |
{Mips::C_OLT_D64, 85, 1 }, |
| 7917 |
{Mips::C_OLT_D64_MM, 86, 1 }, |
7917 |
{Mips::C_OLT_D64_MM, 86, 1 }, |
| 7918 |
{Mips::C_OLT_S, 87, 1 }, |
7918 |
{Mips::C_OLT_S, 87, 1 }, |
| 7919 |
{Mips::C_OLT_S_MM, 88, 1 }, |
7919 |
{Mips::C_OLT_S_MM, 88, 1 }, |
| 7920 |
{Mips::C_SEQ_D32, 89, 1 }, |
7920 |
{Mips::C_SEQ_D32, 89, 1 }, |
| 7921 |
{Mips::C_SEQ_D32_MM, 90, 1 }, |
7921 |
{Mips::C_SEQ_D32_MM, 90, 1 }, |
| 7922 |
{Mips::C_SEQ_D64, 91, 1 }, |
7922 |
{Mips::C_SEQ_D64, 91, 1 }, |
| 7923 |
{Mips::C_SEQ_D64_MM, 92, 1 }, |
7923 |
{Mips::C_SEQ_D64_MM, 92, 1 }, |
| 7924 |
{Mips::C_SEQ_S, 93, 1 }, |
7924 |
{Mips::C_SEQ_S, 93, 1 }, |
| 7925 |
{Mips::C_SEQ_S_MM, 94, 1 }, |
7925 |
{Mips::C_SEQ_S_MM, 94, 1 }, |
| 7926 |
{Mips::C_SF_D32, 95, 1 }, |
7926 |
{Mips::C_SF_D32, 95, 1 }, |
| 7927 |
{Mips::C_SF_D32_MM, 96, 1 }, |
7927 |
{Mips::C_SF_D32_MM, 96, 1 }, |
| 7928 |
{Mips::C_SF_D64, 97, 1 }, |
7928 |
{Mips::C_SF_D64, 97, 1 }, |
| 7929 |
{Mips::C_SF_D64_MM, 98, 1 }, |
7929 |
{Mips::C_SF_D64_MM, 98, 1 }, |
| 7930 |
{Mips::C_SF_S, 99, 1 }, |
7930 |
{Mips::C_SF_S, 99, 1 }, |
| 7931 |
{Mips::C_SF_S_MM, 100, 1 }, |
7931 |
{Mips::C_SF_S_MM, 100, 1 }, |
| 7932 |
{Mips::C_UEQ_D32, 101, 1 }, |
7932 |
{Mips::C_UEQ_D32, 101, 1 }, |
| 7933 |
{Mips::C_UEQ_D32_MM, 102, 1 }, |
7933 |
{Mips::C_UEQ_D32_MM, 102, 1 }, |
| 7934 |
{Mips::C_UEQ_D64, 103, 1 }, |
7934 |
{Mips::C_UEQ_D64, 103, 1 }, |
| 7935 |
{Mips::C_UEQ_D64_MM, 104, 1 }, |
7935 |
{Mips::C_UEQ_D64_MM, 104, 1 }, |
| 7936 |
{Mips::C_UEQ_S, 105, 1 }, |
7936 |
{Mips::C_UEQ_S, 105, 1 }, |
| 7937 |
{Mips::C_UEQ_S_MM, 106, 1 }, |
7937 |
{Mips::C_UEQ_S_MM, 106, 1 }, |
| 7938 |
{Mips::C_ULE_D32, 107, 1 }, |
7938 |
{Mips::C_ULE_D32, 107, 1 }, |
| 7939 |
{Mips::C_ULE_D32_MM, 108, 1 }, |
7939 |
{Mips::C_ULE_D32_MM, 108, 1 }, |
| 7940 |
{Mips::C_ULE_D64, 109, 1 }, |
7940 |
{Mips::C_ULE_D64, 109, 1 }, |
| 7941 |
{Mips::C_ULE_D64_MM, 110, 1 }, |
7941 |
{Mips::C_ULE_D64_MM, 110, 1 }, |
| 7942 |
{Mips::C_ULE_S, 111, 1 }, |
7942 |
{Mips::C_ULE_S, 111, 1 }, |
| 7943 |
{Mips::C_ULE_S_MM, 112, 1 }, |
7943 |
{Mips::C_ULE_S_MM, 112, 1 }, |
| 7944 |
{Mips::C_ULT_D32, 113, 1 }, |
7944 |
{Mips::C_ULT_D32, 113, 1 }, |
| 7945 |
{Mips::C_ULT_D32_MM, 114, 1 }, |
7945 |
{Mips::C_ULT_D32_MM, 114, 1 }, |
| 7946 |
{Mips::C_ULT_D64, 115, 1 }, |
7946 |
{Mips::C_ULT_D64, 115, 1 }, |
| 7947 |
{Mips::C_ULT_D64_MM, 116, 1 }, |
7947 |
{Mips::C_ULT_D64_MM, 116, 1 }, |
| 7948 |
{Mips::C_ULT_S, 117, 1 }, |
7948 |
{Mips::C_ULT_S, 117, 1 }, |
| 7949 |
{Mips::C_ULT_S_MM, 118, 1 }, |
7949 |
{Mips::C_ULT_S_MM, 118, 1 }, |
| 7950 |
{Mips::C_UN_D32, 119, 1 }, |
7950 |
{Mips::C_UN_D32, 119, 1 }, |
| 7951 |
{Mips::C_UN_D32_MM, 120, 1 }, |
7951 |
{Mips::C_UN_D32_MM, 120, 1 }, |
| 7952 |
{Mips::C_UN_D64, 121, 1 }, |
7952 |
{Mips::C_UN_D64, 121, 1 }, |
| 7953 |
{Mips::C_UN_D64_MM, 122, 1 }, |
7953 |
{Mips::C_UN_D64_MM, 122, 1 }, |
| 7954 |
{Mips::C_UN_S, 123, 1 }, |
7954 |
{Mips::C_UN_S, 123, 1 }, |
| 7955 |
{Mips::C_UN_S_MM, 124, 1 }, |
7955 |
{Mips::C_UN_S_MM, 124, 1 }, |
| 7956 |
{Mips::DADDu, 125, 1 }, |
7956 |
{Mips::DADDu, 125, 1 }, |
| 7957 |
{Mips::DI, 126, 1 }, |
7957 |
{Mips::DI, 126, 1 }, |
| 7958 |
{Mips::DIV, 127, 1 }, |
7958 |
{Mips::DIV, 127, 1 }, |
| 7959 |
{Mips::DIVU, 128, 1 }, |
7959 |
{Mips::DIVU, 128, 1 }, |
| 7960 |
{Mips::DI_MM, 129, 1 }, |
7960 |
{Mips::DI_MM, 129, 1 }, |
| 7961 |
{Mips::DI_MMR6, 130, 1 }, |
7961 |
{Mips::DI_MMR6, 130, 1 }, |
| 7962 |
{Mips::DMT, 131, 1 }, |
7962 |
{Mips::DMT, 131, 1 }, |
| 7963 |
{Mips::DSUB, 132, 2 }, |
7963 |
{Mips::DSUB, 132, 2 }, |
| 7964 |
{Mips::DSUBu, 134, 2 }, |
7964 |
{Mips::DSUBu, 134, 2 }, |
| 7965 |
{Mips::DVPE, 136, 1 }, |
7965 |
{Mips::DVPE, 136, 1 }, |
| 7966 |
{Mips::EI, 137, 1 }, |
7966 |
{Mips::EI, 137, 1 }, |
| 7967 |
{Mips::EI_MM, 138, 1 }, |
7967 |
{Mips::EI_MM, 138, 1 }, |
| 7968 |
{Mips::EI_MMR6, 139, 1 }, |
7968 |
{Mips::EI_MMR6, 139, 1 }, |
| 7969 |
{Mips::EMT, 140, 1 }, |
7969 |
{Mips::EMT, 140, 1 }, |
| 7970 |
{Mips::EVPE, 141, 1 }, |
7970 |
{Mips::EVPE, 141, 1 }, |
| 7971 |
{Mips::HYPCALL, 142, 1 }, |
7971 |
{Mips::HYPCALL, 142, 1 }, |
| 7972 |
{Mips::HYPCALL_MM, 143, 1 }, |
7972 |
{Mips::HYPCALL_MM, 143, 1 }, |
| 7973 |
{Mips::JALR, 144, 1 }, |
7973 |
{Mips::JALR, 144, 1 }, |
| 7974 |
{Mips::JALR64, 145, 1 }, |
7974 |
{Mips::JALR64, 145, 1 }, |
| 7975 |
{Mips::JALRC_HB_MMR6, 146, 1 }, |
7975 |
{Mips::JALRC_HB_MMR6, 146, 1 }, |
| 7976 |
{Mips::JALRC_MMR6, 147, 1 }, |
7976 |
{Mips::JALRC_MMR6, 147, 1 }, |
| 7977 |
{Mips::JALR_HB, 148, 1 }, |
7977 |
{Mips::JALR_HB, 148, 1 }, |
| 7978 |
{Mips::JALR_HB64, 149, 1 }, |
7978 |
{Mips::JALR_HB64, 149, 1 }, |
| 7979 |
{Mips::JIALC, 150, 1 }, |
7979 |
{Mips::JIALC, 150, 1 }, |
| 7980 |
{Mips::JIALC64, 151, 1 }, |
7980 |
{Mips::JIALC64, 151, 1 }, |
| 7981 |
{Mips::JIC, 152, 1 }, |
7981 |
{Mips::JIC, 152, 1 }, |
| 7982 |
{Mips::JIC64, 153, 1 }, |
7982 |
{Mips::JIC64, 153, 1 }, |
| 7983 |
{Mips::MOVE16_MM, 154, 1 }, |
7983 |
{Mips::MOVE16_MM, 154, 1 }, |
| 7984 |
{Mips::Move32R16, 155, 1 }, |
7984 |
{Mips::Move32R16, 155, 1 }, |
| 7985 |
{Mips::OR, 156, 1 }, |
7985 |
{Mips::OR, 156, 1 }, |
| 7986 |
{Mips::OR64, 157, 1 }, |
7986 |
{Mips::OR64, 157, 1 }, |
| 7987 |
{Mips::RDHWR, 158, 1 }, |
7987 |
{Mips::RDHWR, 158, 1 }, |
| 7988 |
{Mips::RDHWR64, 159, 1 }, |
7988 |
{Mips::RDHWR64, 159, 1 }, |
| 7989 |
{Mips::RDHWR_MM, 160, 1 }, |
7989 |
{Mips::RDHWR_MM, 160, 1 }, |
| 7990 |
{Mips::RDHWR_MMR6, 161, 1 }, |
7990 |
{Mips::RDHWR_MMR6, 161, 1 }, |
| 7991 |
{Mips::SDBBP, 162, 1 }, |
7991 |
{Mips::SDBBP, 162, 1 }, |
| 7992 |
{Mips::SDBBP_MMR6, 163, 1 }, |
7992 |
{Mips::SDBBP_MMR6, 163, 1 }, |
| 7993 |
{Mips::SDBBP_R6, 164, 1 }, |
7993 |
{Mips::SDBBP_R6, 164, 1 }, |
| 7994 |
{Mips::SIGRIE, 165, 1 }, |
7994 |
{Mips::SIGRIE, 165, 1 }, |
| 7995 |
{Mips::SIGRIE_MMR6, 166, 1 }, |
7995 |
{Mips::SIGRIE_MMR6, 166, 1 }, |
| 7996 |
{Mips::SLL, 167, 1 }, |
7996 |
{Mips::SLL, 167, 1 }, |
| 7997 |
{Mips::SLL_MM, 168, 1 }, |
7997 |
{Mips::SLL_MM, 168, 1 }, |
| 7998 |
{Mips::SLL_MMR6, 169, 1 }, |
7998 |
{Mips::SLL_MMR6, 169, 1 }, |
| 7999 |
{Mips::SUB, 170, 2 }, |
7999 |
{Mips::SUB, 170, 2 }, |
| 8000 |
{Mips::SUBU_MMR6, 172, 2 }, |
8000 |
{Mips::SUBU_MMR6, 172, 2 }, |
| 8001 |
{Mips::SUB_MM, 174, 2 }, |
8001 |
{Mips::SUB_MM, 174, 2 }, |
| 8002 |
{Mips::SUB_MMR6, 176, 2 }, |
8002 |
{Mips::SUB_MMR6, 176, 2 }, |
| 8003 |
{Mips::SUBu, 178, 2 }, |
8003 |
{Mips::SUBu, 178, 2 }, |
| 8004 |
{Mips::SUBu_MM, 180, 2 }, |
8004 |
{Mips::SUBu_MM, 180, 2 }, |
| 8005 |
{Mips::SWSP_MM, 182, 1 }, |
8005 |
{Mips::SWSP_MM, 182, 1 }, |
| 8006 |
{Mips::SYNC, 183, 1 }, |
8006 |
{Mips::SYNC, 183, 1 }, |
| 8007 |
{Mips::SYNC_MM, 184, 1 }, |
8007 |
{Mips::SYNC_MM, 184, 1 }, |
| 8008 |
{Mips::SYNC_MMR6, 185, 1 }, |
8008 |
{Mips::SYNC_MMR6, 185, 1 }, |
| 8009 |
{Mips::SYSCALL, 186, 1 }, |
8009 |
{Mips::SYSCALL, 186, 1 }, |
| 8010 |
{Mips::SYSCALL_MM, 187, 1 }, |
8010 |
{Mips::SYSCALL_MM, 187, 1 }, |
| 8011 |
{Mips::TEQ, 188, 1 }, |
8011 |
{Mips::TEQ, 188, 1 }, |
| 8012 |
{Mips::TEQ_MM, 189, 1 }, |
8012 |
{Mips::TEQ_MM, 189, 1 }, |
| 8013 |
{Mips::TGE, 190, 1 }, |
8013 |
{Mips::TGE, 190, 1 }, |
| 8014 |
{Mips::TGEU, 191, 1 }, |
8014 |
{Mips::TGEU, 191, 1 }, |
| 8015 |
{Mips::TGEU_MM, 192, 1 }, |
8015 |
{Mips::TGEU_MM, 192, 1 }, |
| 8016 |
{Mips::TGE_MM, 193, 1 }, |
8016 |
{Mips::TGE_MM, 193, 1 }, |
| 8017 |
{Mips::TLT, 194, 1 }, |
8017 |
{Mips::TLT, 194, 1 }, |
| 8018 |
{Mips::TLTU, 195, 1 }, |
8018 |
{Mips::TLTU, 195, 1 }, |
| 8019 |
{Mips::TLTU_MM, 196, 1 }, |
8019 |
{Mips::TLTU_MM, 196, 1 }, |
| 8020 |
{Mips::TLT_MM, 197, 1 }, |
8020 |
{Mips::TLT_MM, 197, 1 }, |
| 8021 |
{Mips::TNE, 198, 1 }, |
8021 |
{Mips::TNE, 198, 1 }, |
| 8022 |
{Mips::TNE_MM, 199, 1 }, |
8022 |
{Mips::TNE_MM, 199, 1 }, |
| 8023 |
{Mips::WAIT_MM, 200, 1 }, |
8023 |
{Mips::WAIT_MM, 200, 1 }, |
| 8024 |
{Mips::WRDSP, 201, 1 }, |
8024 |
{Mips::WRDSP, 201, 1 }, |
| 8025 |
{Mips::WRDSP_MM, 202, 1 }, |
8025 |
{Mips::WRDSP_MM, 202, 1 }, |
| 8026 |
{Mips::YIELD, 203, 1 }, |
8026 |
{Mips::YIELD, 203, 1 }, |
| 8027 |
}; |
8027 |
}; |
| 8028 |
|
8028 |
|
| 8029 |
static const AliasPattern Patterns[] = { |
8029 |
static const AliasPattern Patterns[] = { |
| 8030 |
// Mips::MFTACX - 0 |
8030 |
// Mips::MFTACX - 0 |
| 8031 |
{0, 0, 2, 4 }, |
8031 |
{0, 0, 2, 4 }, |
| 8032 |
// Mips::MFTC0 - 1 |
8032 |
// Mips::MFTC0 - 1 |
| 8033 |
{10, 4, 3, 5 }, |
8033 |
{10, 4, 3, 5 }, |
| 8034 |
// Mips::MFTHI - 2 |
8034 |
// Mips::MFTHI - 2 |
| 8035 |
{23, 9, 2, 4 }, |
8035 |
{23, 9, 2, 4 }, |
| 8036 |
// Mips::MFTLO - 3 |
8036 |
// Mips::MFTLO - 3 |
| 8037 |
{32, 13, 2, 4 }, |
8037 |
{32, 13, 2, 4 }, |
| 8038 |
// Mips::MTTACX - 4 |
8038 |
// Mips::MTTACX - 4 |
| 8039 |
{41, 17, 2, 4 }, |
8039 |
{41, 17, 2, 4 }, |
| 8040 |
// Mips::MTTC0 - 5 |
8040 |
// Mips::MTTC0 - 5 |
| 8041 |
{51, 21, 3, 5 }, |
8041 |
{51, 21, 3, 5 }, |
| 8042 |
// Mips::MTTHI - 6 |
8042 |
// Mips::MTTHI - 6 |
| 8043 |
{64, 26, 2, 4 }, |
8043 |
{64, 26, 2, 4 }, |
| 8044 |
// Mips::MTTLO - 7 |
8044 |
// Mips::MTTLO - 7 |
| 8045 |
{73, 30, 2, 4 }, |
8045 |
{73, 30, 2, 4 }, |
| 8046 |
// Mips::NORImm - 8 |
8046 |
// Mips::NORImm - 8 |
| 8047 |
{82, 34, 3, 3 }, |
8047 |
{82, 34, 3, 3 }, |
| 8048 |
// Mips::NORImm64 - 9 |
8048 |
// Mips::NORImm64 - 9 |
| 8049 |
{82, 37, 3, 3 }, |
8049 |
{82, 37, 3, 3 }, |
| 8050 |
// Mips::SLTImm64 - 10 |
8050 |
// Mips::SLTImm64 - 10 |
| 8051 |
{93, 40, 3, 3 }, |
8051 |
{93, 40, 3, 3 }, |
| 8052 |
// Mips::SLTUImm64 - 11 |
8052 |
// Mips::SLTUImm64 - 11 |
| 8053 |
{104, 43, 3, 3 }, |
8053 |
{104, 43, 3, 3 }, |
| 8054 |
// Mips::ADDIUPC - 12 |
8054 |
// Mips::ADDIUPC - 12 |
| 8055 |
{116, 46, 2, 3 }, |
8055 |
{116, 46, 2, 3 }, |
| 8056 |
// Mips::ADDIUPC_MMR6 - 13 |
8056 |
// Mips::ADDIUPC_MMR6 - 13 |
| 8057 |
{116, 49, 2, 3 }, |
8057 |
{116, 49, 2, 3 }, |
| 8058 |
// Mips::ADDu - 14 |
8058 |
// Mips::ADDu - 14 |
| 8059 |
{128, 52, 3, 6 }, |
8059 |
{128, 52, 3, 6 }, |
| 8060 |
// Mips::BC1F - 15 |
8060 |
// Mips::BC1F - 15 |
| 8061 |
{140, 58, 2, 6 }, |
8061 |
{140, 58, 2, 6 }, |
| 8062 |
// Mips::BC1FL - 16 |
8062 |
// Mips::BC1FL - 16 |
| 8063 |
{150, 64, 2, 7 }, |
8063 |
{150, 64, 2, 7 }, |
| 8064 |
// Mips::BC1F_MM - 17 |
8064 |
// Mips::BC1F_MM - 17 |
| 8065 |
{140, 71, 2, 4 }, |
8065 |
{140, 71, 2, 4 }, |
| 8066 |
// Mips::BC1T - 18 |
8066 |
// Mips::BC1T - 18 |
| 8067 |
{161, 75, 2, 6 }, |
8067 |
{161, 75, 2, 6 }, |
| 8068 |
// Mips::BC1TL - 19 |
8068 |
// Mips::BC1TL - 19 |
| 8069 |
{171, 81, 2, 7 }, |
8069 |
{171, 81, 2, 7 }, |
| 8070 |
// Mips::BC1T_MM - 20 |
8070 |
// Mips::BC1T_MM - 20 |
| 8071 |
{161, 88, 2, 4 }, |
8071 |
{161, 88, 2, 4 }, |
| 8072 |
// Mips::BEQL - 21 |
8072 |
// Mips::BEQL - 21 |
| 8073 |
{182, 92, 3, 5 }, |
8073 |
{182, 92, 3, 5 }, |
| 8074 |
// Mips::BGEZAL - 22 |
8074 |
// Mips::BGEZAL - 22 |
| 8075 |
{197, 97, 2, 5 }, |
8075 |
{197, 97, 2, 5 }, |
| 8076 |
// Mips::BGEZAL_MM - 23 |
8076 |
// Mips::BGEZAL_MM - 23 |
| 8077 |
{197, 102, 2, 3 }, |
8077 |
{197, 102, 2, 3 }, |
| 8078 |
// Mips::BNEL - 24 |
8078 |
// Mips::BNEL - 24 |
| 8079 |
{206, 105, 3, 5 }, |
8079 |
{206, 105, 3, 5 }, |
| 8080 |
// Mips::BREAK - 25 |
8080 |
// Mips::BREAK - 25 |
| 8081 |
{221, 110, 2, 4 }, |
8081 |
{221, 110, 2, 4 }, |
| 8082 |
{227, 114, 2, 4 }, |
8082 |
{227, 114, 2, 4 }, |
| 8083 |
// Mips::BREAK_MM - 27 |
8083 |
// Mips::BREAK_MM - 27 |
| 8084 |
{221, 118, 2, 3 }, |
8084 |
{221, 118, 2, 3 }, |
| 8085 |
{227, 121, 2, 3 }, |
8085 |
{227, 121, 2, 3 }, |
| 8086 |
// Mips::C_EQ_D32 - 29 |
8086 |
// Mips::C_EQ_D32 - 29 |
| 8087 |
{238, 124, 3, 9 }, |
8087 |
{238, 124, 3, 9 }, |
| 8088 |
// Mips::C_EQ_D32_MM - 30 |
8088 |
// Mips::C_EQ_D32_MM - 30 |
| 8089 |
{238, 133, 3, 7 }, |
8089 |
{238, 133, 3, 7 }, |
| 8090 |
// Mips::C_EQ_D64 - 31 |
8090 |
// Mips::C_EQ_D64 - 31 |
| 8091 |
{238, 140, 3, 9 }, |
8091 |
{238, 140, 3, 9 }, |
| 8092 |
// Mips::C_EQ_D64_MM - 32 |
8092 |
// Mips::C_EQ_D64_MM - 32 |
| 8093 |
{238, 149, 3, 7 }, |
8093 |
{238, 149, 3, 7 }, |
| 8094 |
// Mips::C_EQ_S - 33 |
8094 |
// Mips::C_EQ_S - 33 |
| 8095 |
{252, 156, 3, 8 }, |
8095 |
{252, 156, 3, 8 }, |
| 8096 |
// Mips::C_EQ_S_MM - 34 |
8096 |
// Mips::C_EQ_S_MM - 34 |
| 8097 |
{252, 164, 3, 6 }, |
8097 |
{252, 164, 3, 6 }, |
| 8098 |
// Mips::C_F_D32 - 35 |
8098 |
// Mips::C_F_D32 - 35 |
| 8099 |
{266, 170, 3, 9 }, |
8099 |
{266, 170, 3, 9 }, |
| 8100 |
// Mips::C_F_D32_MM - 36 |
8100 |
// Mips::C_F_D32_MM - 36 |
| 8101 |
{266, 179, 3, 7 }, |
8101 |
{266, 179, 3, 7 }, |
| 8102 |
// Mips::C_F_D64 - 37 |
8102 |
// Mips::C_F_D64 - 37 |
| 8103 |
{266, 186, 3, 9 }, |
8103 |
{266, 186, 3, 9 }, |
| 8104 |
// Mips::C_F_D64_MM - 38 |
8104 |
// Mips::C_F_D64_MM - 38 |
| 8105 |
{266, 195, 3, 7 }, |
8105 |
{266, 195, 3, 7 }, |
| 8106 |
// Mips::C_F_S - 39 |
8106 |
// Mips::C_F_S - 39 |
| 8107 |
{279, 202, 3, 8 }, |
8107 |
{279, 202, 3, 8 }, |
| 8108 |
// Mips::C_F_S_MM - 40 |
8108 |
// Mips::C_F_S_MM - 40 |
| 8109 |
{279, 210, 3, 6 }, |
8109 |
{279, 210, 3, 6 }, |
| 8110 |
// Mips::C_LE_D32 - 41 |
8110 |
// Mips::C_LE_D32 - 41 |
| 8111 |
{292, 216, 3, 9 }, |
8111 |
{292, 216, 3, 9 }, |
| 8112 |
// Mips::C_LE_D32_MM - 42 |
8112 |
// Mips::C_LE_D32_MM - 42 |
| 8113 |
{292, 225, 3, 7 }, |
8113 |
{292, 225, 3, 7 }, |
| 8114 |
// Mips::C_LE_D64 - 43 |
8114 |
// Mips::C_LE_D64 - 43 |
| 8115 |
{292, 232, 3, 9 }, |
8115 |
{292, 232, 3, 9 }, |
| 8116 |
// Mips::C_LE_D64_MM - 44 |
8116 |
// Mips::C_LE_D64_MM - 44 |
| 8117 |
{292, 241, 3, 7 }, |
8117 |
{292, 241, 3, 7 }, |
| 8118 |
// Mips::C_LE_S - 45 |
8118 |
// Mips::C_LE_S - 45 |
| 8119 |
{306, 248, 3, 8 }, |
8119 |
{306, 248, 3, 8 }, |
| 8120 |
// Mips::C_LE_S_MM - 46 |
8120 |
// Mips::C_LE_S_MM - 46 |
| 8121 |
{306, 256, 3, 6 }, |
8121 |
{306, 256, 3, 6 }, |
| 8122 |
// Mips::C_LT_D32 - 47 |
8122 |
// Mips::C_LT_D32 - 47 |
| 8123 |
{320, 262, 3, 9 }, |
8123 |
{320, 262, 3, 9 }, |
| 8124 |
// Mips::C_LT_D32_MM - 48 |
8124 |
// Mips::C_LT_D32_MM - 48 |
| 8125 |
{320, 271, 3, 7 }, |
8125 |
{320, 271, 3, 7 }, |
| 8126 |
// Mips::C_LT_D64 - 49 |
8126 |
// Mips::C_LT_D64 - 49 |
| 8127 |
{320, 278, 3, 9 }, |
8127 |
{320, 278, 3, 9 }, |
| 8128 |
// Mips::C_LT_D64_MM - 50 |
8128 |
// Mips::C_LT_D64_MM - 50 |
| 8129 |
{320, 287, 3, 7 }, |
8129 |
{320, 287, 3, 7 }, |
| 8130 |
// Mips::C_LT_S - 51 |
8130 |
// Mips::C_LT_S - 51 |
| 8131 |
{334, 294, 3, 8 }, |
8131 |
{334, 294, 3, 8 }, |
| 8132 |
// Mips::C_LT_S_MM - 52 |
8132 |
// Mips::C_LT_S_MM - 52 |
| 8133 |
{334, 302, 3, 6 }, |
8133 |
{334, 302, 3, 6 }, |
| 8134 |
// Mips::C_NGE_D32 - 53 |
8134 |
// Mips::C_NGE_D32 - 53 |
| 8135 |
{348, 308, 3, 9 }, |
8135 |
{348, 308, 3, 9 }, |
| 8136 |
// Mips::C_NGE_D32_MM - 54 |
8136 |
// Mips::C_NGE_D32_MM - 54 |
| 8137 |
{348, 317, 3, 7 }, |
8137 |
{348, 317, 3, 7 }, |
| 8138 |
// Mips::C_NGE_D64 - 55 |
8138 |
// Mips::C_NGE_D64 - 55 |
| 8139 |
{348, 324, 3, 9 }, |
8139 |
{348, 324, 3, 9 }, |
| 8140 |
// Mips::C_NGE_D64_MM - 56 |
8140 |
// Mips::C_NGE_D64_MM - 56 |
| 8141 |
{348, 333, 3, 7 }, |
8141 |
{348, 333, 3, 7 }, |
| 8142 |
// Mips::C_NGE_S - 57 |
8142 |
// Mips::C_NGE_S - 57 |
| 8143 |
{363, 340, 3, 8 }, |
8143 |
{363, 340, 3, 8 }, |
| 8144 |
// Mips::C_NGE_S_MM - 58 |
8144 |
// Mips::C_NGE_S_MM - 58 |
| 8145 |
{363, 348, 3, 6 }, |
8145 |
{363, 348, 3, 6 }, |
| 8146 |
// Mips::C_NGLE_D32 - 59 |
8146 |
// Mips::C_NGLE_D32 - 59 |
| 8147 |
{378, 354, 3, 9 }, |
8147 |
{378, 354, 3, 9 }, |
| 8148 |
// Mips::C_NGLE_D32_MM - 60 |
8148 |
// Mips::C_NGLE_D32_MM - 60 |
| 8149 |
{378, 363, 3, 7 }, |
8149 |
{378, 363, 3, 7 }, |
| 8150 |
// Mips::C_NGLE_D64 - 61 |
8150 |
// Mips::C_NGLE_D64 - 61 |
| 8151 |
{378, 370, 3, 9 }, |
8151 |
{378, 370, 3, 9 }, |
| 8152 |
// Mips::C_NGLE_D64_MM - 62 |
8152 |
// Mips::C_NGLE_D64_MM - 62 |
| 8153 |
{378, 379, 3, 7 }, |
8153 |
{378, 379, 3, 7 }, |
| 8154 |
// Mips::C_NGLE_S - 63 |
8154 |
// Mips::C_NGLE_S - 63 |
| 8155 |
{394, 386, 3, 8 }, |
8155 |
{394, 386, 3, 8 }, |
| 8156 |
// Mips::C_NGLE_S_MM - 64 |
8156 |
// Mips::C_NGLE_S_MM - 64 |
| 8157 |
{394, 394, 3, 6 }, |
8157 |
{394, 394, 3, 6 }, |
| 8158 |
// Mips::C_NGL_D32 - 65 |
8158 |
// Mips::C_NGL_D32 - 65 |
| 8159 |
{410, 400, 3, 9 }, |
8159 |
{410, 400, 3, 9 }, |
| 8160 |
// Mips::C_NGL_D32_MM - 66 |
8160 |
// Mips::C_NGL_D32_MM - 66 |
| 8161 |
{410, 409, 3, 7 }, |
8161 |
{410, 409, 3, 7 }, |
| 8162 |
// Mips::C_NGL_D64 - 67 |
8162 |
// Mips::C_NGL_D64 - 67 |
| 8163 |
{410, 416, 3, 9 }, |
8163 |
{410, 416, 3, 9 }, |
| 8164 |
// Mips::C_NGL_D64_MM - 68 |
8164 |
// Mips::C_NGL_D64_MM - 68 |
| 8165 |
{410, 425, 3, 7 }, |
8165 |
{410, 425, 3, 7 }, |
| 8166 |
// Mips::C_NGL_S - 69 |
8166 |
// Mips::C_NGL_S - 69 |
| 8167 |
{425, 432, 3, 8 }, |
8167 |
{425, 432, 3, 8 }, |
| 8168 |
// Mips::C_NGL_S_MM - 70 |
8168 |
// Mips::C_NGL_S_MM - 70 |
| 8169 |
{425, 440, 3, 6 }, |
8169 |
{425, 440, 3, 6 }, |
| 8170 |
// Mips::C_NGT_D32 - 71 |
8170 |
// Mips::C_NGT_D32 - 71 |
| 8171 |
{440, 446, 3, 9 }, |
8171 |
{440, 446, 3, 9 }, |
| 8172 |
// Mips::C_NGT_D32_MM - 72 |
8172 |
// Mips::C_NGT_D32_MM - 72 |
| 8173 |
{440, 455, 3, 7 }, |
8173 |
{440, 455, 3, 7 }, |
| 8174 |
// Mips::C_NGT_D64 - 73 |
8174 |
// Mips::C_NGT_D64 - 73 |
| 8175 |
{440, 462, 3, 9 }, |
8175 |
{440, 462, 3, 9 }, |
| 8176 |
// Mips::C_NGT_D64_MM - 74 |
8176 |
// Mips::C_NGT_D64_MM - 74 |
| 8177 |
{440, 471, 3, 7 }, |
8177 |
{440, 471, 3, 7 }, |
| 8178 |
// Mips::C_NGT_S - 75 |
8178 |
// Mips::C_NGT_S - 75 |
| 8179 |
{455, 478, 3, 8 }, |
8179 |
{455, 478, 3, 8 }, |
| 8180 |
// Mips::C_NGT_S_MM - 76 |
8180 |
// Mips::C_NGT_S_MM - 76 |
| 8181 |
{455, 486, 3, 6 }, |
8181 |
{455, 486, 3, 6 }, |
| 8182 |
// Mips::C_OLE_D32 - 77 |
8182 |
// Mips::C_OLE_D32 - 77 |
| 8183 |
{470, 492, 3, 9 }, |
8183 |
{470, 492, 3, 9 }, |
| 8184 |
// Mips::C_OLE_D32_MM - 78 |
8184 |
// Mips::C_OLE_D32_MM - 78 |
| 8185 |
{470, 501, 3, 7 }, |
8185 |
{470, 501, 3, 7 }, |
| 8186 |
// Mips::C_OLE_D64 - 79 |
8186 |
// Mips::C_OLE_D64 - 79 |
| 8187 |
{470, 508, 3, 9 }, |
8187 |
{470, 508, 3, 9 }, |
| 8188 |
// Mips::C_OLE_D64_MM - 80 |
8188 |
// Mips::C_OLE_D64_MM - 80 |
| 8189 |
{470, 517, 3, 7 }, |
8189 |
{470, 517, 3, 7 }, |
| 8190 |
// Mips::C_OLE_S - 81 |
8190 |
// Mips::C_OLE_S - 81 |
| 8191 |
{485, 524, 3, 8 }, |
8191 |
{485, 524, 3, 8 }, |
| 8192 |
// Mips::C_OLE_S_MM - 82 |
8192 |
// Mips::C_OLE_S_MM - 82 |
| 8193 |
{485, 532, 3, 6 }, |
8193 |
{485, 532, 3, 6 }, |
| 8194 |
// Mips::C_OLT_D32 - 83 |
8194 |
// Mips::C_OLT_D32 - 83 |
| 8195 |
{500, 538, 3, 9 }, |
8195 |
{500, 538, 3, 9 }, |
| 8196 |
// Mips::C_OLT_D32_MM - 84 |
8196 |
// Mips::C_OLT_D32_MM - 84 |
| 8197 |
{500, 547, 3, 7 }, |
8197 |
{500, 547, 3, 7 }, |
| 8198 |
// Mips::C_OLT_D64 - 85 |
8198 |
// Mips::C_OLT_D64 - 85 |
| 8199 |
{500, 554, 3, 9 }, |
8199 |
{500, 554, 3, 9 }, |
| 8200 |
// Mips::C_OLT_D64_MM - 86 |
8200 |
// Mips::C_OLT_D64_MM - 86 |
| 8201 |
{500, 563, 3, 7 }, |
8201 |
{500, 563, 3, 7 }, |
| 8202 |
// Mips::C_OLT_S - 87 |
8202 |
// Mips::C_OLT_S - 87 |
| 8203 |
{515, 570, 3, 8 }, |
8203 |
{515, 570, 3, 8 }, |
| 8204 |
// Mips::C_OLT_S_MM - 88 |
8204 |
// Mips::C_OLT_S_MM - 88 |
| 8205 |
{515, 578, 3, 6 }, |
8205 |
{515, 578, 3, 6 }, |
| 8206 |
// Mips::C_SEQ_D32 - 89 |
8206 |
// Mips::C_SEQ_D32 - 89 |
| 8207 |
{530, 584, 3, 9 }, |
8207 |
{530, 584, 3, 9 }, |
| 8208 |
// Mips::C_SEQ_D32_MM - 90 |
8208 |
// Mips::C_SEQ_D32_MM - 90 |
| 8209 |
{530, 593, 3, 7 }, |
8209 |
{530, 593, 3, 7 }, |
| 8210 |
// Mips::C_SEQ_D64 - 91 |
8210 |
// Mips::C_SEQ_D64 - 91 |
| 8211 |
{530, 600, 3, 9 }, |
8211 |
{530, 600, 3, 9 }, |
| 8212 |
// Mips::C_SEQ_D64_MM - 92 |
8212 |
// Mips::C_SEQ_D64_MM - 92 |
| 8213 |
{530, 609, 3, 7 }, |
8213 |
{530, 609, 3, 7 }, |
| 8214 |
// Mips::C_SEQ_S - 93 |
8214 |
// Mips::C_SEQ_S - 93 |
| 8215 |
{545, 616, 3, 8 }, |
8215 |
{545, 616, 3, 8 }, |
| 8216 |
// Mips::C_SEQ_S_MM - 94 |
8216 |
// Mips::C_SEQ_S_MM - 94 |
| 8217 |
{545, 624, 3, 6 }, |
8217 |
{545, 624, 3, 6 }, |
| 8218 |
// Mips::C_SF_D32 - 95 |
8218 |
// Mips::C_SF_D32 - 95 |
| 8219 |
{560, 630, 3, 9 }, |
8219 |
{560, 630, 3, 9 }, |
| 8220 |
// Mips::C_SF_D32_MM - 96 |
8220 |
// Mips::C_SF_D32_MM - 96 |
| 8221 |
{560, 639, 3, 7 }, |
8221 |
{560, 639, 3, 7 }, |
| 8222 |
// Mips::C_SF_D64 - 97 |
8222 |
// Mips::C_SF_D64 - 97 |
| 8223 |
{560, 646, 3, 9 }, |
8223 |
{560, 646, 3, 9 }, |
| 8224 |
// Mips::C_SF_D64_MM - 98 |
8224 |
// Mips::C_SF_D64_MM - 98 |
| 8225 |
{560, 655, 3, 7 }, |
8225 |
{560, 655, 3, 7 }, |
| 8226 |
// Mips::C_SF_S - 99 |
8226 |
// Mips::C_SF_S - 99 |
| 8227 |
{574, 662, 3, 8 }, |
8227 |
{574, 662, 3, 8 }, |
| 8228 |
// Mips::C_SF_S_MM - 100 |
8228 |
// Mips::C_SF_S_MM - 100 |
| 8229 |
{574, 670, 3, 6 }, |
8229 |
{574, 670, 3, 6 }, |
| 8230 |
// Mips::C_UEQ_D32 - 101 |
8230 |
// Mips::C_UEQ_D32 - 101 |
| 8231 |
{588, 676, 3, 9 }, |
8231 |
{588, 676, 3, 9 }, |
| 8232 |
// Mips::C_UEQ_D32_MM - 102 |
8232 |
// Mips::C_UEQ_D32_MM - 102 |
| 8233 |
{588, 685, 3, 7 }, |
8233 |
{588, 685, 3, 7 }, |
| 8234 |
// Mips::C_UEQ_D64 - 103 |
8234 |
// Mips::C_UEQ_D64 - 103 |
| 8235 |
{588, 692, 3, 9 }, |
8235 |
{588, 692, 3, 9 }, |
| 8236 |
// Mips::C_UEQ_D64_MM - 104 |
8236 |
// Mips::C_UEQ_D64_MM - 104 |
| 8237 |
{588, 701, 3, 7 }, |
8237 |
{588, 701, 3, 7 }, |
| 8238 |
// Mips::C_UEQ_S - 105 |
8238 |
// Mips::C_UEQ_S - 105 |
| 8239 |
{603, 708, 3, 8 }, |
8239 |
{603, 708, 3, 8 }, |
| 8240 |
// Mips::C_UEQ_S_MM - 106 |
8240 |
// Mips::C_UEQ_S_MM - 106 |
| 8241 |
{603, 716, 3, 6 }, |
8241 |
{603, 716, 3, 6 }, |
| 8242 |
// Mips::C_ULE_D32 - 107 |
8242 |
// Mips::C_ULE_D32 - 107 |
| 8243 |
{618, 722, 3, 9 }, |
8243 |
{618, 722, 3, 9 }, |
| 8244 |
// Mips::C_ULE_D32_MM - 108 |
8244 |
// Mips::C_ULE_D32_MM - 108 |
| 8245 |
{618, 731, 3, 7 }, |
8245 |
{618, 731, 3, 7 }, |
| 8246 |
// Mips::C_ULE_D64 - 109 |
8246 |
// Mips::C_ULE_D64 - 109 |
| 8247 |
{618, 738, 3, 9 }, |
8247 |
{618, 738, 3, 9 }, |
| 8248 |
// Mips::C_ULE_D64_MM - 110 |
8248 |
// Mips::C_ULE_D64_MM - 110 |
| 8249 |
{618, 747, 3, 7 }, |
8249 |
{618, 747, 3, 7 }, |
| 8250 |
// Mips::C_ULE_S - 111 |
8250 |
// Mips::C_ULE_S - 111 |
| 8251 |
{633, 754, 3, 8 }, |
8251 |
{633, 754, 3, 8 }, |
| 8252 |
// Mips::C_ULE_S_MM - 112 |
8252 |
// Mips::C_ULE_S_MM - 112 |
| 8253 |
{633, 762, 3, 6 }, |
8253 |
{633, 762, 3, 6 }, |
| 8254 |
// Mips::C_ULT_D32 - 113 |
8254 |
// Mips::C_ULT_D32 - 113 |
| 8255 |
{648, 768, 3, 9 }, |
8255 |
{648, 768, 3, 9 }, |
| 8256 |
// Mips::C_ULT_D32_MM - 114 |
8256 |
// Mips::C_ULT_D32_MM - 114 |
| 8257 |
{648, 777, 3, 7 }, |
8257 |
{648, 777, 3, 7 }, |
| 8258 |
// Mips::C_ULT_D64 - 115 |
8258 |
// Mips::C_ULT_D64 - 115 |
| 8259 |
{648, 784, 3, 9 }, |
8259 |
{648, 784, 3, 9 }, |
| 8260 |
// Mips::C_ULT_D64_MM - 116 |
8260 |
// Mips::C_ULT_D64_MM - 116 |
| 8261 |
{648, 793, 3, 7 }, |
8261 |
{648, 793, 3, 7 }, |
| 8262 |
// Mips::C_ULT_S - 117 |
8262 |
// Mips::C_ULT_S - 117 |
| 8263 |
{663, 800, 3, 8 }, |
8263 |
{663, 800, 3, 8 }, |
| 8264 |
// Mips::C_ULT_S_MM - 118 |
8264 |
// Mips::C_ULT_S_MM - 118 |
| 8265 |
{663, 808, 3, 6 }, |
8265 |
{663, 808, 3, 6 }, |
| 8266 |
// Mips::C_UN_D32 - 119 |
8266 |
// Mips::C_UN_D32 - 119 |
| 8267 |
{678, 814, 3, 9 }, |
8267 |
{678, 814, 3, 9 }, |
| 8268 |
// Mips::C_UN_D32_MM - 120 |
8268 |
// Mips::C_UN_D32_MM - 120 |
| 8269 |
{678, 823, 3, 7 }, |
8269 |
{678, 823, 3, 7 }, |
| 8270 |
// Mips::C_UN_D64 - 121 |
8270 |
// Mips::C_UN_D64 - 121 |
| 8271 |
{678, 830, 3, 9 }, |
8271 |
{678, 830, 3, 9 }, |
| 8272 |
// Mips::C_UN_D64_MM - 122 |
8272 |
// Mips::C_UN_D64_MM - 122 |
| 8273 |
{678, 839, 3, 7 }, |
8273 |
{678, 839, 3, 7 }, |
| 8274 |
// Mips::C_UN_S - 123 |
8274 |
// Mips::C_UN_S - 123 |
| 8275 |
{692, 846, 3, 8 }, |
8275 |
{692, 846, 3, 8 }, |
| 8276 |
// Mips::C_UN_S_MM - 124 |
8276 |
// Mips::C_UN_S_MM - 124 |
| 8277 |
{692, 854, 3, 6 }, |
8277 |
{692, 854, 3, 6 }, |
| 8278 |
// Mips::DADDu - 125 |
8278 |
// Mips::DADDu - 125 |
| 8279 |
{128, 860, 3, 5 }, |
8279 |
{128, 860, 3, 5 }, |
| 8280 |
// Mips::DI - 126 |
8280 |
// Mips::DI - 126 |
| 8281 |
{706, 865, 1, 4 }, |
8281 |
{706, 865, 1, 4 }, |
| 8282 |
// Mips::DIV - 127 |
8282 |
// Mips::DIV - 127 |
| 8283 |
{709, 869, 3, 5 }, |
8283 |
{709, 869, 3, 5 }, |
| 8284 |
// Mips::DIVU - 128 |
8284 |
// Mips::DIVU - 128 |
| 8285 |
{720, 874, 3, 5 }, |
8285 |
{720, 874, 3, 5 }, |
| 8286 |
// Mips::DI_MM - 129 |
8286 |
// Mips::DI_MM - 129 |
| 8287 |
{706, 879, 1, 2 }, |
8287 |
{706, 879, 1, 2 }, |
| 8288 |
// Mips::DI_MMR6 - 130 |
8288 |
// Mips::DI_MMR6 - 130 |
| 8289 |
{706, 881, 1, 3 }, |
8289 |
{706, 881, 1, 3 }, |
| 8290 |
// Mips::DMT - 131 |
8290 |
// Mips::DMT - 131 |
| 8291 |
{732, 884, 1, 3 }, |
8291 |
{732, 884, 1, 3 }, |
| 8292 |
// Mips::DSUB - 132 |
8292 |
// Mips::DSUB - 132 |
| 8293 |
{736, 887, 3, 6 }, |
8293 |
{736, 887, 3, 6 }, |
| 8294 |
{748, 893, 3, 6 }, |
8294 |
{748, 893, 3, 6 }, |
| 8295 |
// Mips::DSUBu - 134 |
8295 |
// Mips::DSUBu - 134 |
| 8296 |
{756, 899, 3, 6 }, |
8296 |
{756, 899, 3, 6 }, |
| 8297 |
{769, 905, 3, 6 }, |
8297 |
{769, 905, 3, 6 }, |
| 8298 |
// Mips::DVPE - 136 |
8298 |
// Mips::DVPE - 136 |
| 8299 |
{778, 911, 1, 3 }, |
8299 |
{778, 911, 1, 3 }, |
| 8300 |
// Mips::EI - 137 |
8300 |
// Mips::EI - 137 |
| 8301 |
{783, 914, 1, 4 }, |
8301 |
{783, 914, 1, 4 }, |
| 8302 |
// Mips::EI_MM - 138 |
8302 |
// Mips::EI_MM - 138 |
| 8303 |
{783, 918, 1, 2 }, |
8303 |
{783, 918, 1, 2 }, |
| 8304 |
// Mips::EI_MMR6 - 139 |
8304 |
// Mips::EI_MMR6 - 139 |
| 8305 |
{783, 920, 1, 3 }, |
8305 |
{783, 920, 1, 3 }, |
| 8306 |
// Mips::EMT - 140 |
8306 |
// Mips::EMT - 140 |
| 8307 |
{786, 923, 1, 3 }, |
8307 |
{786, 923, 1, 3 }, |
| 8308 |
// Mips::EVPE - 141 |
8308 |
// Mips::EVPE - 141 |
| 8309 |
{790, 926, 1, 3 }, |
8309 |
{790, 926, 1, 3 }, |
| 8310 |
// Mips::HYPCALL - 142 |
8310 |
// Mips::HYPCALL - 142 |
| 8311 |
{795, 929, 1, 5 }, |
8311 |
{795, 929, 1, 5 }, |
| 8312 |
// Mips::HYPCALL_MM - 143 |
8312 |
// Mips::HYPCALL_MM - 143 |
| 8313 |
{795, 934, 1, 4 }, |
8313 |
{795, 934, 1, 4 }, |
| 8314 |
// Mips::JALR - 144 |
8314 |
// Mips::JALR - 144 |
| 8315 |
{803, 938, 2, 6 }, |
8315 |
{803, 938, 2, 6 }, |
| 8316 |
// Mips::JALR64 - 145 |
8316 |
// Mips::JALR64 - 145 |
| 8317 |
{803, 944, 2, 4 }, |
8317 |
{803, 944, 2, 4 }, |
| 8318 |
// Mips::JALRC_HB_MMR6 - 146 |
8318 |
// Mips::JALRC_HB_MMR6 - 146 |
| 8319 |
{809, 948, 2, 4 }, |
8319 |
{809, 948, 2, 4 }, |
| 8320 |
// Mips::JALRC_MMR6 - 147 |
8320 |
// Mips::JALRC_MMR6 - 147 |
| 8321 |
{821, 952, 2, 4 }, |
8321 |
{821, 952, 2, 4 }, |
| 8322 |
// Mips::JALR_HB - 148 |
8322 |
// Mips::JALR_HB - 148 |
| 8323 |
{830, 956, 2, 5 }, |
8323 |
{830, 956, 2, 5 }, |
| 8324 |
// Mips::JALR_HB64 - 149 |
8324 |
// Mips::JALR_HB64 - 149 |
| 8325 |
{830, 961, 2, 5 }, |
8325 |
{830, 961, 2, 5 }, |
| 8326 |
// Mips::JIALC - 150 |
8326 |
// Mips::JIALC - 150 |
| 8327 |
{841, 966, 2, 6 }, |
8327 |
{841, 966, 2, 6 }, |
| 8328 |
// Mips::JIALC64 - 151 |
8328 |
// Mips::JIALC64 - 151 |
| 8329 |
{841, 972, 2, 4 }, |
8329 |
{841, 972, 2, 4 }, |
| 8330 |
// Mips::JIC - 152 |
8330 |
// Mips::JIC - 152 |
| 8331 |
{850, 976, 2, 5 }, |
8331 |
{850, 976, 2, 5 }, |
| 8332 |
// Mips::JIC64 - 153 |
8332 |
// Mips::JIC64 - 153 |
| 8333 |
{850, 981, 2, 4 }, |
8333 |
{850, 981, 2, 4 }, |
| 8334 |
// Mips::MOVE16_MM - 154 |
8334 |
// Mips::MOVE16_MM - 154 |
| 8335 |
{857, 985, 2, 3 }, |
8335 |
{857, 985, 2, 3 }, |
| 8336 |
// Mips::Move32R16 - 155 |
8336 |
// Mips::Move32R16 - 155 |
| 8337 |
{857, 988, 2, 3 }, |
8337 |
{857, 988, 2, 3 }, |
| 8338 |
// Mips::OR - 156 |
8338 |
// Mips::OR - 156 |
| 8339 |
{128, 991, 3, 6 }, |
8339 |
{128, 991, 3, 6 }, |
| 8340 |
// Mips::OR64 - 157 |
8340 |
// Mips::OR64 - 157 |
| 8341 |
{128, 997, 3, 5 }, |
8341 |
{128, 997, 3, 5 }, |
| 8342 |
// Mips::RDHWR - 158 |
8342 |
// Mips::RDHWR - 158 |
| 8343 |
{861, 1002, 3, 5 }, |
8343 |
{861, 1002, 3, 5 }, |
| 8344 |
// Mips::RDHWR64 - 159 |
8344 |
// Mips::RDHWR64 - 159 |
| 8345 |
{861, 1007, 3, 4 }, |
8345 |
{861, 1007, 3, 4 }, |
| 8346 |
// Mips::RDHWR_MM - 160 |
8346 |
// Mips::RDHWR_MM - 160 |
| 8347 |
{861, 1011, 3, 5 }, |
8347 |
{861, 1011, 3, 5 }, |
| 8348 |
// Mips::RDHWR_MMR6 - 161 |
8348 |
// Mips::RDHWR_MMR6 - 161 |
| 8349 |
{861, 1016, 3, 5 }, |
8349 |
{861, 1016, 3, 5 }, |
| 8350 |
// Mips::SDBBP - 162 |
8350 |
// Mips::SDBBP - 162 |
| 8351 |
{874, 1021, 1, 5 }, |
8351 |
{874, 1021, 1, 5 }, |
| 8352 |
// Mips::SDBBP_MMR6 - 163 |
8352 |
// Mips::SDBBP_MMR6 - 163 |
| 8353 |
{874, 1026, 1, 3 }, |
8353 |
{874, 1026, 1, 3 }, |
| 8354 |
// Mips::SDBBP_R6 - 164 |
8354 |
// Mips::SDBBP_R6 - 164 |
| 8355 |
{874, 1029, 1, 4 }, |
8355 |
{874, 1029, 1, 4 }, |
| 8356 |
// Mips::SIGRIE - 165 |
8356 |
// Mips::SIGRIE - 165 |
| 8357 |
{880, 1033, 1, 4 }, |
8357 |
{880, 1033, 1, 4 }, |
| 8358 |
// Mips::SIGRIE_MMR6 - 166 |
8358 |
// Mips::SIGRIE_MMR6 - 166 |
| 8359 |
{880, 1037, 1, 3 }, |
8359 |
{880, 1037, 1, 3 }, |
| 8360 |
// Mips::SLL - 167 |
8360 |
// Mips::SLL - 167 |
| 8361 |
{857, 1040, 3, 5 }, |
8361 |
{857, 1040, 3, 5 }, |
| 8362 |
// Mips::SLL_MM - 168 |
8362 |
// Mips::SLL_MM - 168 |
| 8363 |
{857, 1045, 3, 4 }, |
8363 |
{857, 1045, 3, 4 }, |
| 8364 |
// Mips::SLL_MMR6 - 169 |
8364 |
// Mips::SLL_MMR6 - 169 |
| 8365 |
{857, 1049, 3, 5 }, |
8365 |
{857, 1049, 3, 5 }, |
| 8366 |
// Mips::SUB - 170 |
8366 |
// Mips::SUB - 170 |
| 8367 |
{887, 1054, 3, 5 }, |
8367 |
{887, 1054, 3, 5 }, |
| 8368 |
{898, 1059, 3, 5 }, |
8368 |
{898, 1059, 3, 5 }, |
| 8369 |
// Mips::SUBU_MMR6 - 172 |
8369 |
// Mips::SUBU_MMR6 - 172 |
| 8370 |
{905, 1064, 3, 5 }, |
8370 |
{905, 1064, 3, 5 }, |
| 8371 |
{917, 1069, 3, 5 }, |
8371 |
{917, 1069, 3, 5 }, |
| 8372 |
// Mips::SUB_MM - 174 |
8372 |
// Mips::SUB_MM - 174 |
| 8373 |
{887, 1074, 3, 5 }, |
8373 |
{887, 1074, 3, 5 }, |
| 8374 |
{898, 1079, 3, 5 }, |
8374 |
{898, 1079, 3, 5 }, |
| 8375 |
// Mips::SUB_MMR6 - 176 |
8375 |
// Mips::SUB_MMR6 - 176 |
| 8376 |
{887, 1084, 3, 5 }, |
8376 |
{887, 1084, 3, 5 }, |
| 8377 |
{898, 1089, 3, 5 }, |
8377 |
{898, 1089, 3, 5 }, |
| 8378 |
// Mips::SUBu - 178 |
8378 |
// Mips::SUBu - 178 |
| 8379 |
{905, 1094, 3, 5 }, |
8379 |
{905, 1094, 3, 5 }, |
| 8380 |
{917, 1099, 3, 5 }, |
8380 |
{917, 1099, 3, 5 }, |
| 8381 |
// Mips::SUBu_MM - 180 |
8381 |
// Mips::SUBu_MM - 180 |
| 8382 |
{905, 1104, 3, 5 }, |
8382 |
{905, 1104, 3, 5 }, |
| 8383 |
{917, 1109, 3, 5 }, |
8383 |
{917, 1109, 3, 5 }, |
| 8384 |
// Mips::SWSP_MM - 182 |
8384 |
// Mips::SWSP_MM - 182 |
| 8385 |
{925, 1114, 3, 2 }, |
8385 |
{925, 1114, 3, 2 }, |
| 8386 |
// Mips::SYNC - 183 |
8386 |
// Mips::SYNC - 183 |
| 8387 |
{937, 1116, 1, 4 }, |
8387 |
{937, 1116, 1, 4 }, |
| 8388 |
// Mips::SYNC_MM - 184 |
8388 |
// Mips::SYNC_MM - 184 |
| 8389 |
{937, 1120, 1, 2 }, |
8389 |
{937, 1120, 1, 2 }, |
| 8390 |
// Mips::SYNC_MMR6 - 185 |
8390 |
// Mips::SYNC_MMR6 - 185 |
| 8391 |
{937, 1122, 1, 3 }, |
8391 |
{937, 1122, 1, 3 }, |
| 8392 |
// Mips::SYSCALL - 186 |
8392 |
// Mips::SYSCALL - 186 |
| 8393 |
{942, 1125, 1, 3 }, |
8393 |
{942, 1125, 1, 3 }, |
| 8394 |
// Mips::SYSCALL_MM - 187 |
8394 |
// Mips::SYSCALL_MM - 187 |
| 8395 |
{942, 1128, 1, 2 }, |
8395 |
{942, 1128, 1, 2 }, |
| 8396 |
// Mips::TEQ - 188 |
8396 |
// Mips::TEQ - 188 |
| 8397 |
{950, 1130, 3, 6 }, |
8397 |
{950, 1130, 3, 6 }, |
| 8398 |
// Mips::TEQ_MM - 189 |
8398 |
// Mips::TEQ_MM - 189 |
| 8399 |
{950, 1136, 3, 4 }, |
8399 |
{950, 1136, 3, 4 }, |
| 8400 |
// Mips::TGE - 190 |
8400 |
// Mips::TGE - 190 |
| 8401 |
{961, 1140, 3, 6 }, |
8401 |
{961, 1140, 3, 6 }, |
| 8402 |
// Mips::TGEU - 191 |
8402 |
// Mips::TGEU - 191 |
| 8403 |
{972, 1146, 3, 6 }, |
8403 |
{972, 1146, 3, 6 }, |
| 8404 |
// Mips::TGEU_MM - 192 |
8404 |
// Mips::TGEU_MM - 192 |
| 8405 |
{972, 1152, 3, 4 }, |
8405 |
{972, 1152, 3, 4 }, |
| 8406 |
// Mips::TGE_MM - 193 |
8406 |
// Mips::TGE_MM - 193 |
| 8407 |
{961, 1156, 3, 4 }, |
8407 |
{961, 1156, 3, 4 }, |
| 8408 |
// Mips::TLT - 194 |
8408 |
// Mips::TLT - 194 |
| 8409 |
{984, 1160, 3, 6 }, |
8409 |
{984, 1160, 3, 6 }, |
| 8410 |
// Mips::TLTU - 195 |
8410 |
// Mips::TLTU - 195 |
| 8411 |
{995, 1166, 3, 6 }, |
8411 |
{995, 1166, 3, 6 }, |
| 8412 |
// Mips::TLTU_MM - 196 |
8412 |
// Mips::TLTU_MM - 196 |
| 8413 |
{995, 1172, 3, 4 }, |
8413 |
{995, 1172, 3, 4 }, |
| 8414 |
// Mips::TLT_MM - 197 |
8414 |
// Mips::TLT_MM - 197 |
| 8415 |
{984, 1176, 3, 4 }, |
8415 |
{984, 1176, 3, 4 }, |
| 8416 |
// Mips::TNE - 198 |
8416 |
// Mips::TNE - 198 |
| 8417 |
{1007, 1180, 3, 6 }, |
8417 |
{1007, 1180, 3, 6 }, |
| 8418 |
// Mips::TNE_MM - 199 |
8418 |
// Mips::TNE_MM - 199 |
| 8419 |
{1007, 1186, 3, 4 }, |
8419 |
{1007, 1186, 3, 4 }, |
| 8420 |
// Mips::WAIT_MM - 200 |
8420 |
// Mips::WAIT_MM - 200 |
| 8421 |
{1018, 1190, 1, 2 }, |
8421 |
{1018, 1190, 1, 2 }, |
| 8422 |
// Mips::WRDSP - 201 |
8422 |
// Mips::WRDSP - 201 |
| 8423 |
{1023, 1192, 2, 4 }, |
8423 |
{1023, 1192, 2, 4 }, |
| 8424 |
// Mips::WRDSP_MM - 202 |
8424 |
// Mips::WRDSP_MM - 202 |
| 8425 |
{1023, 1196, 2, 4 }, |
8425 |
{1023, 1196, 2, 4 }, |
| 8426 |
// Mips::YIELD - 203 |
8426 |
// Mips::YIELD - 203 |
| 8427 |
{1032, 1200, 2, 4 }, |
8427 |
{1032, 1200, 2, 4 }, |
| 8428 |
}; |
8428 |
}; |
| 8429 |
|
8429 |
|
| 8430 |
static const AliasPatternCond Conds[] = { |
8430 |
static const AliasPatternCond Conds[] = { |
| 8431 |
// (MFTACX GPR32Opnd:$rt, AC0) - 0 |
8431 |
// (MFTACX GPR32Opnd:$rt, AC0) - 0 |
| 8432 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
8432 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 8433 |
{AliasPatternCond::K_Reg, Mips::AC0}, |
8433 |
{AliasPatternCond::K_Reg, Mips::AC0}, |
| 8434 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
8434 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
| 8435 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8435 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8436 |
// (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0) - 4 |
8436 |
// (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0) - 4 |
| 8437 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
8437 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 8438 |
{AliasPatternCond::K_RegClass, Mips::COP0RegClassID}, |
8438 |
{AliasPatternCond::K_RegClass, Mips::COP0RegClassID}, |
| 8439 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
8439 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 8440 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
8440 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
| 8441 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8441 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8442 |
// (MFTHI GPR32Opnd:$rt, AC0) - 9 |
8442 |
// (MFTHI GPR32Opnd:$rt, AC0) - 9 |
| 8443 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
8443 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 8444 |
{AliasPatternCond::K_Reg, Mips::AC0}, |
8444 |
{AliasPatternCond::K_Reg, Mips::AC0}, |
| 8445 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
8445 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
| 8446 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8446 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8447 |
// (MFTLO GPR32Opnd:$rt, AC0) - 13 |
8447 |
// (MFTLO GPR32Opnd:$rt, AC0) - 13 |
| 8448 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
8448 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 8449 |
{AliasPatternCond::K_Reg, Mips::AC0}, |
8449 |
{AliasPatternCond::K_Reg, Mips::AC0}, |
| 8450 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
8450 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
| 8451 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8451 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8452 |
// (MTTACX AC0, GPR32Opnd:$rt) - 17 |
8452 |
// (MTTACX AC0, GPR32Opnd:$rt) - 17 |
| 8453 |
{AliasPatternCond::K_Reg, Mips::AC0}, |
8453 |
{AliasPatternCond::K_Reg, Mips::AC0}, |
| 8454 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
8454 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 8455 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
8455 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
| 8456 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8456 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8457 |
// (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0) - 21 |
8457 |
// (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0) - 21 |
| 8458 |
{AliasPatternCond::K_RegClass, Mips::COP0RegClassID}, |
8458 |
{AliasPatternCond::K_RegClass, Mips::COP0RegClassID}, |
| 8459 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
8459 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 8460 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
8460 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 8461 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
8461 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
| 8462 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8462 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8463 |
// (MTTHI AC0, GPR32Opnd:$rt) - 26 |
8463 |
// (MTTHI AC0, GPR32Opnd:$rt) - 26 |
| 8464 |
{AliasPatternCond::K_Reg, Mips::AC0}, |
8464 |
{AliasPatternCond::K_Reg, Mips::AC0}, |
| 8465 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
8465 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 8466 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
8466 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
| 8467 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8467 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8468 |
// (MTTLO AC0, GPR32Opnd:$rt) - 30 |
8468 |
// (MTTLO AC0, GPR32Opnd:$rt) - 30 |
| 8469 |
{AliasPatternCond::K_Reg, Mips::AC0}, |
8469 |
{AliasPatternCond::K_Reg, Mips::AC0}, |
| 8470 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
8470 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 8471 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
8471 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
| 8472 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8472 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8473 |
// (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm) - 34 |
8473 |
// (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm) - 34 |
| 8474 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
8474 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 8475 |
{AliasPatternCond::K_TiedReg, 0}, |
8475 |
{AliasPatternCond::K_TiedReg, 0}, |
| 8476 |
{AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit}, |
8476 |
{AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit}, |
| 8477 |
// (NORImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 37 |
8477 |
// (NORImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 37 |
| 8478 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
8478 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 8479 |
{AliasPatternCond::K_TiedReg, 0}, |
8479 |
{AliasPatternCond::K_TiedReg, 0}, |
| 8480 |
{AliasPatternCond::K_Feature, Mips::FeatureGP64Bit}, |
8480 |
{AliasPatternCond::K_Feature, Mips::FeatureGP64Bit}, |
| 8481 |
// (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 40 |
8481 |
// (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 40 |
| 8482 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
8482 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 8483 |
{AliasPatternCond::K_TiedReg, 0}, |
8483 |
{AliasPatternCond::K_TiedReg, 0}, |
| 8484 |
{AliasPatternCond::K_Feature, Mips::FeatureGP64Bit}, |
8484 |
{AliasPatternCond::K_Feature, Mips::FeatureGP64Bit}, |
| 8485 |
// (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 43 |
8485 |
// (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 43 |
| 8486 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
8486 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 8487 |
{AliasPatternCond::K_TiedReg, 0}, |
8487 |
{AliasPatternCond::K_TiedReg, 0}, |
| 8488 |
{AliasPatternCond::K_Feature, Mips::FeatureGP64Bit}, |
8488 |
{AliasPatternCond::K_Feature, Mips::FeatureGP64Bit}, |
| 8489 |
// (ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm) - 46 |
8489 |
// (ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm) - 46 |
| 8490 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
8490 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 8491 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8491 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8492 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
8492 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 8493 |
// (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm) - 49 |
8493 |
// (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm) - 49 |
| 8494 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
8494 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 8495 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8495 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8496 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
8496 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 8497 |
// (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 52 |
8497 |
// (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 52 |
| 8498 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
8498 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 8499 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
8499 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 8500 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
8500 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 8501 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8501 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8502 |
{AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit}, |
8502 |
{AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit}, |
| 8503 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8503 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8504 |
// (BC1F FCC0, brtarget:$offset) - 58 |
8504 |
// (BC1F FCC0, brtarget:$offset) - 58 |
| 8505 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8505 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8506 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8506 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8507 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8507 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8508 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8508 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8509 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8509 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8510 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8510 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8511 |
// (BC1FL FCC0, brtarget:$offset) - 64 |
8511 |
// (BC1FL FCC0, brtarget:$offset) - 64 |
| 8512 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8512 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8513 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8513 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8514 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
8514 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
| 8515 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8515 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8516 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8516 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8517 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8517 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8518 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8518 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8519 |
// (BC1F_MM FCC0, brtarget:$offset) - 71 |
8519 |
// (BC1F_MM FCC0, brtarget:$offset) - 71 |
| 8520 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8520 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8521 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8521 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8522 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8522 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8523 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8523 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8524 |
// (BC1T FCC0, brtarget:$offset) - 75 |
8524 |
// (BC1T FCC0, brtarget:$offset) - 75 |
| 8525 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8525 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8526 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8526 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8527 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8527 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8528 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8528 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8529 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8529 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8530 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8530 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8531 |
// (BC1TL FCC0, brtarget:$offset) - 81 |
8531 |
// (BC1TL FCC0, brtarget:$offset) - 81 |
| 8532 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8532 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8533 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8533 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8534 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
8534 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
| 8535 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8535 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8536 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8536 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8537 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8537 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8538 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8538 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8539 |
// (BC1T_MM FCC0, brtarget:$offset) - 88 |
8539 |
// (BC1T_MM FCC0, brtarget:$offset) - 88 |
| 8540 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8540 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8541 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8541 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8542 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8542 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8543 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8543 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8544 |
// (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 92 |
8544 |
// (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 92 |
| 8545 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
8545 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 8546 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
8546 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 8547 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8547 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8548 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
8548 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
| 8549 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8549 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8550 |
// (BGEZAL ZERO, brtarget:$offset) - 97 |
8550 |
// (BGEZAL ZERO, brtarget:$offset) - 97 |
| 8551 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
8551 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 8552 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8552 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8553 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8553 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8554 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8554 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8555 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8555 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8556 |
// (BGEZAL_MM ZERO, brtarget_mm:$offset) - 102 |
8556 |
// (BGEZAL_MM ZERO, brtarget_mm:$offset) - 102 |
| 8557 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
8557 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 8558 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8558 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8559 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8559 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8560 |
// (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 105 |
8560 |
// (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 105 |
| 8561 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
8561 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 8562 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
8562 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 8563 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8563 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8564 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
8564 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
| 8565 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8565 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8566 |
// (BREAK 0, 0) - 110 |
8566 |
// (BREAK 0, 0) - 110 |
| 8567 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
8567 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 8568 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
8568 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 8569 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8569 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8570 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8570 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8571 |
// (BREAK uimm10:$imm, 0) - 114 |
8571 |
// (BREAK uimm10:$imm, 0) - 114 |
| 8572 |
{AliasPatternCond::K_Ignore, 0}, |
8572 |
{AliasPatternCond::K_Ignore, 0}, |
| 8573 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
8573 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 8574 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8574 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8575 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8575 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8576 |
// (BREAK_MM 0, 0) - 118 |
8576 |
// (BREAK_MM 0, 0) - 118 |
| 8577 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
8577 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 8578 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
8578 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 8579 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8579 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8580 |
// (BREAK_MM uimm10:$imm, 0) - 121 |
8580 |
// (BREAK_MM uimm10:$imm, 0) - 121 |
| 8581 |
{AliasPatternCond::K_Ignore, 0}, |
8581 |
{AliasPatternCond::K_Ignore, 0}, |
| 8582 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
8582 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 8583 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8583 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8584 |
// (C_EQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 124 |
8584 |
// (C_EQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 124 |
| 8585 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8585 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8586 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8586 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8587 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8587 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8588 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8588 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8589 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
8589 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 8590 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8590 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8591 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8591 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8592 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8592 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8593 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8593 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8594 |
// (C_EQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 133 |
8594 |
// (C_EQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 133 |
| 8595 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8595 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8596 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8596 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8597 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8597 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8598 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8598 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8599 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
8599 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 8600 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8600 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8601 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8601 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8602 |
// (C_EQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 140 |
8602 |
// (C_EQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 140 |
| 8603 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8603 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8604 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8604 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8605 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8605 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8606 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8606 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8607 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
8607 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 8608 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8608 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8609 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8609 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8610 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8610 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8611 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8611 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8612 |
// (C_EQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 149 |
8612 |
// (C_EQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 149 |
| 8613 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8613 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8614 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8614 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8615 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8615 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8616 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8616 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8617 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
8617 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 8618 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8618 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8619 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8619 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8620 |
// (C_EQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 156 |
8620 |
// (C_EQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 156 |
| 8621 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8621 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8622 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8622 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8623 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8623 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8624 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8624 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8625 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8625 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8626 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8626 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8627 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8627 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8628 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8628 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8629 |
// (C_EQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 164 |
8629 |
// (C_EQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 164 |
| 8630 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8630 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8631 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8631 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8632 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8632 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8633 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8633 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8634 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8634 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8635 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8635 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8636 |
// (C_F_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 170 |
8636 |
// (C_F_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 170 |
| 8637 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8637 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8638 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8638 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8639 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8639 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8640 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8640 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8641 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
8641 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 8642 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8642 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8643 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8643 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8644 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8644 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8645 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8645 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8646 |
// (C_F_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 179 |
8646 |
// (C_F_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 179 |
| 8647 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8647 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8648 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8648 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8649 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8649 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8650 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8650 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8651 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
8651 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 8652 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8652 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8653 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8653 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8654 |
// (C_F_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 186 |
8654 |
// (C_F_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 186 |
| 8655 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8655 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8656 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8656 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8657 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8657 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8658 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8658 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8659 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
8659 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 8660 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8660 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8661 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8661 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8662 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8662 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8663 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8663 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8664 |
// (C_F_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 195 |
8664 |
// (C_F_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 195 |
| 8665 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8665 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8666 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8666 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8667 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8667 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8668 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8668 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8669 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
8669 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 8670 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8670 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8671 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8671 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8672 |
// (C_F_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 202 |
8672 |
// (C_F_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 202 |
| 8673 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8673 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8674 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8674 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8675 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8675 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8676 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8676 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8677 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8677 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8678 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8678 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8679 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8679 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8680 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8680 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8681 |
// (C_F_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 210 |
8681 |
// (C_F_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 210 |
| 8682 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8682 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8683 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8683 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8684 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8684 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8685 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8685 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8686 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8686 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8687 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8687 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8688 |
// (C_LE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 216 |
8688 |
// (C_LE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 216 |
| 8689 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8689 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8690 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8690 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8691 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8691 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8692 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8692 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8693 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
8693 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 8694 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8694 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8695 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8695 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8696 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8696 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8697 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8697 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8698 |
// (C_LE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 225 |
8698 |
// (C_LE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 225 |
| 8699 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8699 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8700 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8700 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8701 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8701 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8702 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8702 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8703 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
8703 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 8704 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8704 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8705 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8705 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8706 |
// (C_LE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 232 |
8706 |
// (C_LE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 232 |
| 8707 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8707 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8708 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8708 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8709 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8709 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8710 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8710 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8711 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
8711 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 8712 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8712 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8713 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8713 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8714 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8714 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8715 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8715 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8716 |
// (C_LE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 241 |
8716 |
// (C_LE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 241 |
| 8717 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8717 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8718 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8718 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8719 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8719 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8720 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8720 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8721 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
8721 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 8722 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8722 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8723 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8723 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8724 |
// (C_LE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 248 |
8724 |
// (C_LE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 248 |
| 8725 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8725 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8726 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8726 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8727 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8727 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8728 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8728 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8729 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8729 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8730 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8730 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8731 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8731 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8732 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8732 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8733 |
// (C_LE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 256 |
8733 |
// (C_LE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 256 |
| 8734 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8734 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8735 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8735 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8736 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8736 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8737 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8737 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8738 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8738 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8739 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8739 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8740 |
// (C_LT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 262 |
8740 |
// (C_LT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 262 |
| 8741 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8741 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8742 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8742 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8743 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8743 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8744 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8744 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8745 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
8745 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 8746 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8746 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8747 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8747 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8748 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8748 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8749 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8749 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8750 |
// (C_LT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 271 |
8750 |
// (C_LT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 271 |
| 8751 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8751 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8752 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8752 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8753 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8753 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8754 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8754 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8755 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
8755 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 8756 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8756 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8757 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8757 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8758 |
// (C_LT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 278 |
8758 |
// (C_LT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 278 |
| 8759 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8759 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8760 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8760 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8761 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8761 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8762 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8762 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8763 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
8763 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 8764 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8764 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8765 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8765 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8766 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8766 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8767 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8767 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8768 |
// (C_LT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 287 |
8768 |
// (C_LT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 287 |
| 8769 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8769 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8770 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8770 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8771 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8771 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8772 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8772 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8773 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
8773 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 8774 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8774 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8775 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8775 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8776 |
// (C_LT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 294 |
8776 |
// (C_LT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 294 |
| 8777 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8777 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8778 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8778 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8779 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8779 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8780 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8780 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8781 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8781 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8782 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8782 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8783 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8783 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8784 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8784 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8785 |
// (C_LT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 302 |
8785 |
// (C_LT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 302 |
| 8786 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8786 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8787 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8787 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8788 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8788 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8789 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8789 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8790 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8790 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8791 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8791 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8792 |
// (C_NGE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 308 |
8792 |
// (C_NGE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 308 |
| 8793 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8793 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8794 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8794 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8795 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8795 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8796 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8796 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8797 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
8797 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 8798 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8798 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8799 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8799 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8800 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8800 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8801 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8801 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8802 |
// (C_NGE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 317 |
8802 |
// (C_NGE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 317 |
| 8803 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8803 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8804 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8804 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8805 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8805 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8806 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8806 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8807 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
8807 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 8808 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8808 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8809 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8809 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8810 |
// (C_NGE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 324 |
8810 |
// (C_NGE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 324 |
| 8811 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8811 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8812 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8812 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8813 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8813 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8814 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8814 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8815 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
8815 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 8816 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8816 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8817 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8817 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8818 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8818 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8819 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8819 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8820 |
// (C_NGE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 333 |
8820 |
// (C_NGE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 333 |
| 8821 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8821 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8822 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8822 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8823 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8823 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8824 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8824 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8825 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
8825 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 8826 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8826 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8827 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8827 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8828 |
// (C_NGE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 340 |
8828 |
// (C_NGE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 340 |
| 8829 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8829 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8830 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8830 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8831 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8831 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8832 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8832 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8833 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8833 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8834 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8834 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8835 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8835 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8836 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8836 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8837 |
// (C_NGE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 348 |
8837 |
// (C_NGE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 348 |
| 8838 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8838 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8839 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8839 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8840 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8840 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8841 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8841 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8842 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8842 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8843 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8843 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8844 |
// (C_NGLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 354 |
8844 |
// (C_NGLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 354 |
| 8845 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8845 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8846 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8846 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8847 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8847 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8848 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8848 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8849 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
8849 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 8850 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8850 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8851 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8851 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8852 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8852 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8853 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8853 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8854 |
// (C_NGLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 363 |
8854 |
// (C_NGLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 363 |
| 8855 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8855 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8856 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8856 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8857 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8857 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8858 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8858 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8859 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
8859 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 8860 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8860 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8861 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8861 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8862 |
// (C_NGLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 370 |
8862 |
// (C_NGLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 370 |
| 8863 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8863 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8864 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8864 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8865 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8865 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8866 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8866 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8867 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
8867 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 8868 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8868 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8869 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8869 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8870 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8870 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8871 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8871 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8872 |
// (C_NGLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 379 |
8872 |
// (C_NGLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 379 |
| 8873 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8873 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8874 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8874 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8875 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8875 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8876 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8876 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8877 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
8877 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 8878 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8878 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8879 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8879 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8880 |
// (C_NGLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 386 |
8880 |
// (C_NGLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 386 |
| 8881 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8881 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8882 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8882 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8883 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8883 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8884 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8884 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8885 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8885 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8886 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8886 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8887 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8887 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8888 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8888 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8889 |
// (C_NGLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 394 |
8889 |
// (C_NGLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 394 |
| 8890 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8890 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8891 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8891 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8892 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8892 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8893 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8893 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8894 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8894 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8895 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8895 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8896 |
// (C_NGL_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 400 |
8896 |
// (C_NGL_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 400 |
| 8897 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8897 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8898 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8898 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8899 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8899 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8900 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8900 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8901 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
8901 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 8902 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8902 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8903 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8903 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8904 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8904 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8905 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8905 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8906 |
// (C_NGL_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 409 |
8906 |
// (C_NGL_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 409 |
| 8907 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8907 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8908 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8908 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8909 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8909 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8910 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8910 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8911 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
8911 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 8912 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8912 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8913 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8913 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8914 |
// (C_NGL_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 416 |
8914 |
// (C_NGL_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 416 |
| 8915 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8915 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8916 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8916 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8917 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8917 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8918 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8918 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8919 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
8919 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 8920 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8920 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8921 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8921 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8922 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8922 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8923 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8923 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8924 |
// (C_NGL_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 425 |
8924 |
// (C_NGL_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 425 |
| 8925 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8925 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8926 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8926 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8927 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8927 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8928 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8928 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8929 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
8929 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 8930 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8930 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8931 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8931 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8932 |
// (C_NGL_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 432 |
8932 |
// (C_NGL_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 432 |
| 8933 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8933 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8934 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8934 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8935 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8935 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8936 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8936 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8937 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8937 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8938 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8938 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8939 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8939 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8940 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8940 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8941 |
// (C_NGL_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 440 |
8941 |
// (C_NGL_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 440 |
| 8942 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8942 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8943 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8943 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8944 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8944 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8945 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8945 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8946 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8946 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8947 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8947 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8948 |
// (C_NGT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 446 |
8948 |
// (C_NGT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 446 |
| 8949 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8949 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8950 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8950 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8951 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8951 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8952 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8952 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8953 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
8953 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 8954 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8954 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8955 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8955 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8956 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8956 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8957 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8957 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8958 |
// (C_NGT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 455 |
8958 |
// (C_NGT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 455 |
| 8959 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8959 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8960 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8960 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8961 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
8961 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 8962 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8962 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8963 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
8963 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 8964 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8964 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8965 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8965 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8966 |
// (C_NGT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 462 |
8966 |
// (C_NGT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 462 |
| 8967 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8967 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8968 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8968 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8969 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8969 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8970 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8970 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8971 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
8971 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 8972 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8972 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8973 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8973 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8974 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8974 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8975 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8975 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8976 |
// (C_NGT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 471 |
8976 |
// (C_NGT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 471 |
| 8977 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8977 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8978 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8978 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8979 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
8979 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 8980 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8980 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8981 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
8981 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 8982 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8982 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8983 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8983 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8984 |
// (C_NGT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 478 |
8984 |
// (C_NGT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 478 |
| 8985 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8985 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8986 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8986 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8987 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8987 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8988 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
8988 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 8989 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8989 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8990 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
8990 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 8991 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8991 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 8992 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
8992 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 8993 |
// (C_NGT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 486 |
8993 |
// (C_NGT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 486 |
| 8994 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
8994 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 8995 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8995 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8996 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
8996 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 8997 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
8997 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 8998 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
8998 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 8999 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
8999 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9000 |
// (C_OLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 492 |
9000 |
// (C_OLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 492 |
| 9001 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9001 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9002 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9002 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9003 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9003 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9004 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9004 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9005 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
9005 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 9006 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9006 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9007 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9007 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9008 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9008 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9009 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9009 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9010 |
// (C_OLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 501 |
9010 |
// (C_OLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 501 |
| 9011 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9011 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9012 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9012 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9013 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9013 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9014 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9014 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9015 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
9015 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 9016 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9016 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9017 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9017 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9018 |
// (C_OLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 508 |
9018 |
// (C_OLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 508 |
| 9019 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9019 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9020 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9020 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9021 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9021 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9022 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9022 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9023 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
9023 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 9024 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9024 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9025 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9025 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9026 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9026 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9027 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9027 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9028 |
// (C_OLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 517 |
9028 |
// (C_OLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 517 |
| 9029 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9029 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9030 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9030 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9031 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9031 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9032 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9032 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9033 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
9033 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 9034 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9034 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9035 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9035 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9036 |
// (C_OLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 524 |
9036 |
// (C_OLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 524 |
| 9037 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9037 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9038 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9038 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9039 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9039 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9040 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9040 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9041 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9041 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9042 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9042 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9043 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9043 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9044 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9044 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9045 |
// (C_OLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 532 |
9045 |
// (C_OLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 532 |
| 9046 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9046 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9047 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9047 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9048 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9048 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9049 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9049 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9050 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9050 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9051 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9051 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9052 |
// (C_OLT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 538 |
9052 |
// (C_OLT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 538 |
| 9053 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9053 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9054 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9054 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9055 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9055 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9056 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9056 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9057 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
9057 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 9058 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9058 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9059 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9059 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9060 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9060 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9061 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9061 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9062 |
// (C_OLT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 547 |
9062 |
// (C_OLT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 547 |
| 9063 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9063 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9064 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9064 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9065 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9065 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9066 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9066 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9067 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
9067 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 9068 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9068 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9069 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9069 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9070 |
// (C_OLT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 554 |
9070 |
// (C_OLT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 554 |
| 9071 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9071 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9072 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9072 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9073 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9073 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9074 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9074 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9075 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
9075 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 9076 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9076 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9077 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9077 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9078 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9078 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9079 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9079 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9080 |
// (C_OLT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 563 |
9080 |
// (C_OLT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 563 |
| 9081 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9081 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9082 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9082 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9083 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9083 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9084 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9084 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9085 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
9085 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 9086 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9086 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9087 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9087 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9088 |
// (C_OLT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 570 |
9088 |
// (C_OLT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 570 |
| 9089 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9089 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9090 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9090 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9091 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9091 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9092 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9092 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9093 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9093 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9094 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9094 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9095 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9095 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9096 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9096 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9097 |
// (C_OLT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 578 |
9097 |
// (C_OLT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 578 |
| 9098 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9098 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9099 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9099 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9100 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9100 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9101 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9101 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9102 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9102 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9103 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9103 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9104 |
// (C_SEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 584 |
9104 |
// (C_SEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 584 |
| 9105 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9105 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9106 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9106 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9107 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9107 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9108 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9108 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9109 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
9109 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 9110 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9110 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9111 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9111 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9112 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9112 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9113 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9113 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9114 |
// (C_SEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 593 |
9114 |
// (C_SEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 593 |
| 9115 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9115 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9116 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9116 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9117 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9117 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9118 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9118 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9119 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
9119 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 9120 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9120 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9121 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9121 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9122 |
// (C_SEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 600 |
9122 |
// (C_SEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 600 |
| 9123 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9123 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9124 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9124 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9125 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9125 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9126 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9126 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9127 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
9127 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 9128 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9128 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9129 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9129 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9130 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9130 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9131 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9131 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9132 |
// (C_SEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 609 |
9132 |
// (C_SEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 609 |
| 9133 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9133 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9134 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9134 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9135 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9135 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9136 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9136 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9137 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
9137 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 9138 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9138 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9139 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9139 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9140 |
// (C_SEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 616 |
9140 |
// (C_SEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 616 |
| 9141 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9141 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9142 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9142 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9143 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9143 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9144 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9144 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9145 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9145 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9146 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9146 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9147 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9147 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9148 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9148 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9149 |
// (C_SEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 624 |
9149 |
// (C_SEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 624 |
| 9150 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9150 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9151 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9151 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9152 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9152 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9153 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9153 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9154 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9154 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9155 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9155 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9156 |
// (C_SF_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 630 |
9156 |
// (C_SF_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 630 |
| 9157 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9157 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9158 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9158 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9159 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9159 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9160 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9160 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9161 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
9161 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 9162 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9162 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9163 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9163 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9164 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9164 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9165 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9165 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9166 |
// (C_SF_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 639 |
9166 |
// (C_SF_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 639 |
| 9167 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9167 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9168 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9168 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9169 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9169 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9170 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9170 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9171 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
9171 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 9172 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9172 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9173 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9173 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9174 |
// (C_SF_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 646 |
9174 |
// (C_SF_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 646 |
| 9175 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9175 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9176 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9176 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9177 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9177 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9178 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9178 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9179 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
9179 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 9180 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9180 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9181 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9181 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9182 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9182 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9183 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9183 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9184 |
// (C_SF_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 655 |
9184 |
// (C_SF_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 655 |
| 9185 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9185 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9186 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9186 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9187 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9187 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9188 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9188 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9189 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
9189 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 9190 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9190 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9191 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9191 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9192 |
// (C_SF_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 662 |
9192 |
// (C_SF_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 662 |
| 9193 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9193 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9194 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9194 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9195 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9195 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9196 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9196 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9197 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9197 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9198 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9198 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9199 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9199 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9200 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9200 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9201 |
// (C_SF_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 670 |
9201 |
// (C_SF_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 670 |
| 9202 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9202 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9203 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9203 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9204 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9204 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9205 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9205 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9206 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9206 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9207 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9207 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9208 |
// (C_UEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 676 |
9208 |
// (C_UEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 676 |
| 9209 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9209 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9210 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9210 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9211 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9211 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9212 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9212 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9213 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
9213 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 9214 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9214 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9215 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9215 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9216 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9216 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9217 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9217 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9218 |
// (C_UEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 685 |
9218 |
// (C_UEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 685 |
| 9219 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9219 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9220 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9220 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9221 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9221 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9222 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9222 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9223 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
9223 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 9224 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9224 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9225 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9225 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9226 |
// (C_UEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 692 |
9226 |
// (C_UEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 692 |
| 9227 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9227 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9228 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9228 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9229 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9229 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9230 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9230 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9231 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
9231 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 9232 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9232 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9233 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9233 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9234 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9234 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9235 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9235 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9236 |
// (C_UEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 701 |
9236 |
// (C_UEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 701 |
| 9237 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9237 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9238 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9238 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9239 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9239 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9240 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9240 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9241 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
9241 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 9242 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9242 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9243 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9243 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9244 |
// (C_UEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 708 |
9244 |
// (C_UEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 708 |
| 9245 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9245 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9246 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9246 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9247 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9247 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9248 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9248 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9249 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9249 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9250 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9250 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9251 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9251 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9252 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9252 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9253 |
// (C_UEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 716 |
9253 |
// (C_UEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 716 |
| 9254 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9254 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9255 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9255 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9256 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9256 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9257 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9257 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9258 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9258 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9259 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9259 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9260 |
// (C_ULE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 722 |
9260 |
// (C_ULE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 722 |
| 9261 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9261 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9262 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9262 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9263 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9263 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9264 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9264 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9265 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
9265 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 9266 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9266 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9267 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9267 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9268 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9268 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9269 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9269 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9270 |
// (C_ULE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 731 |
9270 |
// (C_ULE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 731 |
| 9271 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9271 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9272 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9272 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9273 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9273 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9274 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9274 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9275 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
9275 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 9276 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9276 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9277 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9277 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9278 |
// (C_ULE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 738 |
9278 |
// (C_ULE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 738 |
| 9279 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9279 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9280 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9280 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9281 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9281 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9282 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9282 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9283 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
9283 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 9284 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9284 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9285 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9285 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9286 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9286 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9287 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9287 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9288 |
// (C_ULE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 747 |
9288 |
// (C_ULE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 747 |
| 9289 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9289 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9290 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9290 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9291 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9291 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9292 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9292 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9293 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
9293 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 9294 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9294 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9295 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9295 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9296 |
// (C_ULE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 754 |
9296 |
// (C_ULE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 754 |
| 9297 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9297 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9298 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9298 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9299 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9299 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9300 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9300 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9301 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9301 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9302 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9302 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9303 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9303 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9304 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9304 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9305 |
// (C_ULE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 762 |
9305 |
// (C_ULE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 762 |
| 9306 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9306 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9307 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9307 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9308 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9308 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9309 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9309 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9310 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9310 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9311 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9311 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9312 |
// (C_ULT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 768 |
9312 |
// (C_ULT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 768 |
| 9313 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9313 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9314 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9314 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9315 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9315 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9316 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9316 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9317 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
9317 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 9318 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9318 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9319 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9319 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9320 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9320 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9321 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9321 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9322 |
// (C_ULT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 777 |
9322 |
// (C_ULT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 777 |
| 9323 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9323 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9324 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9324 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9325 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9325 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9326 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9326 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9327 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
9327 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 9328 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9328 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9329 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9329 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9330 |
// (C_ULT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 784 |
9330 |
// (C_ULT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 784 |
| 9331 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9331 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9332 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9332 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9333 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9333 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9334 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9334 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9335 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
9335 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 9336 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9336 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9337 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9337 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9338 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9338 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9339 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9339 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9340 |
// (C_ULT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 793 |
9340 |
// (C_ULT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 793 |
| 9341 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9341 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9342 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9342 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9343 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9343 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9344 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9344 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9345 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
9345 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 9346 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9346 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9347 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9347 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9348 |
// (C_ULT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 800 |
9348 |
// (C_ULT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 800 |
| 9349 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9349 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9350 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9350 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9351 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9351 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9352 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9352 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9353 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9353 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9354 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9354 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9355 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9355 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9356 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9356 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9357 |
// (C_ULT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 808 |
9357 |
// (C_ULT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 808 |
| 9358 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9358 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9359 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9359 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9360 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9360 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9361 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9361 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9362 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9362 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9363 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9363 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9364 |
// (C_UN_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 814 |
9364 |
// (C_UN_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 814 |
| 9365 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9365 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9366 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9366 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9367 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9367 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9368 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9368 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9369 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
9369 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 9370 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9370 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9371 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9371 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9372 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9372 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9373 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9373 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9374 |
// (C_UN_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 823 |
9374 |
// (C_UN_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 823 |
| 9375 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9375 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9376 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9376 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9377 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
9377 |
{AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID}, |
| 9378 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9378 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9379 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
9379 |
{AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit}, |
| 9380 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9380 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9381 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9381 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9382 |
// (C_UN_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 830 |
9382 |
// (C_UN_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 830 |
| 9383 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9383 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9384 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9384 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9385 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9385 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9386 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9386 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9387 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
9387 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 9388 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9388 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9389 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9389 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9390 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9390 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9391 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9391 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9392 |
// (C_UN_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 839 |
9392 |
// (C_UN_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 839 |
| 9393 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9393 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9394 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9394 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9395 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
9395 |
{AliasPatternCond::K_RegClass, Mips::FGR64RegClassID}, |
| 9396 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9396 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9397 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
9397 |
{AliasPatternCond::K_Feature, Mips::FeatureFP64Bit}, |
| 9398 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9398 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9399 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9399 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9400 |
// (C_UN_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 846 |
9400 |
// (C_UN_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 846 |
| 9401 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9401 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9402 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9402 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9403 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9403 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9404 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9404 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9405 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9405 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9406 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9406 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9407 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9407 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9408 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9408 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9409 |
// (C_UN_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 854 |
9409 |
// (C_UN_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 854 |
| 9410 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
9410 |
{AliasPatternCond::K_Reg, Mips::FCC0}, |
| 9411 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9411 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9412 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
9412 |
{AliasPatternCond::K_RegClass, Mips::FGR32RegClassID}, |
| 9413 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9413 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9414 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9414 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9415 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
9415 |
{AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat}, |
| 9416 |
// (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 860 |
9416 |
// (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 860 |
| 9417 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
9417 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 9418 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
9418 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 9419 |
{AliasPatternCond::K_Reg, Mips::ZERO_64}, |
9419 |
{AliasPatternCond::K_Reg, Mips::ZERO_64}, |
| 9420 |
{AliasPatternCond::K_Feature, Mips::FeatureGP64Bit}, |
9420 |
{AliasPatternCond::K_Feature, Mips::FeatureGP64Bit}, |
| 9421 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9421 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9422 |
// (DI ZERO) - 865 |
9422 |
// (DI ZERO) - 865 |
| 9423 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9423 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9424 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9424 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9425 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r2}, |
9425 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r2}, |
| 9426 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9426 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9427 |
// (DIV GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 869 |
9427 |
// (DIV GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 869 |
| 9428 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9428 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9429 |
{AliasPatternCond::K_TiedReg, 0}, |
9429 |
{AliasPatternCond::K_TiedReg, 0}, |
| 9430 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9430 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9431 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9431 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9432 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9432 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9433 |
// (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 874 |
9433 |
// (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 874 |
| 9434 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9434 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9435 |
{AliasPatternCond::K_TiedReg, 0}, |
9435 |
{AliasPatternCond::K_TiedReg, 0}, |
| 9436 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9436 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9437 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9437 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9438 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9438 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9439 |
// (DI_MM ZERO) - 879 |
9439 |
// (DI_MM ZERO) - 879 |
| 9440 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9440 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9441 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9441 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9442 |
// (DI_MMR6 ZERO) - 881 |
9442 |
// (DI_MMR6 ZERO) - 881 |
| 9443 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9443 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9444 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9444 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9445 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9445 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9446 |
// (DMT ZERO) - 884 |
9446 |
// (DMT ZERO) - 884 |
| 9447 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9447 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9448 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
9448 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
| 9449 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9449 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9450 |
// (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 887 |
9450 |
// (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 887 |
| 9451 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
9451 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 9452 |
{AliasPatternCond::K_Reg, Mips::ZERO_64}, |
9452 |
{AliasPatternCond::K_Reg, Mips::ZERO_64}, |
| 9453 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
9453 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 9454 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9454 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9455 |
{AliasPatternCond::K_Feature, Mips::FeatureMips3}, |
9455 |
{AliasPatternCond::K_Feature, Mips::FeatureMips3}, |
| 9456 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9456 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9457 |
// (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 893 |
9457 |
// (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 893 |
| 9458 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
9458 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 9459 |
{AliasPatternCond::K_Reg, Mips::ZERO_64}, |
9459 |
{AliasPatternCond::K_Reg, Mips::ZERO_64}, |
| 9460 |
{AliasPatternCond::K_TiedReg, 0}, |
9460 |
{AliasPatternCond::K_TiedReg, 0}, |
| 9461 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9461 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9462 |
{AliasPatternCond::K_Feature, Mips::FeatureMips3}, |
9462 |
{AliasPatternCond::K_Feature, Mips::FeatureMips3}, |
| 9463 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9463 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9464 |
// (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 899 |
9464 |
// (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 899 |
| 9465 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
9465 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 9466 |
{AliasPatternCond::K_Reg, Mips::ZERO_64}, |
9466 |
{AliasPatternCond::K_Reg, Mips::ZERO_64}, |
| 9467 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
9467 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 9468 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9468 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9469 |
{AliasPatternCond::K_Feature, Mips::FeatureMips3}, |
9469 |
{AliasPatternCond::K_Feature, Mips::FeatureMips3}, |
| 9470 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9470 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9471 |
// (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 905 |
9471 |
// (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 905 |
| 9472 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
9472 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 9473 |
{AliasPatternCond::K_Reg, Mips::ZERO_64}, |
9473 |
{AliasPatternCond::K_Reg, Mips::ZERO_64}, |
| 9474 |
{AliasPatternCond::K_TiedReg, 0}, |
9474 |
{AliasPatternCond::K_TiedReg, 0}, |
| 9475 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9475 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9476 |
{AliasPatternCond::K_Feature, Mips::FeatureMips3}, |
9476 |
{AliasPatternCond::K_Feature, Mips::FeatureMips3}, |
| 9477 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9477 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9478 |
// (DVPE ZERO) - 911 |
9478 |
// (DVPE ZERO) - 911 |
| 9479 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9479 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9480 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
9480 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
| 9481 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9481 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9482 |
// (EI ZERO) - 914 |
9482 |
// (EI ZERO) - 914 |
| 9483 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9483 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9484 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9484 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9485 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r2}, |
9485 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r2}, |
| 9486 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9486 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9487 |
// (EI_MM ZERO) - 918 |
9487 |
// (EI_MM ZERO) - 918 |
| 9488 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9488 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9489 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9489 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9490 |
// (EI_MMR6 ZERO) - 920 |
9490 |
// (EI_MMR6 ZERO) - 920 |
| 9491 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9491 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9492 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9492 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9493 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9493 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9494 |
// (EMT ZERO) - 923 |
9494 |
// (EMT ZERO) - 923 |
| 9495 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9495 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9496 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
9496 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
| 9497 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9497 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9498 |
// (EVPE ZERO) - 926 |
9498 |
// (EVPE ZERO) - 926 |
| 9499 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9499 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9500 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
9500 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
| 9501 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9501 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9502 |
// (HYPCALL 0) - 929 |
9502 |
// (HYPCALL 0) - 929 |
| 9503 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9503 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9504 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9504 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9505 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r5}, |
9505 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r5}, |
| 9506 |
{AliasPatternCond::K_Feature, Mips::FeatureVirt}, |
9506 |
{AliasPatternCond::K_Feature, Mips::FeatureVirt}, |
| 9507 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9507 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9508 |
// (HYPCALL_MM 0) - 934 |
9508 |
// (HYPCALL_MM 0) - 934 |
| 9509 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9509 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9510 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9510 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9511 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r5}, |
9511 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r5}, |
| 9512 |
{AliasPatternCond::K_Feature, Mips::FeatureVirt}, |
9512 |
{AliasPatternCond::K_Feature, Mips::FeatureVirt}, |
| 9513 |
// (JALR ZERO, GPR32Opnd:$rs) - 938 |
9513 |
// (JALR ZERO, GPR32Opnd:$rs) - 938 |
| 9514 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9514 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9515 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9515 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9516 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9516 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9517 |
{AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit}, |
9517 |
{AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit}, |
| 9518 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9518 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9519 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9519 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9520 |
// (JALR64 ZERO_64, GPR64Opnd:$rs) - 944 |
9520 |
// (JALR64 ZERO_64, GPR64Opnd:$rs) - 944 |
| 9521 |
{AliasPatternCond::K_Reg, Mips::ZERO_64}, |
9521 |
{AliasPatternCond::K_Reg, Mips::ZERO_64}, |
| 9522 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
9522 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 9523 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9523 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9524 |
{AliasPatternCond::K_Feature, Mips::FeatureMips64r6}, |
9524 |
{AliasPatternCond::K_Feature, Mips::FeatureMips64r6}, |
| 9525 |
// (JALRC_HB_MMR6 RA, GPR32Opnd:$rs) - 948 |
9525 |
// (JALRC_HB_MMR6 RA, GPR32Opnd:$rs) - 948 |
| 9526 |
{AliasPatternCond::K_Reg, Mips::RA}, |
9526 |
{AliasPatternCond::K_Reg, Mips::RA}, |
| 9527 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9527 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9528 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9528 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9529 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9529 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9530 |
// (JALRC_MMR6 RA, GPR32Opnd:$rs) - 952 |
9530 |
// (JALRC_MMR6 RA, GPR32Opnd:$rs) - 952 |
| 9531 |
{AliasPatternCond::K_Reg, Mips::RA}, |
9531 |
{AliasPatternCond::K_Reg, Mips::RA}, |
| 9532 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9532 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9533 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9533 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9534 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9534 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9535 |
// (JALR_HB RA, GPR32Opnd:$rs) - 956 |
9535 |
// (JALR_HB RA, GPR32Opnd:$rs) - 956 |
| 9536 |
{AliasPatternCond::K_Reg, Mips::RA}, |
9536 |
{AliasPatternCond::K_Reg, Mips::RA}, |
| 9537 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9537 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9538 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9538 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9539 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32}, |
9539 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32}, |
| 9540 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9540 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9541 |
// (JALR_HB64 RA_64, GPR64Opnd:$rs) - 961 |
9541 |
// (JALR_HB64 RA_64, GPR64Opnd:$rs) - 961 |
| 9542 |
{AliasPatternCond::K_Reg, Mips::RA_64}, |
9542 |
{AliasPatternCond::K_Reg, Mips::RA_64}, |
| 9543 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
9543 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 9544 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9544 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9545 |
{AliasPatternCond::K_Feature, Mips::FeatureMips64}, |
9545 |
{AliasPatternCond::K_Feature, Mips::FeatureMips64}, |
| 9546 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9546 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9547 |
// (JIALC GPR32Opnd:$rs, 0) - 966 |
9547 |
// (JIALC GPR32Opnd:$rs, 0) - 966 |
| 9548 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9548 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9549 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9549 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9550 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9550 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9551 |
{AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit}, |
9551 |
{AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit}, |
| 9552 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9552 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9553 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9553 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9554 |
// (JIALC64 GPR64Opnd:$rs, 0) - 972 |
9554 |
// (JIALC64 GPR64Opnd:$rs, 0) - 972 |
| 9555 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
9555 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 9556 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9556 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9557 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9557 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9558 |
{AliasPatternCond::K_Feature, Mips::FeatureMips64r6}, |
9558 |
{AliasPatternCond::K_Feature, Mips::FeatureMips64r6}, |
| 9559 |
// (JIC GPR32Opnd:$rs, 0) - 976 |
9559 |
// (JIC GPR32Opnd:$rs, 0) - 976 |
| 9560 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9560 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9561 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9561 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9562 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9562 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9563 |
{AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit}, |
9563 |
{AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit}, |
| 9564 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9564 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9565 |
// (JIC64 GPR64Opnd:$rs, 0) - 981 |
9565 |
// (JIC64 GPR64Opnd:$rs, 0) - 981 |
| 9566 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
9566 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 9567 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9567 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9568 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9568 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9569 |
{AliasPatternCond::K_Feature, Mips::FeatureMips64r6}, |
9569 |
{AliasPatternCond::K_Feature, Mips::FeatureMips64r6}, |
| 9570 |
// (MOVE16_MM ZERO, ZERO) - 985 |
9570 |
// (MOVE16_MM ZERO, ZERO) - 985 |
| 9571 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9571 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9572 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9572 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9573 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9573 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9574 |
// (Move32R16 ZERO, S0) - 988 |
9574 |
// (Move32R16 ZERO, S0) - 988 |
| 9575 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9575 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9576 |
{AliasPatternCond::K_Reg, Mips::S0}, |
9576 |
{AliasPatternCond::K_Reg, Mips::S0}, |
| 9577 |
{AliasPatternCond::K_Feature, Mips::FeatureMips16}, |
9577 |
{AliasPatternCond::K_Feature, Mips::FeatureMips16}, |
| 9578 |
// (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 991 |
9578 |
// (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 991 |
| 9579 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9579 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9580 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9580 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9581 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9581 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9582 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9582 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9583 |
{AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit}, |
9583 |
{AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit}, |
| 9584 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9584 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9585 |
// (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 997 |
9585 |
// (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 997 |
| 9586 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
9586 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 9587 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
9587 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 9588 |
{AliasPatternCond::K_Reg, Mips::ZERO_64}, |
9588 |
{AliasPatternCond::K_Reg, Mips::ZERO_64}, |
| 9589 |
{AliasPatternCond::K_Feature, Mips::FeatureGP64Bit}, |
9589 |
{AliasPatternCond::K_Feature, Mips::FeatureGP64Bit}, |
| 9590 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9590 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9591 |
// (RDHWR GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1002 |
9591 |
// (RDHWR GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1002 |
| 9592 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9592 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9593 |
{AliasPatternCond::K_RegClass, Mips::HWRegsRegClassID}, |
9593 |
{AliasPatternCond::K_RegClass, Mips::HWRegsRegClassID}, |
| 9594 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9594 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9595 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9595 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9596 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9596 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9597 |
// (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0) - 1007 |
9597 |
// (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0) - 1007 |
| 9598 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
9598 |
{AliasPatternCond::K_RegClass, Mips::GPR64RegClassID}, |
| 9599 |
{AliasPatternCond::K_RegClass, Mips::HWRegsRegClassID}, |
9599 |
{AliasPatternCond::K_RegClass, Mips::HWRegsRegClassID}, |
| 9600 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9600 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9601 |
{AliasPatternCond::K_Feature, Mips::FeatureGP64Bit}, |
9601 |
{AliasPatternCond::K_Feature, Mips::FeatureGP64Bit}, |
| 9602 |
// (RDHWR_MM GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1011 |
9602 |
// (RDHWR_MM GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1011 |
| 9603 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9603 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9604 |
{AliasPatternCond::K_RegClass, Mips::HWRegsRegClassID}, |
9604 |
{AliasPatternCond::K_RegClass, Mips::HWRegsRegClassID}, |
| 9605 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9605 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9606 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9606 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9607 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9607 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9608 |
// (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1016 |
9608 |
// (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1016 |
| 9609 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9609 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9610 |
{AliasPatternCond::K_RegClass, Mips::HWRegsRegClassID}, |
9610 |
{AliasPatternCond::K_RegClass, Mips::HWRegsRegClassID}, |
| 9611 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9611 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9612 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9612 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9613 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9613 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9614 |
// (SDBBP 0) - 1021 |
9614 |
// (SDBBP 0) - 1021 |
| 9615 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9615 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9616 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9616 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9617 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32}, |
9617 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32}, |
| 9618 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9618 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9619 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
9619 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6}, |
| 9620 |
// (SDBBP_MMR6 0) - 1026 |
9620 |
// (SDBBP_MMR6 0) - 1026 |
| 9621 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9621 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9622 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9622 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9623 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9623 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9624 |
// (SDBBP_R6 0) - 1029 |
9624 |
// (SDBBP_R6 0) - 1029 |
| 9625 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9625 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9626 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9626 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9627 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9627 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9628 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9628 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9629 |
// (SIGRIE 0) - 1033 |
9629 |
// (SIGRIE 0) - 1033 |
| 9630 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9630 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9631 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9631 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9632 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9632 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9633 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9633 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9634 |
// (SIGRIE_MMR6 0) - 1037 |
9634 |
// (SIGRIE_MMR6 0) - 1037 |
| 9635 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9635 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9636 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9636 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9637 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9637 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9638 |
// (SLL ZERO, ZERO, 0) - 1040 |
9638 |
// (SLL ZERO, ZERO, 0) - 1040 |
| 9639 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9639 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9640 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9640 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9641 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9641 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9642 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9642 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9643 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9643 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9644 |
// (SLL_MM ZERO, ZERO, 0) - 1045 |
9644 |
// (SLL_MM ZERO, ZERO, 0) - 1045 |
| 9645 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9645 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9646 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9646 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9647 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9647 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9648 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9648 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9649 |
// (SLL_MMR6 ZERO, ZERO, 0) - 1049 |
9649 |
// (SLL_MMR6 ZERO, ZERO, 0) - 1049 |
| 9650 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9650 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9651 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9651 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9652 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9652 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9653 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9653 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9654 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9654 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9655 |
// (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1054 |
9655 |
// (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1054 |
| 9656 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9656 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9657 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9657 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9658 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9658 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9659 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9659 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9660 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9660 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9661 |
// (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1059 |
9661 |
// (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1059 |
| 9662 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9662 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9663 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9663 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9664 |
{AliasPatternCond::K_TiedReg, 0}, |
9664 |
{AliasPatternCond::K_TiedReg, 0}, |
| 9665 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9665 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9666 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9666 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9667 |
// (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1064 |
9667 |
// (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1064 |
| 9668 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9668 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9669 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9669 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9670 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9670 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9671 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9671 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9672 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9672 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9673 |
// (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1069 |
9673 |
// (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1069 |
| 9674 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9674 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9675 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9675 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9676 |
{AliasPatternCond::K_TiedReg, 0}, |
9676 |
{AliasPatternCond::K_TiedReg, 0}, |
| 9677 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9677 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9678 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9678 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9679 |
// (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1074 |
9679 |
// (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1074 |
| 9680 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9680 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9681 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9681 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9682 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9682 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9683 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9683 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9684 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9684 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9685 |
// (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1079 |
9685 |
// (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1079 |
| 9686 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9686 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9687 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9687 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9688 |
{AliasPatternCond::K_TiedReg, 0}, |
9688 |
{AliasPatternCond::K_TiedReg, 0}, |
| 9689 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9689 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9690 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9690 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9691 |
// (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1084 |
9691 |
// (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1084 |
| 9692 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9692 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9693 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9693 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9694 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9694 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9695 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9695 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9696 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9696 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9697 |
// (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1089 |
9697 |
// (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1089 |
| 9698 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9698 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9699 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9699 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9700 |
{AliasPatternCond::K_TiedReg, 0}, |
9700 |
{AliasPatternCond::K_TiedReg, 0}, |
| 9701 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9701 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9702 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9702 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9703 |
// (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1094 |
9703 |
// (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1094 |
| 9704 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9704 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9705 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9705 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9706 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9706 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9707 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9707 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9708 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9708 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9709 |
// (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1099 |
9709 |
// (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1099 |
| 9710 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9710 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9711 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9711 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9712 |
{AliasPatternCond::K_TiedReg, 0}, |
9712 |
{AliasPatternCond::K_TiedReg, 0}, |
| 9713 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9713 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9714 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9714 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9715 |
// (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1104 |
9715 |
// (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1104 |
| 9716 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9716 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9717 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9717 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9718 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9718 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9719 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9719 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9720 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9720 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9721 |
// (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1109 |
9721 |
// (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1109 |
| 9722 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9722 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9723 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9723 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9724 |
{AliasPatternCond::K_TiedReg, 0}, |
9724 |
{AliasPatternCond::K_TiedReg, 0}, |
| 9725 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9725 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9726 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
9726 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6}, |
| 9727 |
// (SWSP_MM GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset) - 1114 |
9727 |
// (SWSP_MM GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset) - 1114 |
| 9728 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9728 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9729 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9729 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9730 |
// (SYNC 0) - 1116 |
9730 |
// (SYNC 0) - 1116 |
| 9731 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9731 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9732 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9732 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9733 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
9733 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
| 9734 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9734 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9735 |
// (SYNC_MM 0) - 1120 |
9735 |
// (SYNC_MM 0) - 1120 |
| 9736 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9736 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9737 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9737 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9738 |
// (SYNC_MMR6 0) - 1122 |
9738 |
// (SYNC_MMR6 0) - 1122 |
| 9739 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9739 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9740 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9740 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9741 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
9741 |
{AliasPatternCond::K_Feature, Mips::FeatureMips32r6}, |
| 9742 |
// (SYSCALL 0) - 1125 |
9742 |
// (SYSCALL 0) - 1125 |
| 9743 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9743 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9744 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9744 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9745 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9745 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9746 |
// (SYSCALL_MM 0) - 1128 |
9746 |
// (SYSCALL_MM 0) - 1128 |
| 9747 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9747 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9748 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9748 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9749 |
// (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1130 |
9749 |
// (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1130 |
| 9750 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9750 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9751 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9751 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9752 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9752 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9753 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9753 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9754 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
9754 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
| 9755 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9755 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9756 |
// (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1136 |
9756 |
// (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1136 |
| 9757 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9757 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9758 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9758 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9759 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9759 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9760 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9760 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9761 |
// (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1140 |
9761 |
// (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1140 |
| 9762 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9762 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9763 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9763 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9764 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9764 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9765 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9765 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9766 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
9766 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
| 9767 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9767 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9768 |
// (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1146 |
9768 |
// (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1146 |
| 9769 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9769 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9770 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9770 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9771 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9771 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9772 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9772 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9773 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
9773 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
| 9774 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9774 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9775 |
// (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1152 |
9775 |
// (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1152 |
| 9776 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9776 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9777 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9777 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9778 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9778 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9779 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9779 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9780 |
// (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1156 |
9780 |
// (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1156 |
| 9781 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9781 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9782 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9782 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9783 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9783 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9784 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9784 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9785 |
// (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1160 |
9785 |
// (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1160 |
| 9786 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9786 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9787 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9787 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9788 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9788 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9789 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9789 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9790 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
9790 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
| 9791 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9791 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9792 |
// (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1166 |
9792 |
// (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1166 |
| 9793 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9793 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9794 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9794 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9795 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9795 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9796 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9796 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9797 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
9797 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
| 9798 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9798 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9799 |
// (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1172 |
9799 |
// (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1172 |
| 9800 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9800 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9801 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9801 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9802 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9802 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9803 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9803 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9804 |
// (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1176 |
9804 |
// (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1176 |
| 9805 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9805 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9806 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9806 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9807 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9807 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9808 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9808 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9809 |
// (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1180 |
9809 |
// (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1180 |
| 9810 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9810 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9811 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9811 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9812 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9812 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9813 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
9813 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMips16}, |
| 9814 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
9814 |
{AliasPatternCond::K_Feature, Mips::FeatureMips2}, |
| 9815 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9815 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9816 |
// (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1186 |
9816 |
// (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1186 |
| 9817 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9817 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9818 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9818 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9819 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9819 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9820 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9820 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9821 |
// (WAIT_MM 0) - 1190 |
9821 |
// (WAIT_MM 0) - 1190 |
| 9822 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
9822 |
{AliasPatternCond::K_Imm, uint32_t(0)}, |
| 9823 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9823 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9824 |
// (WRDSP GPR32Opnd:$rt, 31) - 1192 |
9824 |
// (WRDSP GPR32Opnd:$rt, 31) - 1192 |
| 9825 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9825 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9826 |
{AliasPatternCond::K_Imm, uint32_t(31)}, |
9826 |
{AliasPatternCond::K_Imm, uint32_t(31)}, |
| 9827 |
{AliasPatternCond::K_Feature, Mips::FeatureDSP}, |
9827 |
{AliasPatternCond::K_Feature, Mips::FeatureDSP}, |
| 9828 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9828 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9829 |
// (WRDSP_MM GPR32Opnd:$rt, 31) - 1196 |
9829 |
// (WRDSP_MM GPR32Opnd:$rt, 31) - 1196 |
| 9830 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9830 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9831 |
{AliasPatternCond::K_Imm, uint32_t(31)}, |
9831 |
{AliasPatternCond::K_Imm, uint32_t(31)}, |
| 9832 |
{AliasPatternCond::K_Feature, Mips::FeatureDSP}, |
9832 |
{AliasPatternCond::K_Feature, Mips::FeatureDSP}, |
| 9833 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
9833 |
{AliasPatternCond::K_Feature, Mips::FeatureMicroMips}, |
| 9834 |
// (YIELD ZERO, GPR32Opnd:$rs) - 1200 |
9834 |
// (YIELD ZERO, GPR32Opnd:$rs) - 1200 |
| 9835 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
9835 |
{AliasPatternCond::K_Reg, Mips::ZERO}, |
| 9836 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
9836 |
{AliasPatternCond::K_RegClass, Mips::GPR32RegClassID}, |
| 9837 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
9837 |
{AliasPatternCond::K_Feature, Mips::FeatureMT}, |
| 9838 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
9838 |
{AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips}, |
| 9839 |
}; |
9839 |
}; |
| 9840 |
|
9840 |
|
| 9841 |
static const char AsmStrings[] = |
9841 |
static const char AsmStrings[] = |
| 9842 |
/* 0 */ "mftacx $\x01\0" |
9842 |
/* 0 */ "mftacx $\x01\0" |
| 9843 |
/* 10 */ "mftc0 $\x01, $\x02\0" |
9843 |
/* 10 */ "mftc0 $\x01, $\x02\0" |
| 9844 |
/* 23 */ "mfthi $\x01\0" |
9844 |
/* 23 */ "mfthi $\x01\0" |
| 9845 |
/* 32 */ "mftlo $\x01\0" |
9845 |
/* 32 */ "mftlo $\x01\0" |
| 9846 |
/* 41 */ "mttacx $\x02\0" |
9846 |
/* 41 */ "mttacx $\x02\0" |
| 9847 |
/* 51 */ "mttc0 $\x02, $\x01\0" |
9847 |
/* 51 */ "mttc0 $\x02, $\x01\0" |
| 9848 |
/* 64 */ "mtthi $\x02\0" |
9848 |
/* 64 */ "mtthi $\x02\0" |
| 9849 |
/* 73 */ "mttlo $\x02\0" |
9849 |
/* 73 */ "mttlo $\x02\0" |
| 9850 |
/* 82 */ "nor $\x01, $\x03\0" |
9850 |
/* 82 */ "nor $\x01, $\x03\0" |
| 9851 |
/* 93 */ "slt $\x01, $\x03\0" |
9851 |
/* 93 */ "slt $\x01, $\x03\0" |
| 9852 |
/* 104 */ "sltu $\x01, $\x03\0" |
9852 |
/* 104 */ "sltu $\x01, $\x03\0" |
| 9853 |
/* 116 */ "lapc $\x01, $\x02\0" |
9853 |
/* 116 */ "lapc $\x01, $\x02\0" |
| 9854 |
/* 128 */ "move $\x01, $\x02\0" |
9854 |
/* 128 */ "move $\x01, $\x02\0" |
| 9855 |
/* 140 */ "bc1f $\xFF\x02\x01\0" |
9855 |
/* 140 */ "bc1f $\xFF\x02\x01\0" |
| 9856 |
/* 150 */ "bc1fl $\xFF\x02\x01\0" |
9856 |
/* 150 */ "bc1fl $\xFF\x02\x01\0" |
| 9857 |
/* 161 */ "bc1t $\xFF\x02\x01\0" |
9857 |
/* 161 */ "bc1t $\xFF\x02\x01\0" |
| 9858 |
/* 171 */ "bc1tl $\xFF\x02\x01\0" |
9858 |
/* 171 */ "bc1tl $\xFF\x02\x01\0" |
| 9859 |
/* 182 */ "beqzl $\x01, $\xFF\x03\x01\0" |
9859 |
/* 182 */ "beqzl $\x01, $\xFF\x03\x01\0" |
| 9860 |
/* 197 */ "bal $\xFF\x02\x01\0" |
9860 |
/* 197 */ "bal $\xFF\x02\x01\0" |
| 9861 |
/* 206 */ "bnezl $\x01, $\xFF\x03\x01\0" |
9861 |
/* 206 */ "bnezl $\x01, $\xFF\x03\x01\0" |
| 9862 |
/* 221 */ "break\0" |
9862 |
/* 221 */ "break\0" |
| 9863 |
/* 227 */ "break $\xFF\x01\x02\0" |
9863 |
/* 227 */ "break $\xFF\x01\x02\0" |
| 9864 |
/* 238 */ "c.eq.d $\x02, $\x03\0" |
9864 |
/* 238 */ "c.eq.d $\x02, $\x03\0" |
| 9865 |
/* 252 */ "c.eq.s $\x02, $\x03\0" |
9865 |
/* 252 */ "c.eq.s $\x02, $\x03\0" |
| 9866 |
/* 266 */ "c.f.d $\x02, $\x03\0" |
9866 |
/* 266 */ "c.f.d $\x02, $\x03\0" |
| 9867 |
/* 279 */ "c.f.s $\x02, $\x03\0" |
9867 |
/* 279 */ "c.f.s $\x02, $\x03\0" |
| 9868 |
/* 292 */ "c.le.d $\x02, $\x03\0" |
9868 |
/* 292 */ "c.le.d $\x02, $\x03\0" |
| 9869 |
/* 306 */ "c.le.s $\x02, $\x03\0" |
9869 |
/* 306 */ "c.le.s $\x02, $\x03\0" |
| 9870 |
/* 320 */ "c.lt.d $\x02, $\x03\0" |
9870 |
/* 320 */ "c.lt.d $\x02, $\x03\0" |
| 9871 |
/* 334 */ "c.lt.s $\x02, $\x03\0" |
9871 |
/* 334 */ "c.lt.s $\x02, $\x03\0" |
| 9872 |
/* 348 */ "c.nge.d $\x02, $\x03\0" |
9872 |
/* 348 */ "c.nge.d $\x02, $\x03\0" |
| 9873 |
/* 363 */ "c.nge.s $\x02, $\x03\0" |
9873 |
/* 363 */ "c.nge.s $\x02, $\x03\0" |
| 9874 |
/* 378 */ "c.ngle.d $\x02, $\x03\0" |
9874 |
/* 378 */ "c.ngle.d $\x02, $\x03\0" |
| 9875 |
/* 394 */ "c.ngle.s $\x02, $\x03\0" |
9875 |
/* 394 */ "c.ngle.s $\x02, $\x03\0" |
| 9876 |
/* 410 */ "c.ngl.d $\x02, $\x03\0" |
9876 |
/* 410 */ "c.ngl.d $\x02, $\x03\0" |
| 9877 |
/* 425 */ "c.ngl.s $\x02, $\x03\0" |
9877 |
/* 425 */ "c.ngl.s $\x02, $\x03\0" |
| 9878 |
/* 440 */ "c.ngt.d $\x02, $\x03\0" |
9878 |
/* 440 */ "c.ngt.d $\x02, $\x03\0" |
| 9879 |
/* 455 */ "c.ngt.s $\x02, $\x03\0" |
9879 |
/* 455 */ "c.ngt.s $\x02, $\x03\0" |
| 9880 |
/* 470 */ "c.ole.d $\x02, $\x03\0" |
9880 |
/* 470 */ "c.ole.d $\x02, $\x03\0" |
| 9881 |
/* 485 */ "c.ole.s $\x02, $\x03\0" |
9881 |
/* 485 */ "c.ole.s $\x02, $\x03\0" |
| 9882 |
/* 500 */ "c.olt.d $\x02, $\x03\0" |
9882 |
/* 500 */ "c.olt.d $\x02, $\x03\0" |
| 9883 |
/* 515 */ "c.olt.s $\x02, $\x03\0" |
9883 |
/* 515 */ "c.olt.s $\x02, $\x03\0" |
| 9884 |
/* 530 */ "c.seq.d $\x02, $\x03\0" |
9884 |
/* 530 */ "c.seq.d $\x02, $\x03\0" |
| 9885 |
/* 545 */ "c.seq.s $\x02, $\x03\0" |
9885 |
/* 545 */ "c.seq.s $\x02, $\x03\0" |
| 9886 |
/* 560 */ "c.sf.d $\x02, $\x03\0" |
9886 |
/* 560 */ "c.sf.d $\x02, $\x03\0" |
| 9887 |
/* 574 */ "c.sf.s $\x02, $\x03\0" |
9887 |
/* 574 */ "c.sf.s $\x02, $\x03\0" |
| 9888 |
/* 588 */ "c.ueq.d $\x02, $\x03\0" |
9888 |
/* 588 */ "c.ueq.d $\x02, $\x03\0" |
| 9889 |
/* 603 */ "c.ueq.s $\x02, $\x03\0" |
9889 |
/* 603 */ "c.ueq.s $\x02, $\x03\0" |
| 9890 |
/* 618 */ "c.ule.d $\x02, $\x03\0" |
9890 |
/* 618 */ "c.ule.d $\x02, $\x03\0" |
| 9891 |
/* 633 */ "c.ule.s $\x02, $\x03\0" |
9891 |
/* 633 */ "c.ule.s $\x02, $\x03\0" |
| 9892 |
/* 648 */ "c.ult.d $\x02, $\x03\0" |
9892 |
/* 648 */ "c.ult.d $\x02, $\x03\0" |
| 9893 |
/* 663 */ "c.ult.s $\x02, $\x03\0" |
9893 |
/* 663 */ "c.ult.s $\x02, $\x03\0" |
| 9894 |
/* 678 */ "c.un.d $\x02, $\x03\0" |
9894 |
/* 678 */ "c.un.d $\x02, $\x03\0" |
| 9895 |
/* 692 */ "c.un.s $\x02, $\x03\0" |
9895 |
/* 692 */ "c.un.s $\x02, $\x03\0" |
| 9896 |
/* 706 */ "di\0" |
9896 |
/* 706 */ "di\0" |
| 9897 |
/* 709 */ "div $\x01, $\x03\0" |
9897 |
/* 709 */ "div $\x01, $\x03\0" |
| 9898 |
/* 720 */ "divu $\x01, $\x03\0" |
9898 |
/* 720 */ "divu $\x01, $\x03\0" |
| 9899 |
/* 732 */ "dmt\0" |
9899 |
/* 732 */ "dmt\0" |
| 9900 |
/* 736 */ "dneg $\x01, $\x03\0" |
9900 |
/* 736 */ "dneg $\x01, $\x03\0" |
| 9901 |
/* 748 */ "dneg $\x01\0" |
9901 |
/* 748 */ "dneg $\x01\0" |
| 9902 |
/* 756 */ "dnegu $\x01, $\x03\0" |
9902 |
/* 756 */ "dnegu $\x01, $\x03\0" |
| 9903 |
/* 769 */ "dnegu $\x01\0" |
9903 |
/* 769 */ "dnegu $\x01\0" |
| 9904 |
/* 778 */ "dvpe\0" |
9904 |
/* 778 */ "dvpe\0" |
| 9905 |
/* 783 */ "ei\0" |
9905 |
/* 783 */ "ei\0" |
| 9906 |
/* 786 */ "emt\0" |
9906 |
/* 786 */ "emt\0" |
| 9907 |
/* 790 */ "evpe\0" |
9907 |
/* 790 */ "evpe\0" |
| 9908 |
/* 795 */ "hypcall\0" |
9908 |
/* 795 */ "hypcall\0" |
| 9909 |
/* 803 */ "jr $\x02\0" |
9909 |
/* 803 */ "jr $\x02\0" |
| 9910 |
/* 809 */ "jalrc.hb $\x02\0" |
9910 |
/* 809 */ "jalrc.hb $\x02\0" |
| 9911 |
/* 821 */ "jalrc $\x02\0" |
9911 |
/* 821 */ "jalrc $\x02\0" |
| 9912 |
/* 830 */ "jalr.hb $\x02\0" |
9912 |
/* 830 */ "jalr.hb $\x02\0" |
| 9913 |
/* 841 */ "jalrc $\x01\0" |
9913 |
/* 841 */ "jalrc $\x01\0" |
| 9914 |
/* 850 */ "jrc $\x01\0" |
9914 |
/* 850 */ "jrc $\x01\0" |
| 9915 |
/* 857 */ "nop\0" |
9915 |
/* 857 */ "nop\0" |
| 9916 |
/* 861 */ "rdhwr $\x01, $\x02\0" |
9916 |
/* 861 */ "rdhwr $\x01, $\x02\0" |
| 9917 |
/* 874 */ "sdbbp\0" |
9917 |
/* 874 */ "sdbbp\0" |
| 9918 |
/* 880 */ "sigrie\0" |
9918 |
/* 880 */ "sigrie\0" |
| 9919 |
/* 887 */ "neg $\x01, $\x03\0" |
9919 |
/* 887 */ "neg $\x01, $\x03\0" |
| 9920 |
/* 898 */ "neg $\x01\0" |
9920 |
/* 898 */ "neg $\x01\0" |
| 9921 |
/* 905 */ "negu $\x01, $\x03\0" |
9921 |
/* 905 */ "negu $\x01, $\x03\0" |
| 9922 |
/* 917 */ "negu $\x01\0" |
9922 |
/* 917 */ "negu $\x01\0" |
| 9923 |
/* 925 */ "sw $\x01, $\xFF\x02\x03\0" |
9923 |
/* 925 */ "sw $\x01, $\xFF\x02\x03\0" |
| 9924 |
/* 937 */ "sync\0" |
9924 |
/* 937 */ "sync\0" |
| 9925 |
/* 942 */ "syscall\0" |
9925 |
/* 942 */ "syscall\0" |
| 9926 |
/* 950 */ "teq $\x01, $\x02\0" |
9926 |
/* 950 */ "teq $\x01, $\x02\0" |
| 9927 |
/* 961 */ "tge $\x01, $\x02\0" |
9927 |
/* 961 */ "tge $\x01, $\x02\0" |
| 9928 |
/* 972 */ "tgeu $\x01, $\x02\0" |
9928 |
/* 972 */ "tgeu $\x01, $\x02\0" |
| 9929 |
/* 984 */ "tlt $\x01, $\x02\0" |
9929 |
/* 984 */ "tlt $\x01, $\x02\0" |
| 9930 |
/* 995 */ "tltu $\x01, $\x02\0" |
9930 |
/* 995 */ "tltu $\x01, $\x02\0" |
| 9931 |
/* 1007 */ "tne $\x01, $\x02\0" |
9931 |
/* 1007 */ "tne $\x01, $\x02\0" |
| 9932 |
/* 1018 */ "wait\0" |
9932 |
/* 1018 */ "wait\0" |
| 9933 |
/* 1023 */ "wrdsp $\x01\0" |
9933 |
/* 1023 */ "wrdsp $\x01\0" |
| 9934 |
/* 1032 */ "yield $\x02\0" |
9934 |
/* 1032 */ "yield $\x02\0" |
| 9935 |
; |
9935 |
; |
| 9936 |
|
9936 |
|
| 9937 |
#ifndef NDEBUG |
9937 |
#ifndef NDEBUG |
| 9938 |
static struct SortCheck { |
9938 |
static struct SortCheck { |
| 9939 |
SortCheck(ArrayRef OpToPatterns) { |
9939 |
SortCheck(ArrayRef OpToPatterns) { |
| 9940 |
assert(std::is_sorted( |
9940 |
assert(std::is_sorted( |
| 9941 |
OpToPatterns.begin(), OpToPatterns.end(), |
9941 |
OpToPatterns.begin(), OpToPatterns.end(), |
| 9942 |
[](const PatternsForOpcode &L, const PatternsForOpcode &R) { |
9942 |
[](const PatternsForOpcode &L, const PatternsForOpcode &R) { |
| 9943 |
return L.Opcode < R.Opcode; |
9943 |
return L.Opcode < R.Opcode; |
| 9944 |
}) && |
9944 |
}) && |
| 9945 |
"tablegen failed to sort opcode patterns"); |
9945 |
"tablegen failed to sort opcode patterns"); |
| 9946 |
} |
9946 |
} |
| 9947 |
} sortCheckVar(OpToPatterns); |
9947 |
} sortCheckVar(OpToPatterns); |
| 9948 |
#endif |
9948 |
#endif |
| 9949 |
|
9949 |
|
| 9950 |
AliasMatchingData M { |
9950 |
AliasMatchingData M { |
| 9951 |
ArrayRef(OpToPatterns), |
9951 |
ArrayRef(OpToPatterns), |
| 9952 |
ArrayRef(Patterns), |
9952 |
ArrayRef(Patterns), |
| 9953 |
ArrayRef(Conds), |
9953 |
ArrayRef(Conds), |
| 9954 |
StringRef(AsmStrings, std::size(AsmStrings)), |
9954 |
StringRef(AsmStrings, std::size(AsmStrings)), |
| 9955 |
nullptr, |
9955 |
nullptr, |
| 9956 |
}; |
9956 |
}; |
| 9957 |
const char *AsmString = matchAliasPatterns(MI, &STI, M); |
9957 |
const char *AsmString = matchAliasPatterns(MI, &STI, M); |
| 9958 |
if (!AsmString) return false; |
9958 |
if (!AsmString) return false; |
| 9959 |
|
9959 |
|
| 9960 |
unsigned I = 0; |
9960 |
unsigned I = 0; |
| 9961 |
while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
9961 |
while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
| 9962 |
AsmString[I] != '$' && AsmString[I] != '\0') |
9962 |
AsmString[I] != '$' && AsmString[I] != '\0') |
| 9963 |
++I; |
9963 |
++I; |
| 9964 |
OS << '\t' << StringRef(AsmString, I); |
9964 |
OS << '\t' << StringRef(AsmString, I); |
| 9965 |
if (AsmString[I] != '\0') { |
9965 |
if (AsmString[I] != '\0') { |
| 9966 |
if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
9966 |
if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
| 9967 |
OS << '\t'; |
9967 |
OS << '\t'; |
| 9968 |
++I; |
9968 |
++I; |
| 9969 |
} |
9969 |
} |
| 9970 |
do { |
9970 |
do { |
| 9971 |
if (AsmString[I] == '$') { |
9971 |
if (AsmString[I] == '$') { |
| 9972 |
++I; |
9972 |
++I; |
| 9973 |
if (AsmString[I] == (char)0xff) { |
9973 |
if (AsmString[I] == (char)0xff) { |
| 9974 |
++I; |
9974 |
++I; |
| 9975 |
int OpIdx = AsmString[I++] - 1; |
9975 |
int OpIdx = AsmString[I++] - 1; |
| 9976 |
int PrintMethodIdx = AsmString[I++] - 1; |
9976 |
int PrintMethodIdx = AsmString[I++] - 1; |
| 9977 |
printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, OS); |
9977 |
printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, OS); |
| 9978 |
} else |
9978 |
} else |
| 9979 |
printOperand(MI, unsigned(AsmString[I++]) - 1, STI, OS); |
9979 |
printOperand(MI, unsigned(AsmString[I++]) - 1, STI, OS); |
| 9980 |
} else { |
9980 |
} else { |
| 9981 |
OS << AsmString[I++]; |
9981 |
OS << AsmString[I++]; |
| 9982 |
} |
9982 |
} |
| 9983 |
} while (AsmString[I] != '\0'); |
9983 |
} while (AsmString[I] != '\0'); |
| 9984 |
} |
9984 |
} |
| 9985 |
|
9985 |
|
| 9986 |
return true; |
9986 |
return true; |
| 9987 |
} |
9987 |
} |
| 9988 |
|
9988 |
|
| 9989 |
void MipsInstPrinter::printCustomAliasOperand( |
9989 |
void MipsInstPrinter::printCustomAliasOperand( |
| 9990 |
const MCInst *MI, uint64_t Address, unsigned OpIdx, |
9990 |
const MCInst *MI, uint64_t Address, unsigned OpIdx, |
| 9991 |
unsigned PrintMethodIdx, |
9991 |
unsigned PrintMethodIdx, |
| 9992 |
const MCSubtargetInfo &STI, |
9992 |
const MCSubtargetInfo &STI, |
| 9993 |
raw_ostream &OS) { |
9993 |
raw_ostream &OS) { |
| 9994 |
switch (PrintMethodIdx) { |
9994 |
switch (PrintMethodIdx) { |
| 9995 |
default: |
9995 |
default: |
| 9996 |
llvm_unreachable("Unknown PrintMethod kind"); |
9996 |
llvm_unreachable("Unknown PrintMethod kind"); |
| 9997 |
break; |
9997 |
break; |
| 9998 |
case 0: |
9998 |
case 0: |
| 9999 |
printBranchOperand(MI, Address, OpIdx, STI, OS); |
9999 |
printBranchOperand(MI, Address, OpIdx, STI, OS); |
| 10000 |
break; |
10000 |
break; |
| 10001 |
case 1: |
10001 |
case 1: |
| 10002 |
printUImm<10>(MI, OpIdx, STI, OS); |
10002 |
printUImm<10>(MI, OpIdx, STI, OS); |
| 10003 |
break; |
10003 |
break; |
| 10004 |
case 2: |
10004 |
case 2: |
| 10005 |
printMemOperand(MI, OpIdx, STI, OS); |
10005 |
printMemOperand(MI, OpIdx, STI, OS); |
| 10006 |
break; |
10006 |
break; |
| 10007 |
} |
10007 |
} |
| 10008 |
} |
10008 |
} |
| 10009 |
|
10009 |
|
| 10010 |
#endif // PRINT_ALIAS_INSTR |
10010 |
#endif // PRINT_ALIAS_INSTR |
| 10011 |
|
10011 |
|